TW201521169A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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Publication number
TW201521169A
TW201521169A TW103117092A TW103117092A TW201521169A TW 201521169 A TW201521169 A TW 201521169A TW 103117092 A TW103117092 A TW 103117092A TW 103117092 A TW103117092 A TW 103117092A TW 201521169 A TW201521169 A TW 201521169A
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Taiwan
Prior art keywords
substrate
pads
liner
pad
recess
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TW103117092A
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English (en)
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TWI620295B (zh
Inventor
Jie Chen
Ying-Ju Chen
Hsien-Wei Chen
Tsung-Yuan Yu
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Taiwan Semiconductor Mfg
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Publication of TW201521169A publication Critical patent/TW201521169A/zh
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Publication of TWI620295B publication Critical patent/TWI620295B/zh

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Abstract

一種半導體元件，其包含一基板，其包括一表面；複數個襯墊，其配置於該基板之該表面上；該複數個襯墊包括一非阻焊層限定(NSMD)襯墊及一阻焊層限定(SMD)襯墊，且該NSMD襯墊係經安置於一預定位置。此外，一種用於製造一半導體元件之方法，其包括提供一基板，將複數個襯墊配置於該基板之該表面上，將一阻焊層覆於該基板之該表面及該複數個襯墊上，在該阻焊層中形成一第一凹陷以圍繞該複數個襯墊，以及在該阻焊層中且在該複數個襯墊之一者上形成一第二凹陷。

Description

半導體元件及其製造方法
本揭露關於半導體元件及製造半導體元件之方法。
涉及數個半導體元件的電子設備於吾人日常生活係不可缺少的。隨著電子技術的進步，電子設備已成為尺寸較小且必須執行且運行越來越多的複雜及多項功能。因此，電子設備成為涉及數個電子部件更緊密，且成為在如此小區域內涉及高密度輸入/輸出(I/O)端子之結構上更複雜。
晶圓層級封裝(WLP)技術已日益普及。此種技術提供在小尺寸半導體元件的情況下，具有高功能及高效能的半導體元件的晶圓層級製造。在半導體元件的製造期間，採用表面安裝技術(SMT)以將半導體元件小型化。半導體援建包括安裝在另一基板之基板，以使透過一焊球將基板的襯墊與另一基板的襯墊黏合並電連接。
基板的襯墊係藉由多個方法形成在基板的頂部表面上。然而，由不同方法形成的襯墊相對於掉落測試、熱循環、彎曲等可能提供不同的可靠度。例如，有些襯墊可能有能力承受高應力水平，而因此不會輕易地產生裂縫，而有些襯墊可能有能力承受高溫度，而因此自基板的剝離係最小化。
因此，存在對改善基板上之襯墊的組態及製造襯墊的操作以最 佳化的襯墊可靠度和解決上述缺陷的持續需求。
在表面安裝技術(SMT)中，半導體元件包括至少二個基板。透過例如焊接點或焊接凸部的導電凸部，以藉由附接基板的襯墊至另一基板的襯墊的方式，而將一基板堆疊在另一基板上。藉由將導電材料濺射或電鍍至基板上來形成基板的襯墊，使得襯墊導通在基板的電路與在該基板外部的另一基板之間的電力。隨後，焊接材料覆蓋基板的襯墊以選擇性地暴露襯墊的頂部表面。可藉由各種方法暴露襯墊，其定義為了容納凸部之襯墊之頂部表面的區域。隨後將襯墊的暴露表面與凸部附接。
然而，上述基板上的襯墊之組態有一些問題，例如襯墊與基板間的附著力減少、於機械測試(如板彎曲或掉落測試)之低可靠度、在襯墊週邊的應力集中、在板層級溫度循環之低可靠度等等。因為以不同方法形成及暴露襯墊具有不同的問題，最終基板整體可能會有低可靠度及低功能效能。
以下詳細探討本發明之實施例之製造與使用。然而，應當理解此些實施例提供很多可應用的進步性概念，其可在各種各樣的特定情境下體現。應當理解以下揭示提供很多不同實施例或實例以實現各種實施例的不同特徵。以下敘述部件及安置的特定實例以簡化本揭示。當然這些僅為實例並且不旨在於限制。
以下使用特定語言揭示在圖式中顯示的實施例或實例。然而應當理解這些實施例或實例並不旨在於限制。對所揭示實施例之任何改變及修改以及本文所揭示任何進一步原理之應用可預期對本案所屬領域具有通常知識者可正常進行。
此外，應當理解元件的數個處理步驟及/或特徵僅會簡要描述。另外，可附加額外處理步驟及/或特徵，且在實作請求項時，可移除 或更改以下特定的處理步驟及/或特徵。因此，應當理解以下敘述僅代表實例，而非旨於建議需要一或多個步驟或特徵。
除此之外，本揭示在各種例子會重複使用元件符號及/或字母。此種重複係為了簡要及清楚起見，而其本身並未決定所探討之各種實施例及/或組態間的關係。
在本揭示中，揭示一種具有經改良組態的半導體元件。該半導體元件包括一基板及數個在該基板上的襯墊，其係阻焊層限定(SMD)襯墊及非阻焊層限定(NSMD)襯墊之組合，以使得SMD襯墊與NSMD襯墊的缺點係可彌補的，因此作為一個整體的基板具備SMD襯墊與NSMD襯墊所貢獻的優點，例如對於板層級溫度循環的高可靠度、掉落測試的良好效能、應力集中點數目的減少等等。
100‧‧‧半導體元件
101‧‧‧基板
101a‧‧‧表面
101b‧‧‧角落
101c‧‧‧空區域
102‧‧‧襯墊
102-1‧‧‧NSMD襯墊
102-2‧‧‧SMD襯墊
102a‧‧‧頂部表面
102b‧‧‧周圍部分
103‧‧‧阻焊層
103a‧‧‧頂部表面
103b‧‧‧第一凹陷部分/第一凹陷
103c‧‧‧第二凹陷部分/第二凹陷
103e‧‧‧側壁
104‧‧‧間隙
105‧‧‧圓
200‧‧‧半導體元件
300‧‧‧方法
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本揭示之態樣係最好在閱讀附圖時從以下詳細敘述理解。要強調的是，根據產業中的標準實務，各種特徵並非按比例繪製。事實上，各種特徵的維度可能會為了探討清楚而任意增加或減少。
圖1A係根據本揭示的一些實施例之具有非阻焊層限定(NSMD)襯墊之半導體元件的示意圖。
圖1B係根據本揭示的一些實施例之具有NSMD襯墊之半導體元件的俯視圖。
圖2A係根據本揭示的一些實施例之具有阻焊層限定(SMD)襯墊之半導體元件的示意圖。
圖2B係根據本揭示的一些實施例之具有SMD襯墊之半導體元件的俯視圖。
圖3A係根據本揭示的一些實施例之具有NSMD襯墊及SMD襯墊之半導體元件的示意圖。
圖3B係根據本揭示的一些實施例之具有NSMD襯墊及SMD襯墊 之半導體元件的俯視圖。
圖4A係根據本揭示的一些實施例之具有於角落的NSMD襯墊之半導體元件的示意圖。
圖4B係根據本揭示的一些實施例之具有鄰接角落的NSMD襯墊之半導體元件的示意圖。
圖4C係根據本揭示的一些實施例之具有鄰接空區域的NSMD襯墊之半導體元件的示意圖。
圖5係根據本揭示的一些實施例之製造半導體元件之方法的流程圖。
圖5A係根據本揭示的一些實施例之具有第一基板之半導體元件的示意圖。
圖5B係根據本揭示的一些實施例之具有數個襯墊之半導體元件的示意圖。
圖5C係根據本揭示的一些實施例之具有阻焊層之半導體元件的示意圖。
圖5D係根據本揭示的一些實施例之具有於角落的NSMD襯墊之半導體元件的俯視圖。
圖5E係根據本揭示的一些實施例之具有鄰接角落的NSMD襯墊之半導體元件的俯視圖。
圖5F係根據本揭示的一些實施例之具有鄰接角落的NSMD襯墊之半導體元件的俯視圖。
圖5G係根據本揭示的一些實施例之具有在一圓外的NSMD襯墊之半導體元件的俯視圖。
圖5H係根據本揭示的一些實施例之具有在一圓外的NSMD襯墊之半導體元件的俯視圖。
圖5I係根據本揭示的一些實施例之具有NSMD襯墊及SMD襯墊之 半導體元件的示意圖。
圖5J係根據本揭示的一些實施例之具有第二基板之半導體元件的示意圖。
圖5K係根據本揭示的一些實施例之具有第一基板及第二基板之半導體元件的示意圖。
在表面安裝技術(SMT)中，半導體元件包括至少二個基板。透過例如焊接點或焊接凸部的導電凸部，以藉由附接基板的襯墊至另一基板的襯墊的方式，而將一基板堆疊在另一基板上。藉由將導電材料濺射或電鍍至基板上來形成基板的襯墊，使得襯墊導通在基板的電路與在該基板外的另一基板之間的電力。隨後，焊接材料覆蓋基板的襯墊以選擇性地暴露襯墊的頂部表面。可藉由各種方法暴露襯墊，其定義為了容納凸部之襯墊之頂部表面的區域。隨後將襯墊的暴露表面與凸部附接。
然而，上述基板上的襯墊之組態有一些問題，例如襯墊與基板間的附著力減少、於機械測試(如板彎曲或掉落測試)之低可靠度、在襯墊周圍的應力集中、在板層級溫度循環之低可靠度等等。因為以不同方法形成及暴露襯墊具有不同的問題，最終基板整體可能會有低可靠度及低功能效能。
以下詳細探討本發明之實施例之製造與使用。然而，應當理解此些實施例提供很多可應用的進步性概念，其可在各種各樣的特定情境下體現。應當理解以下揭示提供很多不同實施例或實例以實現各種實施例的不同特徵。以下敘述部件及安置的特定實例以簡化本揭示。當然這些僅為實例並且不旨在於限制。
以下使用特定語言揭示在圖式中顯示的實施例或實例。然而應當理解這些實施例或實例並不旨在於限制。對所揭示實施例之任何改 變及修改以及本文所揭示任何進一步原理之應用可預期對本案所屬領域具有通常知識者可正常進行。
此外，應當理解元件的數個處理步驟及/或特徵僅會簡要說明。另外，可附加額外處理步驟及/或特徵，且在實作請求項時，可移除或更改以下特定的處理步驟及/或特徵。因此，應當理解以下敘述僅代表實例，而非旨於建議需要一或多個步驟或特徵。
除此之外，本揭示在各種例子會重複使用元件符號及/或字母。此種重複係為了簡要及清楚起見，而其本身並未決定所探討之各種實施例及/或組態間的關係。
在本揭示中，揭示一種具有經改良組態的半導體元件。該半導體元件包括一基板及數個在該基板上的襯墊，其係阻焊層限定(SMD)襯墊及非阻焊層限定(NSMD)襯墊之組合，以使得SMD襯墊與NSMD襯墊的缺點係可彌補的，因此作為一個整體的基板具備SMD襯墊與NSMD襯墊所貢獻的優點，例如對於板層級溫度循環的高可靠度、掉落測試的良好效能、應力集中點數目的減少等等。
圖1A為半導體元件100之實施例。半導體元件100包括基板101。在一些實施例中，基板101係包括矽基板之電路板，該矽基板用於承載該矽基板內的電路以及支撐連接至該電路的數個半導體部件。矽基板包括數個導電層及數個介電層。導電層包括一些用於在矽基板上電連接數個半導體部件的導電線。介電層係經組態以在導電線間絕緣。一些實施例中，電路板係包括一些積體電路(IC)的印刷電路板(PCB)以用於在其上之半導體部件之電連接。在一些實施例中，基板101係長條狀。
在一些實施例中，半導體元件100包括配置在基板101的表面101a之襯墊102。襯墊102以水平方向沿著表面101a延伸。在一些實施例中，襯墊102係下凸部冶金(UBM)襯墊，其用於接受包括銅、錫、鉛 等的導電凸部(conductive bump)。UBM襯墊係一種可焊表面，其經暴露以接收凸部且將襯墊102與基板101內的電路連接。襯墊102在例如回流之熱處理之後與凸部黏合。
在一些實施例中，藉由各種方法如電鍍、濺鍍等等，將襯墊102配置在表面101a上。在一些實施例中，襯墊102包括例如金、銀、銅、鎳，鎢，鋁及/或以上之合金的導電材料。
在一些實施例中，半導體元件100包括配置覆於基板101之表面101a上的阻焊層103。在一些實施例中，阻焊層103自襯墊102被分隔。阻焊層103圍繞襯墊102。在阻焊層103及襯墊102之間存在間隙104。阻焊層103並未與襯墊102接觸且並未被該襯墊覆蓋。在一些實施例中，阻焊層103之頂部表面103a係高於襯墊102之頂部表面102a的水平面處。
在一些實施例中，阻焊層103包括例如液體環氧樹脂或聚環氧化物等之聚合材料。在一些實施例中，藉由絲網印刷、噴塗等將阻焊層103配置在基板101之表面101a上。
在一些實施例中，阻焊層103包括第一凹陷部分103b。第一凹陷部分103b圍繞襯墊102，襯墊102被配置在阻焊層103之第一凹陷部分103b內。在一些實施例中，第一凹陷部分103b自阻焊層103之頂部表面103a延伸到基板101之頂部表面101a。
在一些實施例中，第一凹陷部分103b的側壁被配置遠離襯墊102。在一些實施例中，第一凹陷部分103b經組態以暴露襯墊102的頂部表面102a以及襯墊102的周圍部分102b，以接受凸部。
在一些實施例中，襯墊102係非阻焊層限定(NSMD)襯墊。NSMD襯墊102被配置在第一凹陷部分103b內且自阻焊層103分隔。NSMD襯墊102自阻焊層103隔離。阻焊層103不存在襯墊102之頂部表面102a及周圍部分102b。用於接受凸部的NSMD襯墊102之區域並非取決於第 一凹陷部分103b之尺寸。第一凹陷部分103b係大於NSMD襯墊102。
圖1B係圖1A的半導體元件100之實施例的俯視圖。半導體元件100包括基板101、襯墊102及阻焊層103。在一些實施例中，阻焊層103大體上覆蓋基板101之頂部表面101a。阻焊層103包括環繞襯墊102的第一凹陷部分103b，使得阻焊層103自襯墊102分隔。在一些實施例中，有環狀間隙104在襯墊102及阻焊層103之間。環狀間隙104圍繞襯墊102。
在一些實施例中，第一凹陷部分103b係圓形或橢圓形，且襯墊102亦係圓形或橢圓形。在一些實施例中，第一凹陷部分103b具有一寬度或直徑Dfirst recessed portion，且襯墊102具有一寬度或直徑Dpad。在一些實施例中，第一凹陷部分103b之直徑Dfirst recessed portion係大於襯墊102之直徑Dpad。在一些實施例中，第一凹陷部分103b之直徑Dfirst recessed portion係約300um至約350um。在一些實施例中，襯墊102之直徑Dpad係約200um至約300um。
圖2A係半導體元件100之實施例。半導體元件100包括基板101。在一些實施例中，基板101係包括積體電路(IC)的印刷電路板(PCB)以用於其上半導體部件之電連接。在一些實施例中，基板101係長條狀。在一些實施例中，半導體元件100包括配置在基板101的表面101a上的襯墊102。襯墊102以水平方向沿著表面101a延伸。在一些實施例中，襯墊102係一種用於接受導電凸部的UBM襯墊，該導電凸部包括銅、錫、鉛、焊錫等等。UBM襯墊經組態以用基板101內的電路以電連接襯墊102。在一些實施例中，襯墊102包括例如金、銀、銅、鎳，鎢，鋁及/或以上之合金的導電材料。
在一些實施例中，半導體元件100包括配置覆於基板101的表面101a上的阻焊層103。在一些實施例中，阻焊層103包括例如液體環氧樹脂或聚環氧化物等之聚合材料。在一些實施例中，阻焊層103圍繞 襯墊102。在一些實施例中，阻焊層103部分地覆蓋襯墊102。襯墊102的頂部表面102a的末端部分及襯墊102的周圍部分102b被阻焊層103覆蓋。阻焊層103與襯墊102接觸。
在一些實施例中，頂部表面102a的中央部分被暴露以接受凸部。在一些實施例中，阻焊層103的頂部表面103a係高於襯墊102的頂部表面102a的水平面處且覆於襯墊102上。
在一些實施例中，阻焊層103包括第二凹陷部分103c。在一些實施例中，第二凹陷部分103c在襯墊102之上。襯墊102被配置在第二凹陷部分103c下方。在一些實施例中，第二凹陷部分103c自阻焊層103的頂部表面103a延伸至襯墊102的頂部表面102a。第二凹陷部分103c之底部介接頂部表面102a。
在一些實施例中，第二凹陷部分103c之側壁103e被配置在襯墊102的頂部表面102a。在一些實施例中，第二凹陷部分103c經組態以用於暴露襯墊102之頂部表面102a的中央部分，以接受凸部。
在一些實施例中，襯墊102係一種阻焊層限定(SMD)襯墊。SMD襯墊102係部分地被阻焊層103覆蓋。SMD襯墊102之周圍被阻焊層103圍繞，從而用於接受凸部的SMD襯墊102之頂部表面102a的中央部分由阻焊層103定義，暴露用於接受凸部的SMD襯墊102之頂部表面102a的中央部分以取決第二凹陷部分103c的尺寸。在一些實施例中，第二凹陷部分103c係小於SMD襯墊102。
圖2B係圖2A的半導體元件100之實施例的俯視圖。半導體元件100包括基板101、襯墊102及阻焊層103。在一些實施例中，阻焊層103覆蓋基板101之頂部表面101a及襯墊102之周圍部分102b。阻焊層103包括配置在襯墊102上的第二凹陷部分103c。在一些實施例中，襯墊102之周圍部分102b被阻焊層103沿圓周方向圍繞。
在一些實施例中，第二凹陷部分103c係圓形或橢圓形，且襯墊 102亦係圓形或橢圓形。在一些實施例中，第二凹陷部分103c具有一寬度或直徑Dsecond recessed portion，且襯墊102具有一寬度或直徑Dpad。在一些實施例中，第二凹陷部分103c之直徑Dsecond recessed portion係小於襯墊102之直徑Dpad。在一些實施例中，第二凹陷部分103c之直徑Dsecond recessed portion係約175um至約250um。在一些實施例中，襯墊102之直徑Dpad係約250um至約350um。
圖3A為半導體元件200之實施例。半導體元件200包括基板101、阻焊層103以及配置在基板101的頂部表面101a的數個襯墊102。在一些實施例中，襯墊102包括數個NSMD襯墊102-1及數個SMD襯墊102-2。NSMD襯墊102-1具有與圖1A及1B相似的組態。SMD襯墊102-2具有與圖2A及2B相似的組態。在一些實施例中，阻焊層103覆蓋SMD襯墊102-2之周圍部分102b，且阻焊層103與NSMD襯墊102-1遠離地分隔。
在一些實施例中，阻焊層103包括數個第一凹陷部分103b及數個第二凹陷部分103c。NSMD襯墊102-1在第一凹陷部分103b內，且SMD襯墊102-2被配置在第二凹陷部分103c下方。
圖3B係圖3A的半導體元件200之實施例的俯視圖。半導體元件200包括基板101、數個NSMD襯墊102-1、數個SMD襯墊102-2及被配置覆於頂部表面101a上的阻焊層103。在一些實施例中，阻焊層103包括數個第一凹陷部分103b及數個第二凹陷部分103c，使得NSMD襯墊102-1在環狀間隙104中自阻焊層103分隔，且SMD襯墊102-2之周圍部分102b被阻焊層103沿圓周方向覆蓋。
圖4A為半導體元件200之實施例。半導體元件200包括基板101、在基板上之阻焊層103、配置在基板101上的數個NSMD襯墊102-1及數個SMD襯墊102-2。在一些實施例中，SMD襯墊102-2被配置遠離基板101之角落101b。在一些實施例中，SMD襯墊102-2被配置在基板 101的中央部分。
在一些實施例中，NSMD襯墊102-1及SMD襯墊102-2被排列成規則陣列。NSMD襯墊102-1及SMD襯墊102-2在基板101排列成數個水平行中及數個垂直列。
在一些實施例中，NSMD襯墊102-1被安置在預定位置。在一些實施例中，預定位置係在基板101的角落101b處。NSMD襯墊102-1經組態以用於可與另一基板上襯墊電連接之凸部。
在一些實施例中，因為NSMD襯墊102-1允許凸部配置在NSMD襯墊102-1的頂部表面102a上以及NSMD襯墊102-1的周圍部分102b，所以NSMD襯墊102-1被安置在角落101b，以最小化甚至避免阻焊層103周圍的應力集中點的產生。如此，基板101的角落101b處NSMD襯墊102-1的配置提供相對於掉落測試、板層級溫度循環、板彎曲等之基板的改良之可靠度，以及最小化部件之裂縫與剝離的產生。
在一些實施例中，阻焊層103包括數個第一凹陷部分103b及數個第二凹陷部分103c。在一些實施例中，第一凹陷部分103b圍繞NSMD襯墊102-1，且SMD襯墊102-2被配置在第二凹陷部分103c上方。
在一些實施例中，根據對應的NSMD襯墊102-1之位置將第一凹陷部分103b配置在預定位置。在一些實施例中，因為NSMD襯墊102-1被配置在角落101b處，所以第一凹陷部分103b被配置在基板101的角落101b處。第一凹陷部分103b的位置對應於對應的NSMD襯墊102-1之位置。
在一些實施例中，第二凹陷部分103c被配置在對應於SMD襯墊102-2之位置的位置。在一些實施例中，因為對應的SMD襯墊102-2被配置在中央部分，所以第二凹陷部分103c被配置在基板101的中央部分處。第二凹陷部分103c的位置對應於對應的SMD襯墊102-2之位置。
圖4B係半導體元件200之實施例。半導體元件200包括基板101、在基板上的阻焊層103、配置在基板101上的數個NSMD襯墊102-1及數個SMD襯墊102-2。在一些實施例中，SMD襯墊102-2被配置在基板101的中央部分。
在一些實施例中，NSMD襯墊102-1被安置在預定位置。在一些實施例中，預定位置係在基板101的角落101b處以及在鄰接角落101b的角落區域。在一些實施例中，NSMD襯墊102-1在角落101b處與NSMD襯墊102-1鄰接。在一些實施例中，有三個NSMD襯墊102-1被配置在角落101b處以及角落區域。
在一些實施例中，阻焊層103包括數個第一凹陷部分103b及數個第二凹陷部分103c。在一些實施例中，根據對應的NSMD襯墊102-1之位置，第一凹陷部分103b被配置在預定位置。在一些實施例中，第一凹陷部分103b被配置在角落101b以及角落區域。在一些實施例中，有三個第一凹陷部分103b被配置在角落101b處以及角落區域，對應於對應的NSMD襯墊102-1的位置。
圖4C係半導體元件200之實施例。半導體元件200包括基板101、在基板上的阻焊層103、配置在基板101上的數個NSMD襯墊102-1及數個SMD襯墊102-2。在一些實施例中，NSMD襯墊102-1及SMD襯墊102-2被排列成包括空區域101c的不規則陣列，空區域101c不存在NSMD襯墊及SMD襯墊。
在一些實施例中，NSMD襯墊102-1被安置在預定位置。在一些實施例中，預定位置係在鄰接基板101的空區域101c處。鄰接空區域101c的襯墊102被定義為孤立襯墊(isolated pad)且以NSMD襯墊102-1配置。孤立襯墊鄰近少於四個襯墊102。在一些實施例中，有二個孤立襯墊鄰接空區域101c且以NSMD襯墊102-1配置。
在一些實施例中，阻焊層103包括數個第一凹陷部分103b及數個 第二凹陷部分103c。在一些實施例中，根據對應的NSMD襯墊102-1的位置，第一凹陷部分103b被配置在預定位置。在一些實施例中，第一凹陷部分103b被配置以鄰接空區域101c。第一凹陷部分103b圍繞鄰接空區域101c的孤立襯墊。在一些實施例中，有二個第一凹陷部分103b被配置鄰接空區域101c，對應於定義為孤立襯墊的對應NSMD襯墊102-1的位置。
在本揭示中，亦揭示製造半導體元件之方法。在一些實施例中，半導體元件係藉由方法300來形成。方法300包括數個操作，且說明和圖示不應視為操作順序之限制。
圖5係製造半導體元件之方法300的實施例。方法300包括數個操作(301、302、303、304、305、306、307、308、309)。
於操作301，如圖5A，提供第一基板101。在一些實施例中，第一基板101係用於支撐數個半導體部件及承載基板內的電路之矽基板。在一些實施例中，第一基板101係印刷電路板(PCB)。
於操作302，如圖5B，數個襯墊102被配置在基板101之表面101a上。在一些實施例中，襯墊102沿著表面101a而水平地配置。在一些實施例中，襯墊102係一種用於接受凸部的下凸部冶金(UBM)襯墊。在一些實施例中，藉由電鍍而將襯墊102配置在表面101a上。在一些實施例中，襯墊102包括例如金、銀、銅、鎳，鎢，鋁及/或以上之合金的導電材料。
於操作303，如圖5C，阻焊層103被配置覆於基板101的表面101a上。阻焊層103覆蓋襯墊102及表面101a。在一些實施例中，阻焊層103包括例如液體環氧樹脂或聚環氧化物等之聚合材料。在一些實施例中，藉由絲網印刷、噴塗等將阻焊層103配置在基板101之表面101a上。
於操作304，藉由各種方法以判定在阻焊層上第一凹陷的位置及 第二凹陷的位置。在一些實施例中，第一凹陷的位置及第二凹陷的位置係於預定位置處。
在一些實施例中，位置係由圖5D之方法來判定。圖5D係圖5A、5B及5C的半導體元件200的俯視圖。在一些實施例中，第一凹陷103b的位置及第二凹陷103c的位置係藉由定義具有預定的中點NP及預定的直徑DNP之圓105來判定。在一些實施例中，圓105以中點NP為中心且具有直徑DNP。中點NP係圓105之中心。
在一些實施例中，第一凹陷103b的位置被判定在圓105外的襯墊102上之位置。在一些實施例中，襯墊102被配置在大於在圓105的中點NP與圓周之間的距離DNP處。在一些實施例中，在圓105外襯墊102之上方的位置係基板101之角落101b。如此，第一凹陷103b被判定在角落101b處且覆於襯墊102上。在一些實施例中，有四個第一凹陷103b被配置在阻焊層103上且在角落101b處。
在一些實施例中，第二凹陷103c的位置被判定在圓105內的襯墊上方的位置。在一些實施例中，襯墊102被配置在小於在圓105的中點NP與圓周之間的距離DNP處。在一些實施例中，在襯墊102上方的位置係基板101的中央位置，且因此第二凹陷103b被判定在中央部分處。在一些實施例中，有三十二個第二凹陷103c被配置在阻焊層103上且在基板101的中央部分處。
在一些實施例中，第一凹陷的位置及第二凹陷的位置係由圖5E之方法來判定。圖5E係圖5A、5B及5C的半導體元件200的俯視圖。在一些實施例中，第一凹陷103b的位置及第二凹陷103c的位置係藉由定義具有預定的中點NP及預定的直徑DNP之圓105來判定。在一些實施例中，中點NP係圓105的中心。
在一些實施例中，第一凹陷103b被判定在圓105外之襯墊102之上的位置處。在一些實施例中，襯墊102被配置在大於在圓105的中點 NP與圓周之間的距離DNP處。在一些實施例中，在圓105外襯墊102之上方的位置鄰接基板101的角落101b，且因此第一凹陷103b被判定在鄰接角落102b且覆於襯墊102上之位置處。在一些實施例中，有十二個第一凹陷103b被配置覆於阻焊層103上且在鄰接角落101b之位置處。
在一些實施例中，第二凹陷103c的位置被判定在圓105內的襯墊上方的位置。在一些實施例中，襯墊102被配置在小於在圓105的中點NP與圓周之間的距離DNP處。在一些實施例中，在襯墊102上方的位置係基板101的中央位置，且因此第二凹陷103c被判定在中央部分處。在一些實施例中，有二十四個第二凹陷103c被配置在阻焊層103上方且在基板101的中央部分處。
在一些實施例中，第一凹陷的位置及第二凹陷的位置係由圖5F之方法來判定。圖5F係圖5A、5B及5C的半導體元件200的俯視圖。在一些實施例中，根據定義襯墊102為孤立襯墊以判定第一凹陷103b的位置及第二凹陷103c的位置。
在一些實施例中，若襯墊102鄰接基板101的空區域101c，則襯墊102被定義為孤立襯墊。在一些實施例中，若襯墊102相鄰少於四個襯墊102，則襯墊102被定義為孤立襯墊。在一些實施例中，有二個孤立襯墊鄰接空區域101c，且因此第一凹陷103b被配置在孤立襯墊的上方。在一些實施例中，第二凹陷103c被配置在被定義為非孤立襯墊之襯墊102的上方。非孤立襯墊係相鄰多於四個襯墊102的襯墊102。
在一些實施例中，第一凹陷的位置及第二凹陷的位置由圖5D及5F之方法即圖5G之方法來判定。圖5G係圖5A、5B及5C的半導體元件200的俯視圖。在一些實施例中，藉由定義襯墊102為孤立襯墊以及定義具有預定的中點NP及預定的直徑DNP之圓105來判定第一凹陷103b。第一凹陷103b係配置覆於鄰接空區域101c或在圓105外作為孤 立襯墊的襯墊102上，而第二凹陷103c係配置覆於襯墊102上作為遠離空區域101c或在圓105內的非孤立襯墊。
在一些實施例中，第一凹陷的位置及第二凹陷的位置由圖5E及5F之方法即圖5H之方法來判定。圖5H係圖5A、5B及5C的半導體元件200的俯視圖。在一些實施例中，藉由定義襯墊102為孤立襯墊以及定義具有預定的中點NP及預定的直徑DNP之圓105來判定第一凹陷103b。第一凹陷103b係配置覆於襯墊102上作為鄰接空區域101c或在圓105外的孤立襯墊，而第二凹陷103c係配置覆於襯墊102上作為遠離空區域101c或在圓105內的非孤立襯墊。
於操作305，如圖5I，阻焊層103的一部分被移除。在一些實施例中，根據判定覆於襯墊102上第一凹陷103b及第二凹陷103c的位置來移除阻焊層103的一部分，參考如上所載操作304以及圖5D-5H。
於操作306，如圖5I，形成阻焊層103的第一凹陷103b。在一些實施例中，第一凹陷103b係形成覆於襯墊102上，使得襯墊102成為非阻焊層限定(NSMD)襯墊102-1。NSMD襯墊102-1係類似圖1A及1B的組態。NSMD襯墊102-1對應地在第一凹陷103b內且在間隙104中自第一凹陷103b分隔。
於操作307，如圖5I，形成阻焊層103的第二凹陷103c。在一些實施例中，於襯墊102上形成第二凹陷103c，使得襯墊102成為阻焊層限定(SMD)襯墊102-2。SMD襯墊102-2係類似圖1C及1D的組態。SMD襯墊102-2對應地在第二凹陷103b上且部分地被阻焊層103覆蓋。
於操作308，如圖5J，提供第二基板401。在一些實施例中，第二基板401係包括晶圓基板內的晶粒及電路的晶圓基板。在一些實施例中，數個晶粒襯墊402被配置在第二基板401之表面404上。晶粒襯墊402經組態以接受凸點。
於操作309，第一基板101與第二基板401黏合。在一些實施例 中，藉由用數個凸部將第一基板102之襯墊對應地連接第二基板401的晶粒襯墊402以將第一基板101與第二基板401黏合。對應地將凸部403與晶粒襯墊402附接，使得第一基板內的電路透過襯墊102、晶粒襯墊402及凸點403電連接至第二基板401內的電路。
在一些實施例中，半導體元件包括基板，該基板包括表面、配置在基板之表面上的數個襯墊，襯墊包括非阻焊層限定(NSMD)襯墊及阻焊層限定(SMD)襯墊102-2，且NSMD襯墊被安置在預定位置處。
在一些實施例中，預定位置係在基板之角落處。在一些實施例中，SMD襯墊被配置遠離基板之角落在一些實施例中，NSMD襯墊及SMD襯墊被配置在包括空區域之不規則陣列中，空區域不存在NSMD襯墊及SMD襯墊，且NSMD襯墊被安置以鄰接空區域。在一些實施例中，SMD襯墊部分地被阻焊層覆蓋。在一些實施例中，NSMD襯墊自阻焊層分隔。
在一些實施例中，半導體元件包括基板，該基板包括表面、配置在基板之表面上的數個襯墊、配置在基板之表面的阻焊層，阻焊層包括第一凹陷部分及第二凹陷部分。襯墊之至少一者對應地在第一凹陷部分內，且襯墊之至少一者對應地配置在第二凹陷部分下方。
在一些實施例中，第一凹陷部分之每一者係大於一對應之襯墊。在一些實施例中，第二凹陷部分之每一者係大於一對應之襯墊。在一些實施例中，第一凹陷部分被配置在基板之角落。在一些實施例中，第二凹陷部分被配置在基板之中央部分。
在一些實施例中，一種製造半導體元件的方法，其包括提供基板、配置數個襯墊在基板之表面上、配置阻焊層覆於基板之表面及襯墊上、在阻焊層中形成第一凹陷以圍繞襯墊之一者、及在阻焊層中且在襯墊之一者上形成第二凹陷。
在一些實施例中，對應於第一凹陷的襯墊之一者被配置在基板 之角落時，則形成第一凹陷。在一些實施例中，該方法進一步包括判定形成在阻焊層上第一凹陷之位置以及第二凹陷之位置。在一些實施例中，該方法進一步包括定義具有預定中點及預定直徑的圓以在阻焊層上判定第一凹陷之位置以及第二凹陷之位置。
在一些實施例中，定位第一凹陷以圍繞被配置在圓外的襯墊之一者，該圓具有預定中點及預定直徑。在一些實施例中，定位第二凹陷在被配置在圓內的襯墊之一者上，該圓具有預定中點及預定直徑。在一些實施例中，該方法進一步包括定義鄰接基板之空區域之襯墊之至少一者以作為孤立襯墊。在一些實施例中，形成第一凹陷以圍繞被定義為孤立襯墊之襯墊。在一些實施例中，被定義為孤立襯墊之襯墊係與少於四個襯墊相鄰。
本發明之方法與特徵已於上述實例及敘述充分描述。應當理解不偏離本發明的精神之任何改變及修改將意圖涵蓋在本發明的保護範圍。
除此之外，在本申請的範圍並不旨在限於本說明書所描述之程序、機器、製程以及物質組成、手段、方法及步驟之特定實施例。本領域技術人員將容易從本揭示、程序、機器、製程、物質組成、手段、方法或步驟，當前存在或以後開發的揭示而體會，可利用根據本揭示之所描述的對應實施例，執行實質上相同的功能或達成實質上相同的結果。
因此，所附申請專利範圍旨在在其範圍內包括如此的程序、機器、製程、物質組成、手段、方法或步驟。此外，每一請求項構成了一個單獨的實施方案，且各請求項和實施例的組合都在本發明的範圍之內。
100‧‧‧半導體元件
101‧‧‧基板
101a‧‧‧表面
102‧‧‧襯墊
102a‧‧‧頂部表面
102b‧‧‧周圍部分
103‧‧‧阻焊層
103a‧‧‧頂部表面
103b‧‧‧第一凹陷部分
104‧‧‧間隙

Claims (10)

  1. 一種半導體元件，其包含：一基板，其包括一表面；複數個襯墊，其配置在該基板之該表面上；其中該複數個襯墊包括一非阻焊層限定(NSMD)襯墊及一阻焊層限定(SMD)襯墊，且該NSMD襯墊被安置於一預定位置處。
  2. 如請求項1之半導體元件，其中該預定位置係於該基板之一角落處，或其中該SMD襯墊被配置而遠離該基板之一角落。
  3. 如請求項1之半導體元件，其中該NSMD襯墊及該SMD襯墊被排列成一不規則陣列，該不規則陣列包括一空區域，該空區域不存在該NSMD襯墊及該SMD襯墊，且該NSMD襯墊被安置以鄰接該空區域。
  4. 一種半導體元件，其包含：一基板，其包括一表面；複數個襯墊，其配置在該基板之該表面上；一阻焊層，其配置覆於該基板之該表面上；其中該阻焊層包括複數個第一凹陷部分及複數個第二凹陷部分，該複數個襯墊之至少一者係對應地在該複數個第一凹陷部分內，且該複數個襯墊之至少一者係對應地被配置在該複數個第二凹陷部分下方。
  5. 如請求項4之半導體元件，其中該複數個第一凹陷部分之每一者係大於複數個襯墊之一對應者，或其中該複數個第二凹陷部分之每一者係小於複數個襯墊之一對應者。
  6. 如請求項4之半導體元件，其中該複數個第一凹陷部分被配置於該基板之一角落處，或其中該複數個第二凹陷部分被配置於該 基板之中央部分。
  7. 一種製造一半導體元件之方法，其包含：提供一基板；配置複數個襯墊在該基板之一表面上；配置一阻焊層覆於該基板之該表面及該複數個襯墊上；在該阻焊層中形成一第一凹陷以圍繞該複數個襯墊之一者；及在該阻焊層中且在該複數個襯墊之一者上形成一第二凹陷。
  8. 如請求項7之方法，其中在對應於該第一凹陷之該複數個襯墊之一者被配置於該基板之一角落處時，形成該複數個第一凹陷部分，或其中形成該第一凹陷以圍繞被定義作為一孤立襯墊之該複數個襯墊之一者。
  9. 如請求項7之方法，其進一步包含判定形成在該阻焊層上該第一凹陷之一位置以及該第二凹陷之一位置，或其進一步包含定義具有一預定中點及一預定直徑的一圓以在該阻焊層上判定該第一凹陷之一位置以及該第二凹陷之一位置，或其進一步包含定義鄰接該基板之一空區域之該複數個襯墊之至少一者作為一孤立襯墊。
  10. 如請求項7之方法，其中定位該第一凹陷以圍繞被配置在一圓外的該複數個襯墊之一者，該圓具有一預定中點及一預定直徑，或其中定位該第二凹陷在被配置在一圓內的該複數個襯墊之一者上，該圓具有一預定中點及一預定直徑。
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