TW200531186A - Chip package and process thereof - Google Patents

Abstract

A chip package and a process thereof are provided. The chip package comprises a chip and a rigid cover, wherein the chip has an active surface and a plurality of bond pads those are disposed on the former. The rigid cover is disposed on the active surface and the bond pads are exposed above the active surface by the rigid cover. The rigid cover can protect the active surface of the chip and improve the structural strength of the chip package. In addition, when the material of the rigid cover is a thermal conductive material such as copper or aluminum alloy, the thermal conductive efficiency of the chip package can be improved. Besides, when the rigid cover is made of a electrical conductive material and is electrically connected to the ground of the chip, the external electromagnetic interference (EMI) to the chip can be reduced.

Description

200531186 V. Description of the invention (υ [Technical field to which the invention belongs] The present invention relates to a chip package and its manufacturing process, and in particular to a chip package with a hard cover on the active surface of the chip and its [Previous technology] In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages: the design of integrated circuits, the production of integrated circuits, and the packaging of integrated circuits (Package), etc. Among them, bare wafers are completed through wafer (Wafer) fabrication, circuit design, mask fabrication, and wafer dicing, and each bare wafer formed by wafer dicing is soldered on the bare wafer. After the Bond Pad is electrically connected to the external signal, the bare chip is covered with a sealing material. The purpose of the package is to prevent the bare chip from being affected by moisture, heat and noise, and to provide the bare chip with external Circuits, such as printed circuit boards (PCBs) or other packaging media used for electrical connection between substrates, thus completing the integration In today's highly informative society, in order to meet the requirements of high-speed processing, multifunctionalization, accumulation, and miniaturization of electronic devices, the packaging technology of integrated circuits has also continued to move toward micro The development of high-density and high-density. Among the many types of chip packaging, "Chip Scale Package (CSP)" refers generally to the side length of a package body which is approximately 1 · 2 times or less the side length of the contained chip, or ( (Chip area / package area) is greater than 80%, and the package pitch of the package is limited to less than 1 mm. According to the structure and materials used, chip size packages can be roughly divided into hard

12013twf.ptd Page 9 200531186 V. Description of the Invention (2) Rigid Interposer Type, Flex Interposer Type, Custom Lead Frame Type and Wafer Level (Wafer Level Type) and other types. Different from the traditional packaging technology that uses a single die as the processing target, wafer-level packaging (wafer 1 eve 1 package) uses wafer as the object of package processing, and its main purpose is to simplify the wafer. Packaging process to save time and cost. After the fabrication of the integrated circuit on the wafer is completed, the entire wafer can be directly packaged, and then the wafer cutting (W af r S a w) operation can be performed to form a plurality of wafer packages respectively. [Summary of the Invention] Therefore, an object of the present invention is to provide a chip package which has better structural strength, and optionally has higher heat dissipation efficiency and anti-electromagnetic interference ability. Another object of the present invention is to provide a chip packaging process, which is suitable for manufacturing a chip packaging structure using wafer-level packaging technology, which has better structural strength, and can optionally have higher heat dissipation efficiency and anti-electromagnetic Interference ability. Based on the above object of the present invention, the present invention provides a chip package, which includes a wafer and a hard cover, wherein the wafer has an active surface and a plurality of solder pads, and the solder pads are disposed on the active surface. The hard cover is also disposed on the active surface of the chip, and these pads are exposed above the active surface.

12013twf.ptd Page 10 200531186 V. Description of the invention (3) According to the chip package according to the preferred embodiment of the present invention, the above chip may further have a heavy wiring layer, which is arranged on the active surface and forms the above. These pads. According to the chip package according to the preferred embodiment of the present invention, the above-mentioned hard cover system is arranged on the active surface of the chip in an adhesive manner. Among them, the hard cover can be adhered to the active part of the chip through the periphery of the hard cover. surface. In addition, the material of the hard cover may include a conductive material, an insulating material, or a transparent material. According to the chip package according to the preferred embodiment of the present invention, the above chip package may further include a plurality of conductive contacts, which are respectively arranged on the above-mentioned solder pads, and the height of these conductive contacts relative to the active surface is It is greater than the height of the hard cover relative to the active surface. According to the chip package according to the preferred embodiment of the present invention, the above-mentioned bonding pads can have a variety of different arrangements. For example, these pads can be arranged on the active surface of the wafer in an array manner, and the hard cover body has multiple openings, which respectively expose the corresponding pads. In addition, the above-mentioned pads can also be disposed on the periphery of the active surface. When the outline of the active surface is rectangular, the pads are disposed on at least one side of the periphery of the active surface. At this time, the chip may have a back surface opposite to the active surface and a plurality of connection lines, and one end of the connection lines is respectively connected to the pads, and the connection lines extend to the chip through the side edge surfaces of the chip And a bonding pad is formed on the back surface of the wafer respectively. It is worth noting that the above-mentioned bonding pads can be arranged on the periphery of the back surface of the wafer, or can be arranged on the back surface of the wafer in a surface array manner. In addition, on

12013twf.ptd Page 11 200531186 V. The chip package described in (4) of the invention further includes a plurality of conductive contacts, which are respectively arranged on the bonding pads. Based on the above object of the present invention, the present invention further proposes a wafer packaging process. First, a wafer is provided, wherein the wafer has an active surface and a corresponding back surface, and the wafer has a first wafer area and an adjacent area. One of the second wafer regions. In addition, the wafer further has a plurality of first pads and a plurality of second pads, which are respectively disposed on the active surface of the first wafer region and the active surface of the second wafer region. Then, a plurality of through-holes are formed on the wafer, and these through-holes penetrate the wafer, connect the active surface and the back surface, and are sequentially arranged at the junction of the first region and the second region. Then, a plurality of first connection lines and a plurality of second connection lines are formed on the wafer, and one end of the first connection lines respectively passes through the aforementioned through hole, and is electrically connected to the aforementioned first pads, respectively. Moreover, the other ends of the first connection lines further extend to the back surface of the first chip region, and a first bonding pad is formed on the back surface of the first chip region, respectively. In addition, one end of the aforementioned second connection lines also passes through the through holes, respectively, and is electrically connected to the aforementioned second pads, and the other ends of the second connection lines further extend to the back of the second chip region. A second bonding pad is formed on the back of the second wafer region. In addition, the first connection line partially located in the through holes may be further connected to the second connection line partially located in the through holes. Then, a first hard cover and a second hard cover are respectively disposed on the active surface of the first wafer region and the active surface of the second wafer region. Then, along the junction of the first wafer region and the second wafer region of the wafer

12013twf.ptd Page 12 200531186 V. Description of the invention (5) Cut the wafer, and at the same time cut the first connection line partially inside the above-mentioned through hole and the second connection line partially connected inside the above-mentioned through hole. Finally, the first wafer region and the second wafer region of the wafer are individually separated from the other parts of the wafer in a slicing manner, so that the "chip brother" wafer region and the first hard cover body become a first chip package. And make the second chip region and the second hard cover of the wafer a second chip package. According to the wafer packaging process according to the preferred embodiment of the present invention, before the first wafer region and the second wafer region of the wafer are separated from the other parts of the wafer by cutting, respectively, a plurality of conductive layers can be formed. The contacts are at the first joint 塾 and the second joint 上述 described above. In addition, the above-mentioned first hard cover system is arranged on the active surface of the first chip region in an adhesive manner, and moreover, it can be adhered to the active surface of the first chip region through the periphery of the first hard cover body. In addition, the material of the first hard cover may include a conductive material, an insulating material, and a transparent material. According to the chip packaging process according to the preferred embodiment of the present invention, the first bonding pads described above may be disposed on the periphery of the back surface of the first wafer region, or may be disposed on the back surface of the first wafer region in a surface array manner. In addition, a method of forming the partial first connection lines in the above-mentioned through holes includes plating. In addition, when the first hard cover and the second hard cover are configured, the first hard cover and the second hard cover can be structurally connected to each other, and when the wafer is cut, the first hard cover and the second hard cover are further cut. The connecting portion of the second hard cover is used to separate the first hard cover and the second hard cover. Based on the above, the chip package of the present invention and its manufacturing process are configured with a hard cover on the active surface of the chip to protect the active watch of the chip.

12013twf.ptd Page 13 200531186 V. Description of the invention (6) and increase the structural strength of the chip package. In addition, when the material of the hard cover is a thermally conductive material such as copper or aluminum alloy, the hard cover can improve the heat dissipation performance of the chip package. In addition, when the material of the hard cover is a conductive material, the hard cover electrically connected to the ground end of the chip can further reduce electromagnetic interference from the outside to the chip. It is worth noting that the wafer packaging process of the present invention can further form a plurality of bonding pads on the back surface of the wafer, so that the chip package can be bonded to a circuit board (PCB) or substrate through the bonding pads on the back surface of the wafer. (Substrate) multiple contacts. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows. [Embodiment] [First embodiment] Please refer to FIGS. 1A and 1B, where FIG. 1A illustrates a top view of a first chip package according to a first embodiment of the present invention, and FIG. 1B illustrates a first Section A of I-I / line. The chip package 100 includes a chip 110, a hard cover 120, and an adhesive layer 130. The chip 110 is a plurality of uncut wafers formed by a wafer (not shown). One of the wafers, and the shape of the wafer 1 10 is, for example, a rectangle and has an active surface 1 12 and a plurality of pads 1 1 4. The pads 1 1 4 are arranged on the periphery of the active surface 1 12. In addition, the hard cover 120 is adhered to the active surface 1 1 2 of the wafer 1 10 through an adhesive layer 130, and the pads 1 4 are surrounded by the periphery of the hard cover 120. Please also refer to Figures IA, 1B and 1C, where Figure 1C shows Figure 1A

12013twf.ptd Page 14 200531186 V. Description of Invention (7) The first type of chip package, which is assembled to a cross-sectional view of a printed circuit board. A conductive contact 1 1 6, such as a conductive bump, may be provided on each of the solder pads 1 1 4. The height of the conductive contacts 116 relative to the active surface 112 is greater than the rigid cover 120. The height relative to the active surface 1 12 so that the chip package 100 can be assembled on a printed circuit board 1 40 through conductive contacts 1 16, where the printed circuit board 1 40 can have multiple Each of the bonding pads 1 4 2 is electrically connected to the bonding pads 14 2 of the printed circuit board 1 40 through the conductive contacts 1 1 4 of the chip package 100. In addition, by controlling the height of the conductive contact 1 16 or the hard cover 120 with respect to the wafer 110, the hard cover 120 can be selectively brought into contact with or not in contact with the printed circuit board 140. Under certain thermal or electrical considerations, the rigid cover 120 can be structurally or electrically connected to the printed circuit board 140. In addition, in FIGS. 1A to 1C, the pads 1 1 4 of the wafer 1 10 are not limited to being disposed around the active surface 112 of the wafer 110, and may be disposed on the active surface 1 1 of the wafer 110. The early side or two sides of 2 (such as adjacent sides or opposite sides). Please refer to FIGS. 2A and 2B, where FIG. 2A shows a top view of a second chip package according to the first embodiment of the present invention. Fig. 2B shows a cross-sectional view taken along line Π- Π / of Fig. 2A. Compared with the first type of chip package described above, the chip 210 of the second type of chip package 200 has a plurality of bonding pads 2 1 4 which are arranged on the active surface 2 1 of the chip 2 1 in a surface array manner. 2. The active surface 212 of the chip 210 may have a re-distribution layer (RDL) (not shown). This re-wiring layer may allow the pads 2 1 4 originally located around the active surface 2 1 2 Rearranged on the active surface 2 1 2 in an area array manner. In addition, the hard cover 2 2 0 is borrowed

12013twf.ptd Page 15 200531186 V. Description of the invention (8) The active surface 212 of the chip 210 is adhered by the adhesive layer 230, and the hard cover 2 2 0 has a plurality of openings 2 2 2 which correspond to these solders, respectively. The pads 2 1 4 also expose these pads 214. Please refer to FIG. 2C, which illustrates a cross-sectional view of the second chip package of FIG. 2A assembled to a printed circuit board. A conductive contact 2 1 6 is formed on each of the pads 2 1 4 arranged in a surface array manner on the wafer 2 10, and the height of the 0 conductive contacts 2 1 6 relative to the active surface 2 1 2 is greater than the rigidity. The height of the cover body 2 2 0 relative to the active surface 2 1 2 enables the chip package 2 0 0 to be assembled on a printed circuit board 2 4 0 through these conductive contacts 2 1 6, wherein the printed circuit board 2 The 240 may have a plurality of bonding pads 242, and the bonding pads 214 of the chip package 200 are electrically connected to the bonding pads 242 of the printed circuit board 240 through the conductive contacts 216. In the two chip packages of the first embodiment, the hard cover system is completely covered on the wafer, and a conductive contact (such as a conductive bump) is respectively arranged on these pads, and then the wafer is cut into Multiple independent chip packages. It is worth noting that, in addition to forming conductive pads on the wafer before the dicing of the wafer, for the chip package to be assembled to a printed circuit board or other carrier board, you can also choose to form the conductive contacts first. On the bonding pads of the printed circuit board, the chip package is assembled to the printed circuit board through these conductive contacts. [Second Embodiment] In addition to the above-mentioned first embodiment, in which a plurality of conductive contacts are arranged on a plurality of bonding pads on the active surface of a wafer, a second embodiment of the present invention is to use a plurality of connection lines to separately separate the wafers. Of the active surface of these pads,

12013twf.ptd Page 16 200531186 V. Description of the invention (9) The side of the wafer extends to the back of the wafer, and a plurality of bonding pads are formed on the back of the wafer, and a plurality of conductive contacts are respectively arranged on the back of the wafer. Bonding pads *. The chip package and its manufacturing process according to the second embodiment of the present invention will be described in detail below. t Please refer to FIGS. 3A to 3F and FIGS. 4A to 4F, where FIGS. 3A to 3F show a top view of a chip packaging process according to the second embodiment of the present invention, and θ FIGS. 4A to 4F show 3A ~ 3F picture! Π — melon, line cross-section. First, as shown in FIGS. 3A and 4A, a wafer 302 is provided, and the wafer 302 has an active surface 3 1 2 and a corresponding back surface 3 1 6. In addition, the wafer 300 has a first wafer region 310a and an adjacent second wafer region 31b. The active surface 312 of the first wafer region 310a is provided with a plurality of first zinc alloys 314a, and On the active surface 312 of the second wafer region 31b, a plurality of second fresh wafers 314b are disposed. Next, as shown in FIGS. 3B and 4B, at the boundary between the first wafer region 31a and the second wafer region 3 1 Ob, for example, laser drilling or mechanical drilling is used to increase the ratio> A plurality of through holes 3 1 8 are formed on the wafer 300. The through holes 3 1 8 penetrate the wafer 302 ′ and connect the active surface 312 and the back surface 316 of the wafer 300 and are sequentially arranged on the first wafer. The boundary between the region 3 10a and the second wafer region 31b. Then, as shown in FIGS. 3C and 4C, a plurality of first connection lines 3 2 2a and a plurality of second connection lines 2b are formed on the crystal j3 0 2 by, for example, plating or the like. Among these, the first connections The lines "through one end are respectively passed through the I holes 318, and are electrically connected to the first pads 31", and the other ends of the first and connection lines 3 22a extend to the first chip area 31a. back

200531186

316, and a first bonding pad 3 24a is formed respectively. In addition, one end of the second connection lines 3 2 2 b also passes through the through holes 318, respectively, and ^ = is on the second pads 314b, and the other end of the second connection line 3 2 2b extends to the second chip area. 3 丨 0b on the back surface 316, and respectively form a second joint 塾 3 24b. It is worth noting that, because the first connection line 3 2 2 a and the second connection line 3 2 2b are formed by electroplating at the same time, the first connection line 3 2 2 a located partially within the through hole 318 may be located partially The first connection lines 322b within the through holes 318 are connected. Next, as shown in FIGS. 3D and 4D, a first hard cover body 32 0 & and a second hard cover body 3 2 0 b are respectively adhered to the first chip area 310 a through an adhesive layer 33 0. The active surface 312 and the main surface of the second wafer region 3 10b, the surface 3 1 2. In addition, in order to meet heat dissipation requirements or electrical function considerations, the materials of the first hard cover 320a and the second hard cover 320b may be conductive, insulating, or transparent. In addition, since the wafer packaging process of the present invention can adopt a wafer-level packaging process, the first hard cover 320a and the first hard cover 320b can also be formed integrally, that is, the first hard negative cover 320a and the first The two hard cover bodies 320b can be structurally connected to each other by a connecting rod 320c or a connection structure of other shapes. In this way, the positioning of the first hard cover body 32a and the first hard cover body can be completed. The step of disposing two hard covers 320b on the active surface 312 of the wafer 302. Next, as shown in FIGS. 3E and 4E, for example, by mechanical cutting or laser cutting, etc., along the boundary between the first wafer region 3 i 〇a and the second wafer region 3 1 0 b of the wafer 3 2 The wafer 3 02 is cut at the same time, and the first connection line 3223 partially located in the through hole 318 and the connected part is located in the through hole at the same time.

200531186

A connection line within 3 2 2 b. Therefore, the side edge of the wafer 3 1 0 will have a recessed surface 318a (ie, half of the original through-holes 318), which is recessed on the surface of the side edge of the wafer 3 1 0, and the local lines of these connection lines 3 2 2 They are respectively disposed on the 14 recessed surfaces 3 丨 8 a, so that the connection lines 3 2 2 I respectively extend through the recessed surfaces 318 a, and are electrically connected between the corresponding coasters 314 and the bonding pads 324. In addition, when the first hard cover body 32 0a and the second hard cover body 3 2 0b are formed into one of the above-mentioned structures before cutting, the connecting rods 3 2 0 c can be cut at the same time to separate the first hard cover body. The cover body 320a and the second hard cover body 320b. Finally, as shown in Figures 3F and 4F, for example, the first wafer region 3 i 〇a and the second wafer region 3 1 0 b of the wafer 3 are individually separated by mechanical cutting or laser cutting. In other parts of the wafer 3 02, the first wafer region 310a and the first hard cover 32a of the wafer 3 02 become a first wafer package 3 0a, and the wafer 3 02 The second chip region 3 10b and the second hard cover 320b become a second chip package 300b. Please refer to FIG. 5, which is a cross-sectional view of the chip package of FIG. 3F assembled to a printed circuit board. The chip package 300 may include a chip 310, a hard cover body 320, and an adhesive layer 3300. The chip 310 is approximately a rectangle ', and has an active surface 312 and a corresponding back surface 316'. The chip 310 further has a plurality of bonding pads 314, which are disposed on the periphery of the active surface 312, and the connection lines 322 extend to the back surface 3 1 6 of the chip 310 to form a plurality of bonding pads 3 2 4. In addition, a plurality of joints 3, 2 and 4 of the chip package 300 can be passed through a pre-solder block (P re-s ο 1 der), an anisotropic conductive adhesive (ACP), or an anisotropic conductive film ( ACF) and other connection media

12〇l3twf.ptd Page 19 200531186 V. Description of the invention (12) (not shown), and a plurality of bonding pads 3 4 2 connected to the printed circuit board 3 4 0 Please refer to FIG. 6 for a drawing A cross-sectional view of another chip packaging structure according to a second embodiment of the present invention, which is assembled to a printed circuit board. Compared with the bonding pads 3 2 4 arranged peripherally on the back surface 3 1 6 of the wafer 3 1 0 in FIG. 5, the bonding pads 3 2 4 of the wafer package 3 0 1 in FIG. 6 are in an area array. The method is arranged on the back 3 1 6 of the wafer 3 1 0, and the bonding pads 3 2 4 can be connected to the printed circuit board 3 4 0 through a conductive contact 3 5 0 (such as a conductive bump). Bonding pads 3 4 2. Based on the above, the second embodiment of the present invention uses a plurality of connection lines to respectively extend the pads on the active surface of the wafer to the back of the wafer through the side of the wafer, and form a plurality of bonding pads on the back of the wafer. A plurality of conductive contacts are respectively arranged on the bonding pads on the back surface of the wafer. Therefore, when the chip package is bonded to the printed circuit board, the active surface of the chip and the hard cover can be exposed to the outside. When the material of the hard cover is a transparent material, the chip package of the second embodiment is more applicable. For photovoltaic devices or bio-chips such as CMOS Image Sensor (CIS) and Solar Cell 1 (Bio-Chip) ° In summary, the chip package of the present invention and its process A hard cover is arranged on the active surface of the chip to protect the active surface of the chip and increase the structural strength of the chip package. In addition, when the material of the hard cover is a thermally conductive material such as copper or aluminum alloy, the hard cover can improve the heat dissipation performance of the chip package. In addition, when the material of the hard cover is a conductive material or

12013twf.ptd Page 20 200531186 V. Description of the invention (13) With a conductive layer, a hard cover plate electrically connected to the ground end of the chip can further reduce electromagnetic interference from the outside world to the chip. In addition, when the material of the hard cover is transparent so that light can illuminate the active surface of the chip, the chip package is more suitable for packaging types such as photovoltaic elements or biochips. In addition, the wafer packaging process of the present invention can further form a plurality of bonding pads on the back surface of the wafer, so that the chip package can be bonded to a circuit board (PCB) or a substrate through these bonding pads on the back surface of the wafer (Substrate) multiple contacts. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

12013twf.ptd Page 21 200531186 Brief Description of Drawings Figure 1A shows a top view of the first chip package of the first embodiment of the present invention. Figure 1B is a cross-sectional view taken along line I-I / of Figure 1A. FIG. 1C is a cross-sectional view of the first chip package of FIG. 1A assembled to a printed circuit board. Figure 2A is a top view of a second chip package according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view taken along line Π-Π / of FIG. 2A. FIG. 2C shows a cross-sectional view of the second chip package of FIG. 2A assembled to a printed circuit board. 3A to 3F are top views of a wafer-level wafer packaging process according to a second embodiment of the present invention. Figures 4A to 4F are cross-sectional views of plates III / I of Figures 3A to 3F, respectively. FIG. 5 is a cross-sectional view of the chip package of FIG. 3F assembled to a printed circuit board. FIG. 6 is a cross-sectional view of another chip package according to a second embodiment of the present invention, which is assembled to a printed circuit board. [Illustration of Graphical Symbols] 1 0 0: Chip package 1 1 0: Chip 1 1 2: Active surface 1 1 4: Solder pad 1 1 6: Conductive contact

12013twf.ptd Page 22 200531186 Brief description of the drawing 120 Hard cover 130 Adhesive layer 140 Printed circuit board 142 Bonding pad 200 Chip package 2 10 Chip 2 12 Active surface 2 14 Fresh pad 2 16 Conductive contact 220 Hard cover 230 Adhesive layer 240 Printed circuit board 242 Bonding pad 3 0 a: First chip package 3 0 0 b: Second chip package 3 0 1: Chip package 3 0 2 · Wafer 3 1 0: Chip 3 1 0 a: first wafer area 3 1 0 b: second wafer area 3 1 2: active surface 3 1 4: pad 3 1 4 a: first pad 314b: second pad

12013twf.ptd Page 23 200531186 Schematic description

316: back surface 318: through hole 318a: recessed surface 3 2 0: hard cover body 3 2 0 a: first--hard cover body 3 2 0 b: second hard cover body 3 2 0 c: connecting rod 3 2 2: Connection line 3 2 2 a: No.--Connection line 3 2 2b See also-• Le one two connection line 3 2 4: Bonding pad 3 2 4a •• No.--Bonding pad 32 4b • Enough-• Fun one •- Bonding pad 3 3 0: Adhesive layer 34 0 ·· Printed circuit board 34 2 ·· Bonding pad 3 5 0: Conductive contact 12013twf.ptd Page 24

Claims (1)

200531186 VI. Scope of patent application 1. A chip package including at least: a chip having an active surface and a plurality of pads, wherein the pads are disposed on the active surface; and a hard cover is disposed on the The active surface of the chip, but the pads are exposed above the active surface. 2. The chip package according to item 1 of the patent application scope, wherein the chip further has a redistribution layer disposed on the active surface and forming the solder pads. 3. The chip package according to item 1 of the scope of patent application, wherein the hard cover system is disposed on the active surface of the chip in an adhesive manner. 4. The chip package according to item 1 of the scope of the patent application, wherein the periphery of the hard cover is arranged on the active surface of the chip in an adhesive manner. 5. The chip package as described in item 1 of the scope of patent application, wherein the material of the hard cover body includes conductive materials, insulating materials and transparent materials. Among them-〇6. The chip package as described in item 1 of the scope of patent application The body further includes a plurality of conductive contacts, which are respectively disposed on the pads, and the height of the conductive contacts relative to the active surface is greater than the height of the hard cover relative to the active surface. 7 · The chip package as described in item 1 of the patent application scope, wherein the pads are arranged on the periphery of the active surface. 8 · The chip package according to item 7 of the scope of the patent application, wherein the active surface of the chip is rectangular in outline, and the pads are disposed in the 12013twf.ptd Page 25 200531186 6. Scope of Patent Application At least one side of the periphery of the active surface. 9. The chip package according to item 7 of the scope of patent application, wherein the chip further has a back surface opposite to the active surface and a plurality of connection lines, and one end of the connection lines is respectively connected to the pads. Moreover, the connection lines respectively extend to the back surface of the wafer through the side edge surfaces of the wafer, and form a bonding pad on the back surface of the wafer, respectively. 10. The chip package according to item 9 of the scope of patent application, wherein the bonding pads are arranged on the periphery of the back surface of the chip. 1 1. The chip package according to item 9 of the scope of patent application, wherein the bonding pads are arranged on the back surface of the chip in a surface array manner. 1 2. The chip package according to item 9 of the scope of the patent application, wherein the side edge of the chip further includes a recessed surface, which is relatively recessed at the side edge of the chip, and the connection line is partially disposed at The recessed surface. 1 3. The chip package according to item 9 of the scope of patent application, further comprising a plurality of conductive contacts, which are respectively arranged on the bonding pads. 14. The chip package according to item 1 of the scope of the patent application, wherein the pads are arranged on the active surface of the chip in a surface array manner, and the hard cover has a plurality of openings. Corresponding to these corresponding welding castles *. 1 5. A wafer packaging process at least includes: providing a wafer, wherein the wafer has an active surface and a corresponding back surface, and the wafer has a first wafer region and an adjacent second wafer region The wafer further has a plurality of first pads and a plurality of second pads, which are respectively disposed on the active surface and the second pad of the first wafer region. 12013twf.ptd Page 26 200531186 VI. The active surface of the patent application wafer area; forming a plurality of through holes on the wafer, and the through holes penetrate the wafer and connect the active surface and the back surface, And sequentially arranged at the junction of the first chip region and the second chip region; forming a plurality of first connection lines and a plurality of second connection lines on the wafer, wherein one end of the first connection lines is Passed through the through holes, respectively, and are electrically connected to the first solder pads, and the other ends of the first connection lines extend to the back surface of the first chip region, and respectively form a first bond. Pads on the back surface of the first chip region, and one ends of the second connection lines also pass through the through holes, respectively, and are electrically connected to the second pads, and the second connection lines The other end further extends to the back surface of the second wafer region, and a second bonding pad is formed on the back surface of the second wafer region, respectively, and the first connection lines partially located within the through holes are connected. A second connection line partially located within the through holes; a first hard cover and a second hard cover are respectively disposed on the active surface of the first chip region and the active surface of the second chip region ; Cutting the wafer along the junction of the first wafer region and the second wafer region of the wafer, and simultaneously cutting the first connection lines and the connected parts located inside the through holes at the same time; The second connection lines within the through-holes; and the first wafer region and the second wafer region of the wafer are individually separated from other parts of the wafer in a cutting manner, so that the该 第 The first 12013twf.ptd Page 27 200531186 VI. Patent application scope A wafer area and the first hard cover body become a first chip package, and the second wafer area of the wafer and the second hard cover body become one The second chip package. 16. The wafer packaging process according to item 15 of the scope of patent application, wherein before the first wafer region and the second wafer region of the wafer are separated from the other parts of the wafer by cutting, respectively Furthermore, it includes forming a plurality of conductive contacts on the first bonding pads and the second bonding pads. 1 7. The chip packaging process according to item 15 of the scope of the patent application, wherein the first hard cover system is disposed on the active surface of the first chip region in an adhesive manner. 1 8. The chip packaging process according to item 15 of the scope of patent application, wherein the periphery of the first hard cover is arranged on the active surface of the first chip region in an adhesive manner. 19 9. The chip packaging process according to item 15 of the scope of patent application, wherein the material of the first hard cover includes one of a conductive material, an insulating material, and a transparent material. 20. The chip packaging process according to item 15 of the scope of the patent application, wherein the first bonding pads are disposed on the outer periphery of the back surface of the first chip region. 2 1. The chip packaging process according to item 15 of the scope of patent application, wherein the first bonding pads are arranged on the back surface of the first chip region in a surface array manner. 2 2. The chip packaging process as described in item 15 of the scope of patent application, in which the first connection lines are partially formed in the through holes. 12013twf.ptd Page 28 200531186 6. Scope of Patent Application The method includes electroplating. 2 3. The chip packaging process according to item 15 of the scope of patent application, wherein when the first hard cover and the second hard cover are configured, the first hard cover and the second hard cover system are mutually It is structurally connected, and when cutting the wafer, it further includes cutting the connecting portion of the first hard cover and the second hard cover to separate the first hard cover and the second hard cover. 12013twf.ptd Page 29