CN104576637B - 3d集成电路及其形成方法 - Google Patents

3d集成电路及其形成方法 Download PDF

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Publication number
CN104576637B
CN104576637B CN201410553385.4A CN201410553385A CN104576637B CN 104576637 B CN104576637 B CN 104576637B CN 201410553385 A CN201410553385 A CN 201410553385A CN 104576637 B CN104576637 B CN 104576637B
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layer
dielectric
barrier layer
dielectric layer
porous
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CN104576637A (zh
Inventor
匡训冲
朱彦璋
萧清泰
刘丙寅
赵兰璘
杜友伦
蔡嘉雄
陈晓萌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了3D集成电路及其形成方法。一种集成电路结构包括封装组件，该封装组件进一步包括具有第一孔隙率的非多孔介电层和位于该非多孔介电层上方并与该非多孔介电层接触的多孔介电层，其中多孔介电层的第二孔隙率高于第一孔隙率。接合焊盘穿透非多孔介电层和多孔介电层。介电势垒层位于多孔介电层上方并与多孔介电层接触。通过介电势垒层而暴露接合焊盘。介电势垒层具有平坦顶面。接合焊盘的平坦顶面高于介电势垒层的底面。

Description

3D集成电路及其形成方法
技术领域
本发明一般地涉及半导体技术领域，更具体地，涉及3D集成电路及其形成方法。
背景技术
在晶圆与晶圆接合技术中，已经开发出了各种方法以将两个封装组件(诸如晶圆)接合至一起。可利用的接合方法包括熔融接合、共晶接合、直接金属接合、混合接合等等。在熔融接合中，晶圆的氧化物表面接合至另一个晶圆的氧化物表面或硅表面。在共晶接合中，两种共晶材料放置在一起，并且施加特定的压力和温度。在不同的条件下，共晶材料熔化。当熔化的共晶材料凝固时，晶圆接合至一起。在直接金属与金属接合中，两个金属焊盘在升高的温度下彼此挤压，金属焊盘的互相扩散导致金属焊盘的接合。在混合接合中，两个晶圆的金属焊盘通过直接金属与金属接合来彼此接合，并且两个晶圆其中之一的氧化物表面接合至另一个晶圆的氧化物表面或硅表面。
先前开发的接合方法具有它们的缺点。例如，对于熔融接合而言，需要额外的电连接件将接合晶圆互连。共晶接合的精确性较低，并且可能存在由于接合金属的熔化所导致的金属挤压。直接的金属与金属接合的产量也较低。在混合接合中，金属焊盘具有比接合的晶圆表面上的介电层更高的热膨胀系数(CTE)。这会导致介电层接合的问题。例如，如果金属焊盘的膨胀体积小于金属焊盘的凹陷体积，则金属焊盘之间的接合会分层。相反，如果金属焊盘的膨胀体积明显大于凹陷体积，则介电层之间的接合会分层。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，一种集成电路结构，包括：第一封装组件，包括：非多孔介电层，具有第一孔隙率；多孔介电层，位于所述非多孔介电层上方并与所述非多孔介电层接触，其中，所述多孔介电层的第二孔隙率高于所述第一孔隙率；第一接合焊盘，穿透所述非多孔介电层和所述多孔介电层；以及第一介电势垒层，位于所述多孔介电层上方并且与所述多孔介电层接触，其中，通过所述第一介电势垒层而暴露所述第一接合焊盘，所述第一介电势垒层具有平坦顶面，并且所述第一接合焊盘的第二平坦顶面高于所述第一介电势垒层的底面。
该集成电路结构进一步包括：第二封装组件，与所述第一封装组件接合，其中，所述第二封装组件包括：第二接合焊盘，通过金属与金属接合与所述第一接合焊盘接合；以及第二介电势垒层，与所述第一介电势垒层接合。
在该集成电路结构中，所述第二孔隙率介于大约5％和大约40％之间。
在该集成电路结构中，所述多孔介电层的介电常数小于大约3.8。
在该集成电路结构中，所述接合焊盘的竖直边缘从所述第一介电势垒层连续地延伸到所述非多孔介电层的底面。
在该集成电路结构中，所述第一介电势垒层包括无机介电材料。
在该集成电路结构中，所述第一介电势垒层包括有机介电材料。
根据本发明的另一方面，提供了一种集成电路结构，包括：第一管芯，包括：顶部金属间介电层(IMD)，包括低k介电材料；顶部金属部件，位于所述顶部IMD中；蚀刻停止层，位于所述顶部金属部件和所述顶部IMD上方；非多孔介电层，位于所述蚀刻停止层上方并与所述蚀刻停止层接触；多孔介电层，位于所述非多孔介电层上方并与所述非多孔介电层接触；第一介电势垒层，位于所述多孔介电层上方；和第一接合焊盘，从所述第一介电势垒层的顶面延伸到所述顶部金属部件；以及第二管芯，包括：第二接合焊盘，与所述第一接合焊盘接合；和第二介电势垒层，与所述第一介电势垒层接合。
在该集成电路结构中，所述非多孔介电层由非掺杂硅酸盐玻璃(USG)或氧化硅形成。
在该集成电路结构中，所述多孔介电层包括低k介电材料。
在该集成电路结构中，所述第一介电势垒层包括氮氧化硅。
在该集成电路结构中，所述第一介电势垒层包括基于硅氧烷的聚合物。
在该集成电路结构中，所述第一接合焊盘包括从所述第一介电势垒层的顶面连续地延伸至所述顶部金属部件的导电势垒层。
在该集成电路结构中，所述第一接合焊盘包括：导电势垒层；以及含铜材料，位于所述导电势垒层上方。
根据本发明的又一方面，提供了一种方法，包括：形成第一管芯，包括：在顶部金属部件上方形成非多孔介电层；形成位于所述非多孔介电层上方并与所述非多孔介电层接触的多孔介电层；在所述多孔介电层上方形成第一介电势垒层；蚀刻所述非多孔介电层和所述多孔介电层以形成开口，其中通过所述开口而暴露所述顶部金属部件；用金属材料填充所述开口，以在所述开口中形成第一接合焊盘；以及将所述第一管芯接合至第二管芯，其中所述第一接合焊盘接合至所述第二管芯中的第二接合焊盘，并且所述第一介电势垒层接合至所述第二管芯中的第二介电势垒层。
在该方法中，形成所述第一介电势垒层包括：在形成所述接合焊盘之前，形成覆盖式介电势垒层，并且在所述蚀刻步骤中对所述覆盖式介电势垒层进行图案化以形成所述第一介电势垒层。
在该方法中，形成所述第一介电势垒层包括：在形成所述接合焊盘之后，形成覆盖式介电势垒层；以及执行光刻以使所述覆盖式介电势垒层图案化并形成所述第一介电势垒层。
在该方法中，将所述第一管芯接合至所述第二管芯包括：在升高的温度下执行预接合；对所述第一管芯和所述第二管芯进行固化；并且对所述第一管芯和所述第二管芯执行热退火。
在该方法中，当执行所述接合时，所述第一管芯是未切割的第一晶圆的一部分，所述第二管芯是未切割的第二晶圆的一部分，并且所述方法还包括：在所述接合之后，从所述第一晶圆和所述第二晶圆上切割所述第一管芯和所述第二管芯。
在该方法中，在相同光刻工艺中蚀刻所述非多孔介电层和所述多孔介电层。
附图说明
为了更完全地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图5是根据一些示例性实施例形成第一封装组件的中间阶段的横截面视图；
图6至图9是根据可选实施例形成第一封装组件的中间阶段的横截面视图；
图10示出了根据可选实施例的第二封装组件的横截面视图；以及
图11示出了根据一些示例性实施例的两个封装组件的接合的横截面视图。
具体实施方式
在下文中详细地讨论了本公开内容的不同实施例的制作和使用。然而，应当理解，实施例提供了可以在广泛的特定背景下实施的很多适用的构思。讨论的特定实施例是说明性的，并且不限制本公开内容的范围。
根据不同的示例性实施例提供了包括混合接合的封装件和形成这种封装件的方法。示出了形成这种封装件的中间阶段。讨论了实施例的变型例。在各个附图和所有的说明性的实施例，相同的附图标记用于指示相同的元件。
图1至图5示出了根据一些实施例形成封装组件的中间阶段的横截面视图。参照图1，示出了封装组件100。封装组件100可以包括器件晶圆、封装晶圆、中介层晶圆等。在实施例中，封装组件100包括器件晶圆，封装组件100包括可以是例如硅衬底的半导体衬底102。诸如碳化硅衬底、锗化硅衬底和III-V族化合物半导体衬底的其它半导体衬底也是可用的。有源器件104可以形成在衬底102的表面上，并且可以包括例如晶体管。金属线和通孔106形成在介电层108中，该介电层108可以包括层间介电层(ILD)、金属间介电(IMD)层、钝化层等。在一些实施例中，ILD层和IMD层可以是低k介电层，该低k介电层具有小于预定值的介电常数(k值)，诸如小于大约3.5、小于大约3.0、小于大约2.5等。介电层108可以包括介电常数(k值)等于或大于3.8的非低k介电材料。金属导线106(包括金属线和通孔)可以包括铜、铝、镍、钨或其合金。金属线和通孔106使有源器件104互连，并且使有源器件104电连接到上面的金属部件112。
在可选实施例中，封装组件100是其中没有有源器件的中介层晶圆。根据一些实施例，封装组件100可以包括或可以不包括无源器件(未示出)，诸如电阻器、电容器、电感器、变压器等。
在又一可选实施例中，封装组件100是封装衬底。在一些实施例中，封装组件100是层压封装衬底，其中导线106嵌入示意性示出的层压介电层108中。在可选实施例中，封装组件100是组合封装衬底，该组合封装衬底包括芯体(未示出)和建立在芯体的相对侧上的导线(由轨道106来表示)。组合封装衬底的芯体包括纤维层(未示出)和穿过纤维层的金属部件(未示出)，其中，通过金属部件互连导线。通过芯体中的导电部件来互连导线106。
在封装组件100是器件晶圆、中介层晶圆、封装衬底等的不同实施例中，形成可以是顶部IMD层的介电层110。在一些实施例中，介电层110是k值低于大约3.0、低于大约2.5或低于大约2.0的低k介电层。在可选的实施例中，介电层110包括氧化硅、氮氧化硅、氮化硅等。金属部件112形成在介电层110中并且可以通过金属线和通孔106电耦合到有源器件104。金属部件112可以是金属线或金属焊盘。金属部件112也可以由铜、铝、镍、钨、上述金属的合金或其它适当的材料来形成。介电层110的顶面和金属部件112的顶面可以基本上彼此齐平。在封装组件100为器件晶圆的实施例中，介电层110和金属部件112可以位于衬底102的正面(具有有源器件104的面)或背面(衬底102之下的面)上。例如，图1示出介电层110和金属部件112位于衬底102的正面上。
金属线和通孔106与金属部件112中的每个或一些可以包括含铜区域(未示出)和将含铜区域与相应的介电层分离的导电势垒层。导电势垒层可以包括钛、氮化钛、钽、氮化钽等。
参照图2，形成了多层。在一些实施例中，多层包括蚀刻停止层114、蚀刻停止层114上方的非多孔介电层116、非多孔介电层116上方的多孔介电层118和多孔介电层118上方的介电势垒层120。多层中的上面的层可以与相应的下面的层物理接触。在一些实施例中，蚀刻停止层114包括碳化硅、氮化硅、氮氧化硅或其它介电材料。非多孔介电层116还可以是k值等于或高于大约3.8的非低k介电层。而且，非多孔介电层116的孔隙率可以低于大约5％。当孔隙率低于大约5％时，非多孔介电层116不具有释放由于封装组件100和200(图11)的连续接合所产生的应力的功能。在一些示例性的实施例中，非多孔介电层116由非掺杂硅酸盐玻璃(USG)、氧化硅等形成。非多孔介电层116的形成方法可以包括化学汽相沉积(CVD)法，诸如高密度等离子体CVD(HDPCVD)、等离子体增强化学汽相沉积(PECVD)、原子层沉积(ALD)等。
多孔介电层118还可以是k值低于3.8或低于大约3.0的低k介电层。k值低于3.8的低k介电材料是低k介电材料。介电层118的k值还可以在大约2.5至3.0之间。而且，多孔介电层118的孔隙率高于非多孔介电层116的孔隙率。例如，多孔介电层118的孔隙率可以高于大约5％并低于大约40％。当多孔介电层118的孔隙率达到大约5％时，多孔介电层118开始释放由封装组件100和200(图11)的连续接合所产生的应力。当多孔介电层118的孔隙率进一步增加时，应力得到更好地释放。因为当多孔介电层118的孔隙率达到大约40％时，多孔介电层118可能会破裂，所以多孔介电层118的孔隙率选择为低于大约40％。在一些示例性实施例中，多孔介电层118包括含碳电介质。非多孔介电层116的形成方法可以包括SiO2、磷硅酸盐玻璃(PSG)、掺氟硅酸盐玻璃(FSG)等。
介电势垒层120包括介电材料，例如，该介电材料可以是基于硅的电介质，诸如氮化硅、氮氧化硅，等等。介电势垒层120具有通过熔融接合而接合至另一个管芯/晶圆的功能，并且还可以阻止铜扩散通过。
参照图3，通过光刻工艺来执行蚀刻步骤，因此在介电层114、116、118和120中形成开口122。在蚀刻步骤中，蚀刻停止层114用于停止蚀刻，然后，进一步对蚀刻停止层114进行蚀刻以暴露下面的金属部件112。因此，开口122具有从介电势垒层120的顶面连续延伸到金属部件112的顶面的侧壁124。根据一些实施例，侧壁124基本上是基本垂直于衬底102的顶面102A的竖直侧壁，但是侧壁124也可以是倾斜的。
接下来，导电势垒层126和金属材料128填充到开口122中，从而生成图4所示的结构。在一些实施例中，导电势垒层126包括钛、氮化钛、钽、氮化钽、它们的组合、由它们的多层或其它材料。金属材料128可以是基本上包括纯铜或铜合金的含铜材料。金属材料128还可以包括铝、镍等。
然后，执行诸如化学机械抛光(CMP)的平坦化。介电势垒层120可以用作CMP停止层。因此，剩余的金属材料128的顶面与介电势垒层120的顶面共面。图5示出了生成的结构。在下文中，导电势垒层126和相应的上面的金属材料128的剩余部分统称为接合焊盘130。在一些实施例中，金属焊盘130可以包括凹陷。如图5所示，每个接合焊盘130具有从介电势垒层120的顶面连续延伸到金属部件112的基本上竖直的边缘。
图6至图9示出了根据可选实施例的接合焊盘130和介电势垒层120的形成。除了在接合焊盘130形成之后，形成介电势垒层120(图9)并且可以使用诸如基于硅氧烷聚合物的有机材料形成该介电势垒层之外，这些实施例类似于图1至图5中的实施例。参照图6，形成蚀刻停止层114、非多孔介电层116和多孔介电材料118。随后在层114、116和118中形成开口122，使得暴露下面的金属部件112。接下来，参照图7，导电势垒层126和金属材料128填充到开口122中。随后执行CMP以去除导电势垒层126和金属材料128的多余部分，从而形成如图8所示的接合焊盘130。生成的接合焊盘130的顶面与多孔介电材料118的顶面共面，但是有时接合焊盘130可以存在凹陷。在随后的步骤中，如图9所示，在接合焊盘130和多孔介电材料118上方形成了覆盖式介电势垒层120。随后执行光刻工艺以去除覆盖式介电势垒层120的部分，从而去除覆盖接合焊盘130的部分。可以使用光刻胶132作为蚀刻掩模来执行光刻工艺。在对介电势垒层120进行图案化之后，去除光刻胶132。
在一些实施例中，介电势垒层120包括基于硅氧烷的聚合物。例如，该基于硅氧烷的聚合物可以是由Shin-Etsu Chemical Co.,LTD(Shin-Etsu化学有限责任公司)所提供的SINRTM。介电势垒层120的厚度T1可以小于大约1μm，使得在随后的接合工艺中，膨胀的金属材料128(例如，当加热时)可以从介电势垒层120的顶面凸起，并且与另一个晶圆/管芯中的金属焊盘接触。
图10示出了要接合至图5或图9中的封装组件100的封装组件200。封装组件200可以具有类似于关于封装组件100(图5和图9)所描述的结构，并且在本文中不再重复具体细节。可以参照如参照图1至图9描述的封装组件100中的相同部件来找到封装组件200中的部件的材料。与封装组件100中的部件相对应的部件具有以数字“1”开始的附图标记，而与封装组件200中的部件相对应的部件具有以数字“2”开始的附图标记。
还可以从器件晶圆、中介层晶圆、封装衬底等中选择封装组件200。在所示的图10中，封装组件200包括衬底202、有源器件204、介电层208、介电层208中的金属线和通孔206。在可选实施例中，封装组件200不包括诸如晶体管、二极管等的有源器件。
在一些实施例中，封装组件200还可以包括蚀刻停止层214、非多孔介电层216、多孔介电层218、介电势垒层220和接合焊盘230。接合焊盘230可以进一步包括导电势垒层226和介电势垒层216上方的含铜的金属材料228。
在可选实施例中，封装组件200可以不包括多孔介电层218。更确切地说，导电势垒层226可以直接形成在非多孔介电层216上方并且与非多孔介电层216接触，该非多孔介电层216可以包括USG、氧化硅等。在这些实施例中，在随后的接合工艺中施加给已接合的接合焊盘130/230(图11)和介电层的应力被封装组件100中的多孔介电层118所吸收。
接下来，如图11所示，预接合封装组件100和200。在预接合中，首先通过将封装组件100的接合焊盘130与封装组件200的接合焊盘230对准而将封装组件100和200对准。在对准之后，封装组件100和200彼此挤压。在预接合期间，可以施加压紧力，以使封装组件100和200彼此挤压，其中例如，压紧力可以低于大约每管芯5牛顿。在介电势垒层120和220由无机材料形成的实施例中，可以在室温下(例如，在大约21℃至25℃之间)执行预接合，但是可以使用较高或较低的温度。例如，接合时间可以短于大约1分钟。
在介电势垒层120和220由诸如SINR的有机材料形成的实施例中，可以在大约140℃和大约160℃之间的范围内的升高的温度下执行预接合。例如，预接合可以持续大约1分钟和大约5分钟之间的范围内的时间周期。此外，在预接合之后，可以执行固化工艺以将介电势垒层120和220中的溶剂驱赶到相应的封装组件100和200之外。在一些示例性实施例中，在大约170℃和大约190℃之间的范围内的温度下执行固化。例如，固化可以持续大约60分钟和大约120分钟之间的范围内的时间周期。在介电势垒层120和220由无机材料形成的实施例中，可以省略固化步骤。
在预接合之后，介电势垒层120和220彼此接合。然而，在一些实施例中，在随后的退火步骤中改进了接合强度。可以在例如大约300℃和大约400℃之间的温度下对接合的封装组件100和200进行退火。可以大约1小时和2小时之间的时间周期内执行退火。当温度升高时，表面介电层110和210中的氢氧(OH)键(如果有的话)破裂以形成强Si-O-Si键，因此封装组件100和200通过熔化接合(并且通过范德瓦尔斯力)而彼此接合。此外，在退火期间，接合焊盘130和230中的诸如铜的金属彼此互相扩散，使得也形成金属与金属接合。在不同的实施例中，封装组件100与200之间生成的接合称为混合接合，其包括金属与金属接合与Si-O-Si键合，并且不同于仅有金属与金属接合或仅有Si-O-Si键合。在接合之后，接合的封装组件100和200被切割为多个封装件300。每个封装都包括管芯100′和管芯200′，它们分别为封装组件100和200的分离部分。
在接合工艺中，温度上升到室温(例如，大约21℃)之上，并且接合焊盘130和230膨胀。接合焊盘130和230的热膨胀系数(CTE)高于介电材料(诸如114/214、116/216、118/218和120/220等)的热膨胀系数(CTE)。因此，可以施加应力以将介电势垒层120和220拉至彼此分离。在接合工艺的升高的温度之后，对封装组件100和200进行冷却。在接合工艺的冷却阶段期间，另一方面，接合焊盘130和230收缩，从而导致应力产生。应力施加到接合焊盘和介电材料上。这些应力会导致接合焊盘和介电层的分层。在本公开内容的不同实施例中，多孔介电层具有吸收应力的功能，因此减少金属焊盘和介电层的分层。
在图11示出的接合结构中，应力出现在靠近封装组件100与200之间界面的区域中。应力在不同区域具有不同值。模拟结果显示最高应力很可能出现在介电势垒层120和220的界面与相互扩散的接合焊盘130和230结合的位置处。如果使用非多孔材料，应力会导致介电势垒层120和220的分层和/或接合焊盘130和230的分层。在不同的实施例中，对图11所示的结构进行了应力模拟。从模拟获得的结果显示，在采用实施例的结构的第一组样本中，发现无介电分层和金属焊盘分层。作为比较，也形成具有与实施例类似结构的第二组样本，其中第二组样本使用USG以形成层116和118。结果显示第二组样本具有大约30％至大约80％的介电分层百分比，和大约10％至大约50％的金属焊盘分层百分比。
根据一些实施例，集成电路结构包括封装组件，该封装组件进一步包括具有第一孔隙率的非多孔介电层和在非多孔介电层上并与非多孔介电层接触的多孔介电层，其中多孔介电层的第二孔隙率高于第一孔隙率。接合焊盘穿过非多孔介电层和多孔介电层。介电势垒层位于多孔介电层上方并与多孔介电层接触。通过介电势垒层暴露接合焊盘。介电势垒层具有平坦的顶面。接合焊盘的平坦顶面高于介电势垒层的底面。
根据其它实施例，集成电路结构包括第一管芯和第二管芯。第一管芯包括具有低k介电材料的顶部IMD、顶部IMD中的顶部金属部件、位于顶部金属部件和顶部IMD上方的蚀刻停止层、位于蚀刻停止层上方并且与蚀刻停止层接触的非多孔介电层，以及位于非多孔介电层上方并且与非多孔介电层接触的多孔介电层。第一管芯进一步包括多孔介电层上方的第一介电势垒层，并且第一接合焊盘从第一介电势垒层的顶面延伸到顶部金属部件。第二管芯包括与第一接合焊盘接合的第二接合焊盘，以及与第一介电势垒层接合的第二介电势垒层。
根据又一实施例，方法包括形成第一管芯，该第一管芯包括在顶部金属部件之上形成非多孔介电层、形成位于非多孔介电层上方并且与非多孔介电层接触的多孔介电层、在多孔介电层上方形成第一介电势垒层并且蚀刻非多孔介电层和多孔介电层以形成开口，其中通过开口暴露顶部金属部件。第一管芯的形成进一步包括用金属材料填充开口，以在开口中形成第一接合焊盘。第一管芯随后与第二管芯接合，其中第一接合焊盘与第二管芯中的第二接合焊盘接合，并且第一介电势垒层与第二管芯中的第二介电势垒层接合。
虽然已经详细地描述了不同实施例及其优点，但是应该理解的是在本文中，在不脱离由所附权利要求限定的实施例的精神和范围的情况下，可以进行各种改变、替代和变更。此外，本申请的范围不意图限于说明书中描述的工艺、机器、制造、物质组分、装置、方法和步骤的特定实施例。本领域的普通技术人员通过本发明的公开内容容易理解，可以根据本发明来利用基本上执行与本文中描述的相应实施例相同功能或基本上实现相同结果的当前存在或随后开发的工艺、机器、制造、物质组分、装置、方法或步骤。因此，所附权利要求旨在在其范围内包括这些工艺、机器、制造、物质组分、装置、方法或步骤。此外，每项权利要求都构成单独的实施例，并且不同的权利要求和实施例的组合都在本公开内容的范围内。

Claims (19)

1.一种集成电路结构，包括：
第一封装组件，包括：
非多孔介电层，具有第一孔隙率；
多孔介电层，位于所述非多孔介电层上方并与所述非多孔介电层接触，其中，所述多孔介电层的第二孔隙率高于所述第一孔隙率；
第一接合焊盘，穿透所述非多孔介电层和所述多孔介电层；以及
第一介电势垒层，位于所述多孔介电层上方并且与所述多孔介电层接触，其中，通过所述第一介电势垒层而暴露所述第一接合焊盘，所述第一介电势垒层具有平坦顶面，并且所述第一接合焊盘的第二平坦顶面高于所述第一介电势垒层的底面；
所述第一接合焊盘的竖直边缘从所述第一介电势垒层连续地延伸到所述非多孔介电层的底面。
2.根据权利要求1所述的集成电路结构，进一步包括：
第二封装组件，与所述第一封装组件接合，其中，所述第二封装组件包括：
第二接合焊盘，通过金属与金属接合与所述第一接合焊盘接合；以及
第二介电势垒层，与所述第一介电势垒层接合。
3.根据权利要求1所述的集成电路结构，其中，所述第二孔隙率介于5％和40％之间。
4.根据权利要求1所述的集成电路结构，其中，所述多孔介电层的介电常数小于3.8。
5.根据权利要求1所述的集成电路结构，其中，所述第一介电势垒层包括无机介电材料。
6.根据权利要求1所述的集成电路结构，其中，所述第一介电势垒层包括有机介电材料。
7.一种集成电路结构，包括：
第一管芯，包括：
顶部金属间介电层(IMD)，包括低k介电材料；
顶部金属部件，位于所述顶部金属间介电层中；
蚀刻停止层，位于所述顶部金属部件和所述顶部金属间介电层上方；
非多孔介电层，位于所述蚀刻停止层上方并与所述蚀刻停止层接触；
多孔介电层，位于所述非多孔介电层上方并与所述非多孔介电层接触；
第一介电势垒层，位于所述多孔介电层上方；和
第一接合焊盘，从所述第一介电势垒层的顶面延伸到所述顶部金属部件；以及
第二管芯，包括：
第二接合焊盘，与所述第一接合焊盘接合；和
第二介电势垒层，与所述第一介电势垒层接合。
8.根据权利要求7所述的集成电路结构，其中，所述非多孔介电层由非掺杂硅酸盐玻璃(USG)或氧化硅形成。
9.根据权利要求7所述的集成电路结构，其中，所述多孔介电层包括低k介电材料。
10.根据权利要求7所述的集成电路结构，其中，所述第一介电势垒层包括氮氧化硅。
11.根据权利要求7所述的集成电路结构，其中，所述第一介电势垒层包括基于硅氧烷的聚合物。
12.根据权利要求7所述的集成电路结构，其中，所述第一接合焊盘包括从所述第一介电势垒层的顶面连续地延伸至所述顶部金属部件的导电势垒层。
13.根据权利要求7所述的集成电路结构，其中，所述第一接合焊盘包括：
导电势垒层；以及
含铜材料，位于所述导电势垒层上方。
14.一种用于制造集成电路结构的方法，包括：
形成第一管芯，包括：
在顶部金属部件上方形成非多孔介电层；
形成位于所述非多孔介电层上方并与所述非多孔介电层接触的多孔介电层；
在所述多孔介电层上方形成第一介电势垒层；
蚀刻所述非多孔介电层和所述多孔介电层以形成开口，其中通过所述开口而暴露所述顶部金属部件；
用金属材料填充所述开口，以在所述开口中形成第一接合焊盘；以及
将所述第一管芯接合至第二管芯，其中所述第一接合焊盘接合至所述第二管芯中的第二接合焊盘，并且所述第一介电势垒层接合至所述第二管芯中的第二介电势垒层。
15.根据权利要求14所述的用于制造集成电路结构的方法，其中，形成所述第一介电势垒层包括：在形成所述第一接合焊盘之前，形成覆盖式介电势垒层，并且在所述蚀刻步骤中对所述覆盖式介电势垒层进行图案化以形成所述第一介电势垒层。
16.根据权利要求14所述的用于制造集成电路结构的方法，其中，形成所述第一介电势垒层包括：
在形成所述第一接合焊盘之后，形成覆盖式介电势垒层；以及
执行光刻以使所述覆盖式介电势垒层图案化并形成所述第一介电势垒层。
17.根据权利要求14所述的用于制造集成电路结构的方法，其中，将所述第一管芯接合至所述第二管芯包括：
在升高的温度下执行预接合；
对所述第一管芯和所述第二管芯进行固化；并且
对所述第一管芯和所述第二管芯执行热退火。
18.根据权利要求14所述的用于制造集成电路结构的方法，其中，当执行所述接合时，所述第一管芯是未切割的第一晶圆的一部分，所述第二管芯是未切割的第二晶圆的一部分，并且所述方法还包括：在所述接合之后，从所述第一晶圆和所述第二晶圆上切割所述第一管芯和所述第二管芯。
19.根据权利要求14所述的用于制造集成电路结构的方法，其中，在相同光刻工艺中蚀刻所述非多孔介电层和所述多孔介电层。
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