CN104205301A - 电子元器件及电子元器件的制造方法 - Google Patents

电子元器件及电子元器件的制造方法 Download PDF

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Publication number
CN104205301A
CN104205301A CN201280071499.4A CN201280071499A CN104205301A CN 104205301 A CN104205301 A CN 104205301A CN 201280071499 A CN201280071499 A CN 201280071499A CN 104205301 A CN104205301 A CN 104205301A
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metal film
electronic devices
components
film
knitting layer
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CN104205301B (zh
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斋藤隆
西泽龙男
木下庆人
梨子田典弘
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

本发明中，在成为半导体元件的正面电极的导电部(1)的表面对以铜为主要成分的第1金属膜(2)进行成膜。在第1金属膜(2)的表面对以银为主要成分的第2金属膜(3)进行成膜。在第2金属膜(3)的表面，经由含有银粒子的接合层(4)接合有金属板(5)，该金属板(5)用于电连接导电部(1)与其他构件(例如绝缘基板(23)的电路图案(24))。在第2金属膜(3)中不包含会使第2金属膜(3)与含有银粒子的接合层(4)的接合强度下降的镍。由此，能够提供具有较高的接合强度及优异的耐热性和散热性的电子元器件(10)以及电子元器件(10)的制造方法。

Description

电子元器件及电子元器件的制造方法
技术领域
本发明涉及电子元器件及电子元器件的制造方法。
背景技术
以往，提出有如下半导体装置，该半导体装置具有在设置于绝缘基板的电路图案上接合半导体元件而成的封装结构。作为将设置于半导体元件正面的电极(以下，称为正面电极)与绝缘基板的电路图案相接合的方法，已知有使用铝(Al)线、焊料来进行接合的方法。图11是表示现有封装结构的半导体装置的主要部分的剖视图。如图11所示，具有半导体元件的半导体芯片101的背面通过焊料接合层102与绝缘基板103的正面的电路图案104相接合。
绝缘基板103的背面与例如由铜(Cu)构成的金属板(以下，称为Cu板)105的正面相接合。Cu板105的背面经由焊料接合层(未图示)与基底构件106的正面相接合。利用热压接或超声波振动将设置于半导体芯片101的正面的未图示的半导体元件的正面电极连接至铝线107，并通过铝线107与电路图案104进行电连接。
图12是表示现有封装结构的半导体装置的另一示例的主要部分的剖视图。如图12所示，半导体芯片101的未图示的正面电极通过金属板108与电路图案104进行电连接。正面电极和电路图案104分别经由焊料接合层102与金属板108相接合。图12所示的半导体装置中除金属板108以外的结构与图11所示的半导体装置相同。此外，在图11、12中，省略对壳体和外部电极用端子的图示。
半导体元件的正面电极例如有铝或铝合金形成。然而，铝与焊料之间的浸润性较差，且无法与焊料牢固地紧密接合。因此，在正面电极与焊料接合层之间，需要形成与正面电极和焊料的密接性较高的凸点下金属膜(under-bump metal film)。作为凸点下金属膜，通常使用无电解Ni/Au镀膜(ENIG)。在半导体元件的正面电极表面，通过实施Ni/Au镀膜，能够使焊料与正面电极牢固地接合。
作为这种实施镀膜的方法，提出了以下方法，即：连续进行使被镀敷材料与去除金离子后的无电解金镀液相接触的工序、以及使被镀敷材料与包含金离子的无电解金镀液相接触的工序(例如，参照下述专利文献1。)。
此外，作为实施镀膜的其他方法，提出了以下方法，即：对形成于基板坯体的表面的导电部实施镀敷处理，依次形成以Ni为主要成分的无电解Ni被膜和以Au为主要成分的置换Au被膜，然后，在进行去除附着于置换Au被膜的Ni化合物的后处理的电子元器件的镀敷方法中，使用从柠檬酸、甘氨酸、乙酸、葡萄糖酸、谷氨酸、酒石酸、乙二胺四乙酸、二乙三安五一酸、苹果酸、丙二酸、亚硫酸、氨基酸、以及氨基磺酸中选择的特定的络合剂作为Ni去除液，在所述后处理中，实施使所述Ni化合物与所述Ni去除液相接触的接触处理，由此从所述置换Au被膜上去除所述Ni化合物(例如，参照下述专利文献2。)。
此外，作为由实施镀膜的其他方法制造得到的电子元器件，提出了如下电子元器件。电子元器件中，在形成于陶瓷坯体的表面的导电部上形成了2层结构的Ni-P被膜，并进一步在该Ni-P被膜的表面形成Au被膜。并且，在Ni-P被膜中，第1层的P含有率在3重量％以上6重量％以下，第2层的P含有率超过6重量％且在9重量％以下，且该Ni-P被膜的厚度在0.1μm以上1.0μm以下(例如，参照下述专利文献3。)。
此外，作为实施镀膜的其他方法，提出了以下方法。在实施镀膜时，经过预处理工序、自催化Ni镀敷工序、置换Au镀敷工序，在形成于陶瓷坯体的表面的Cu电极上依次形成Ni-P被膜和Au被膜。然后，在后处理工序中，将形成有Au被膜的陶瓷坯体作为被干燥物，将被干燥物提供到至少减压至13.3Pa以下的真空干燥装置内，实施真空干燥处理，以去除残留在Ni-P被膜和Au被膜之间的界面中的水分。也可以使用与Ni相比离子化倾向较小的金属来代替Au被膜，具体而言，可使用Ag、Cu、Pd、以及Pt、或者使用它们的合金(例如，参照下述专利文献4。)。
此外，作为实施镀膜的其他方法，提出了以下方法。连接用端子使用在铜板上实施Ni镀敷并进一步在其表面进行金镀敷后得到的材料，在将半导体元件搭载于绝缘基板的布线上之后，对半导体元件的发射极电极(上侧)涂布含有平均粒径为5nm的Au粒子的溶液。接着，对形成于绝缘基板上的铜布线图案的表面实施Ni镀敷处理，并进一步对经由端子与半导体元件的发射极电极相连接的部分进行Au镀敷处理，然后对进行了Au镀敷处理的布线的Au镀敷部分涂布含有Au粒子的溶液。对这些半导体元件和绝缘基板上布线中所涂布的含有Au的溶液进行干燥，形成由金粒子形成的电极部分，然后，将连接用端子搭载于该由金粒子形成的电极的上部，并以80℃加热60分钟，由此来连接半导体元件和布线(例如，参照下述专利文献5。)。
此外，作为实施镀膜的其他方法、以及将半导体元件安装于布线电路的方法，提出了以下方法。在半导体元件的基板金属层上利用无电解镀敷法形成镍类薄层，使用各向异性导电性粘接剂来对该镍类薄层与布线电路进行接合。并且，在形成镍类薄层之后，利用无电解镀敷法形成含有0.1～95重量％的钯和铅或锡的钯合金层，并使用各向异性导电粘接剂将其与布线电路相接合。各向异性导电性粘接剂含有具有突起的粒径为20μm以下和1μm以下的金类、白金类，或银类微粉末来作为导电填料，使用混合有作为粘合剂的环氧类树脂的材料(例如，参照下述专利文献6。)。
此外，作为实施镀膜的其他方法，提出了以下方法。在将半导体元件安装到引线框时，在半导体元件和引线框相接合的区域，实施由Ag、或Ag合金形成的镀膜，并且，在使用包含纳米粒子的导电性粘接剂作为安装过程中的接合材料。导电性粘接剂使用以环氧树脂等热固化性树脂作为基底、且混合粒径为1～20μm的银粒子和20nm以下的银粒子后得到的材料(例如，参照下述专利文献7。)。
此外，作为实施镀膜的其他方法，提出了以下方法。进行以下工序，即：在被接合构件的接合界面形成含有氧的氧化物层的工序；在接合界面配置接合用材料的工序，该接合用材料包含有平均粒径为1nm以上50μm以下的金属化合物粒子和由有机物构成的还原剂；以及通过对被接合构件之间进行加热、加压来接合被接合构件的工序。对于所述被接合构件的接合面，在接合前预先实施以下处理，即：利用无电解镀敷或电镀来析出铜、银或镍之后，使镀敷金属表面氧化(例如，参照下述专利文献8。)。
此外，近年来，作为将半导体元件的正面电极与绝缘基板的电路图案相接合的其他方法，提出了使用含有银(Ag)粒子的接合层来进行接合的方法，以此来取代焊料接合。作为使用含有银粒子的接合层的接合方法，提出了以下方法：使用表面被银纳米粒子接合材料等有机物覆盖的金属粒子作为接合材料，来使利用无电解镀敷或电镀形成的金属表面彼此相接合，由此能够进行具有高耐热性和可靠性、以及高散热性的接合，进而能够在安装工艺的接合过程中实现接合温度的低温化(例如，参照下述专利文献8。)。
在使用含有Ag粒子的接合层的接合中，半导体元件的正面电极和含有Ag粒子的接合层之间的接合部需要是金、银(Ag)等贵金属。由于如上所述半导体元件的正面电极是例如由铝或铝合金形成的，因此，在半导体元件的正面电极的表面难以直接成膜(形成)金镀膜、银镀膜。因而，主要使用具有在半导体元件的正面电极与金镀膜、银镀膜之间夹有Ni镀膜而构成的Ni/Au镀膜、Ni/Ag镀膜。
现有技术文献
专利文献
专利文献1：日本专利第3484367号公报
专利文献2：日本专利第4096671号公报
专利文献3：日本专利特开2006－131949号公报
专利文献4：日本专利特开2004－115902号公报
专利文献5：日本专利特开2005－136375号公报
专利文献6：日本专利特开平7－263493号公报
专利文献7：日本专利特开2007－180059号公报
专利文献8：日本专利特开2008－208442号公报
发明内容
发明所要解决的技术问题
然而，根据发明人反复潜心研究的结果，进一步明确现有技术会产生下述问题。在使用铝线、焊料的接合中，耐热性较低，而在使用导电性粘接剂的接合中，作为粘合剂使用的环氧类树脂的耐热性较低，并且，热传导率也较低，因此，无法提供能够耐受在近年来所要求的高温度环境下的动作(例如，在175℃下连续动作等)的电子元器件。并且，在使用了导电性粘接材料的接合中，使用Ag来作为导电填料，而对于接合，则利用作为粘合剂的环氧类树脂来进行粘接。因此，该粘接原理与使用含有Ag粒子的导电性组合物的接合不同，要求接合的对象物的性质也大不相同。另一方面，使用了含有Ag粒子的接合层的接合中，能够获得高温环境下的耐热性。然而，使用了含有Ag粒子的接合层的接合中，由于半导体元件的正面电极与最表面的镀敷金属之间的接合强度较大程度上取决于镀敷金属的种类、膜厚，因此，为了得到牢固的接合强度，需要对接合条件进行研究。
本发明的目的在于，为了解决上述现有技术中的问题点，提供一种接合强度较高的电子元器件和电子元器件的制造方法。此外，本发明的目的在于，提供一种耐热性较高的电子元器件和电子元器件的制造方法。本发明的目的还在于，提供一种散热性较高的电子元器件和电子元器件的制造方法。
解决技术问题所采用的技术方案
为解决上述问题，达到本发明的目的，本发明所涉及的电子元器件具有下述特征。在半导体元件的表面设有导电部。在所述导电部的表面设有由以铜为主要成分的材料所形成的第1金属膜。在所述第1金属膜的表面设有第2金属膜。此外，第2金属膜由与所述第1金属膜相比离子化倾向较小的金属形成。在所述第2金属膜的表面设有含有银粒子的接合层。
此外，本发明所涉及的电子元器件的特征在于，在上述发明中，所述半导体元件由硅或碳化硅形成，所述导电部由至少以铜或铝为主要成分的材料形成。
本发明所涉及的电子元器件的特征在于，在上述发明中，所述第2金属膜由以银为主要成分的材料形成。
本发明所涉及的电子元器件的特征在于，在上述发明中，所述第1金属膜是镀敷膜或蒸镀膜。
本发明所涉及的电子元器件的特征在于，在上述发明中，所述第2金属膜是镀敷膜或蒸镀膜。
本发明所涉及的电子元器件的特征在于，在上述发明中，所述接合层是在200℃以上350℃以下的温度下进行加热，并在0.25MPa以上30MPa以下的压力下进行加压而形成的烧结体。
本发明所涉及的电子元器件的特征在于，在上述发明中，所述第2金属膜内不包含会降低所述接合层与所述第2金属膜的接合强度的镍的析出物。
此外，为解决上述问题，达到本发明的目的，本发明所涉及的电子元器件的制造方法具有下述特征。首先，在设置于半导体晶片的表面的导电部的表面，形成由以铜为主要成分的材料形成的第1金属膜。其次，在所述第1金属膜的表面，利用以与所述第1金属膜相比离子化倾向较小的金属为主要成分的材料形成第2金属膜。然后，在所述第2金属膜的表面，涂布含有银粒子的导电性材料。最后，通过热处理对所述导电性材料进行烧结。
此外，本发明所涉及的电子元器件的制造方法的特征在于，在上述发明中，所述导电部是在由硅或碳化硅形成的所述半导体晶片的表面，利用至少以铜或铝为主要成分的材料形成得到的。
本发明所涉及的电子元器件的制造方法的特征在于，在上述发明中，所述第2金属膜由以银为主要成分的材料形成。
本发明所涉及的电子元器件的制造方法的特征在于，在上述发明中，所述第1金属膜通过镀敷法、溅射法或蒸镀法来形成。
本发明所涉及的电子元器件的制造方法的特征在于，在上述发明中，所述第2金属膜通过镀敷法、溅射法或蒸镀法来形成。
本发明所涉及的电子元器件的制造方法的特征在于，在上述发明中，在所述热处理中，通过在200℃以上350℃以下的温度下进行加热，并在0.25MPa以上30MPa以下的压力下进行加压，由此来对所述导电性材料进行烧结。
本发明所涉及的电子元器件的制造方法的特征在于，在上述发明中，在所述热处理中，使所述导电性材料的烧结体即接合层与所述第2金属膜的接合强度下降的镍不会在所述第2金属膜内析出。
根据上述发明，通过在导电部的表面对以铜(Cu)为主要成分的第1金属膜进行成膜，能够在导电部的最表面形成与含有银粒子的接合层(以下，设为Ag接合层)的密接性较高的第2金属膜。因此，在将导电部的最表面的第2金属膜与用于电连接导电部与其他构件的金属板相接合时，能够使用Ag接合层。由此，与使用焊料接合层来进行第2金属膜与金属板的接合的情况相比，能够提高接合强度。此外，与使用焊料来接合导电部与金属板的情况相比，能够提高耐热性。
此外，根据上述发明，通过在导电部表面对以Cu为主要成分的第1金属膜进行成膜，在第2金属膜内不会析出会导致与Ag接合层的接合强度降低的Ni粒子。因此，能够防止导电部与Ag接合层之间的接合强度的下降，从而能够使导电部与金属板经由Ag接合层牢固地接合。
此外，根据上述发明，通过在导电部的最表面对以Ag为主要成分的第2金属膜进行成膜，例如即使在第1金属膜包含有Ni的情况下，也能够抑制在第2金属膜的Ag接合层侧的表面层析出Ni粒子。由此，能够防止导电部与第1Ag接合层之间的接合强度下降。
此外，根据上述发明，通过使用Ag接合层来接合各构件，能够制作(制造)具备以下特性的电子元器件，即：Ag接合层所具有的高熔点(约960℃左右)、热导率(100W/m·K以上300W/m·K以下)、以及电阻(1μΩcm以上3μΩcm以下)。此外，根据上述发明，由于利用以热传导率高于Ni的Cu为主要成分的材料来形成第1金属膜，与利用以Ni为主要成分的材料来形成第1金属膜的情况相比，能够得到较高的散热性。
发明效果
根据本发明所涉及的电子元器件和电子元器件的制造方法，获得能够提供接合强度较高的电子元器件的效果。此外，根据本发明所涉及的电子元器件和电子元器件的制造方法，获得能够提供耐热性较高的电子元器件的效果。此外，根据本发明所涉及的电子元器件和电子元器件的制造方法，获得能够提供散热性较高的电子元器件的效果。
附图说明
图1是放大实施方式所涉及的电子元器件的主要部分来表示的剖视图。
图2是表示实施方式所涉及的电子元器件的剖视图。
图3是表示实施方式所涉及的电子元器件的制造方法的流程图。
图4是表示银粒子材料和各金属单体之间的接合强度的特性图。
图5是表示实施方式所涉及的电子元器件的主要部分的接合强度的特性图。
图6是对与图5相对应的电子元器件的主要部分的接合强度数值化后得到的图表。
图7是表示构成实施方式所涉及的电子元器件的金属膜的含有成分和其含有率的特性图。
图8是对与图7相对应的金属膜的含有成分和其含有率数值化后得到的图表。
图9是表示实施方式所涉及的电子元器件的接合强度的特性图。
图10是对与图9相对应的电子元器件的接合强度数值化后得到的图表。
图11是表示现有封装结构的半导体装置的主要部分的剖视图。
图12是表示现有封装结构的半导体装置的另一个示例的主要部分的剖视图。
具体实施方式
下面参照附图，对本发明所涉及的电子元器件和电子元器件的制造方法的优选实施方式进行详细说明。此外，在以下的实施方式的说明及附图中，对相同结构标注同一标记，并省略重复说明。
(实施方式)
说明实施方式所涉及的电子元器件的结构。图1是放大实施方式所涉及的电子元器件的主要部分来表示的剖视图。图2是表示实施方式所涉及的电子元器件的剖视图。图1示出了图2的半导体芯片20与金属板5的接合部附近。图1、图2所示的实施方式所涉及的电子元器件10是安装有半导体芯片20的封装结构的半导体装置。半导体芯片20例如由硅(Si)、碳化硅(SiC)等来形成。图1中省略了对半导体芯片20的半导体硅部分的图示。
半导体芯片20构成半导体元件，在半导体芯片20的正面设置有构成半导体元件的正面电极等的导电部1。导电部1由例如铜(Cu)、铝(Al)或它们的合金来形成。具体而言，导电部1由例如铝－硅(Al-Si)合金或铝－硅－铜(Al-Si-Cu)合金来形成。通过使导电部1中包含Si来抑制铝尖峰形成(aluminum spiking)，通过使导电部1中包含Cu来抑制电迁移(electro-migration)。
导电部1的表面依次成膜(形成)有第1金属膜2和第2金属膜3。关于第1金属膜2和第2金属膜3将在后文中阐述。第2金属膜3的表面经由含有第1银(Ag)粒子的接合层(以下，设为第1Ag接合层)4与金属板5的一端相接合。金属板5的另一端经由含有第2Ag粒子的接合层(以下，设为第2Ag接合层)21与绝缘基板23的正面的电路图案24相接合。为了提高与第1、第2Ag接合层4、21的接合强度，在金属板5的最表面成膜例如金(Au)或银(Ag)膜。
半导体芯片20的背面设置有未图示的背面电极。在背面电极的最表面，利用例如溅射处理来对金膜或银膜进行成膜。半导体芯片20的背面电极经由含有第3Ag粒子的接合层(以下，设为第3Ag接合层)22与绝缘基板23的正面的电路图案24相接合。在电路图案24的最表面成膜用于提高与第2、第3Ag接合层21、22的接合强度的例如Au膜或Ag膜。
第1～3Ag接合层4、21、22是含有Ag粒子的导电性组合物(导电性材料)的烧结体。通过利用第1～3Ag接合层4、21、22来接合各构件，与利用焊料来接合各构件的情况相比，能够提高耐热性。具体而言，通过利用第1～3Ag接合层4、21、22来接合各构件，能够提供电子元器件10，该电子元器件10能够耐受在高温度环境下的动作(例如175℃下的连续动作等)。
绝缘基板23例如可以是在陶瓷材料的表面和背面直接接合铜后得到的DCB基板。绝缘基板23的背面与例如由铜构成的金属板(Cu板)25的正面相接合。Cu板25的背面与基底构件26的正面相接合。基底构件26由热传导率较高的材料形成。Cu板25与基底构件26的接合可以是利用焊料接合层来进行的接合，也可以是利用含有Ag粒子的接合层(Ag接合层)来进行的接合。
在Cu板25与基底构件26经由Ag接合层相接合的情况下，在Cu板25的最表面对用于提高与Ag接合层的接合强度的例如Au膜或Ag膜进行成膜。绝缘基板23的正面(半导体芯片20侧的面)被与绝缘基板23的周缘相接合的树脂壳体(未图示)覆盖。半导体芯片20的正面电极和背面电极分别通过外部电极用端子(未图示)引出至树脂壳体的外侧。树脂壳体的内部填充有树脂、凝胶等密封材料(未图示)。
接着，对第1金属膜2和第2金属膜3进行详细说明。为了在导电部1的最表面对第2金属膜3进行成膜，在对第2金属膜3进行成膜之前，在导电部1的表面对第1金属膜2进行成膜。第1金属膜2与导电部1的接合强度较高，且由表面容易对第2金属膜3进行成膜的材料来构成。具体而言，第1金属膜2由例如以铜(Cu)为主要成分的材料来形成。其理由是，能够提高经由第1Ag接合层4而接合的第2金属膜3与金属板5之间的接合强度。
并且，第1金属膜2优选由不含镍(Ni)的材料来形成。其理由如下所述。为了利用第1～3Ag接合层4、21、22来接合各构件彼此，需要在250℃左右的温度下进行高温热处理。在第1金属膜2含有镍的情况下，第2金属膜3内的第1Ag接合层4侧的表面层会因该热处理而析出镍粒子。第2金属膜3与金属板5之间的接合强度会因该镍的析出物而降低。第1金属膜2例如通过电解镀敷法、无电解镀敷法、溅射法(物理蒸镀法)或化学蒸镀法来形成。
为提高与第1Ag接合层4的接合强度，在半导体芯片20的最表面形成有第2金属膜3。第2金属膜3与第1Ag接合层4的接合性较高，由与第1金属膜2相比离子化倾向较小的材料来形成。具体而言，第2金属膜3由例如以银或金为主要成分的材料来形成。优选为第2金属膜3由以银为主要成分的材料来形成。其理由是，与第2金属膜3的主要成分为金的情况相比，能够抑制向第2金属膜3内析出镍。第2金属膜3例如通过电解镀敷法、无电解镀敷法、溅射法(物理蒸镀法)或化学蒸镀法来形成。
接着，说明图2所示的电子元器件10的制造方法。图3是表示实施方式所涉及的电子元器件的制造方法的流程图。以例如通过无电解镀敷处理来形成第1金属膜2和第2金属膜3的情况为例来进行说明。首先，通过例如溅射法，在半导体晶片的正面形成铝硅电极来作为导电部1。接着，以所需要的芯片尺寸来切割半导体晶片，从而制作半导体芯片20。接着，在进行成膜第1、第2金属膜2、3的镀敷处理(步骤S6，S7)之前，对半导体芯片20进行镀敷预处理(步骤S1～S5)。
具体而言，在镀敷预处理中，首先，对半导体芯片20进行脱脂处理(步骤S1)。接着，通过蚀刻，来去除附着于半导体芯片20表面的颗粒或有机物、氧化膜(步骤S2)。也可以在步骤S2的处理之后，使用例如硝酸来对半导体芯片20进行酸洗清洁，通过步骤S2的处理来去除半导体芯片20表面所生成的不溶性的蚀刻残渣。接着，进行浸锌(锌置换)处理(第1浸锌处理)，以提高半导体芯片20的正面的与后续工序中成膜的第1金属膜2的密接性(步骤S3)。
接着，使用例如硝酸对半导体芯片20进行酸洗清洁，去除步骤S3中在半导体芯片20的表面所形成的置换锌层(硝酸剥离、步骤S4)。接着，再次进行浸锌处理(第2浸锌处理)，以提高半导体芯片20的正面的与第2金属膜2之间的密接性，然后结束镀敷预处理(步骤S5)。在上述步骤S1～S5的各处理之间，分别进行对导电部1的表面进行水洗的处理。
接着，进行对第1金属膜2和第2金属膜3进行成膜的镀敷处理(步骤S6，S7)。具体而言，例如进行无电解Cu镀敷处理，在导电部1的表面对第1金属膜2进行成膜(步骤S6)。接着，在对半导体芯片20进行水洗之后，进行例如无电解Ag镀敷处理，在第1金属膜2的表面对第2金属膜3进行成膜(步骤S7)。
然后，将半导体芯片20安装到绝缘基板23。具体而言，在绝缘基板23的电路图案24的表面按照所希望的图案涂布成为第3Ag接合层22的含有Ag粒子的糊状导电性组合物(步骤S8)。接着，在以半导体芯片20的背面朝下(绝缘基板23侧)的方式将半导体芯片20放置于含有Ag粒子的糊状导电性组合物的表面之后，在进行加热的同时进行加压，从而对包含Ag粒子的导电性组合物进行烧结。由此，半导体芯片20经由第3Ag接合层22与绝缘基板23的电路图案24的表面相接合(步骤S9)。
然后，在半导体芯片20最表面的第2金属膜3的表面按照所希望的图案涂布成为第1Ag接合层4的含有Ag粒子的糊状导电性组合物(步骤S10)。此时，在绝缘基板23的电路图案24的表面也按照所希望的图案涂布成为第2Ag接合层21的含有Ag粒子的糊状导电性组合物。接着，在将金属板5放置于含有Ag粒子的糊状导电性组合物的表面之后，在进行加热的同时进行加压，由此对含有Ag粒子的导电性组合物进行烧结。由此，金属板5的一端经由第1Ag接合层4与半导体芯片20最表面的第2金属膜3的表面相接合(步骤S11)。此外，金属板5的另一端经由第2Ag接合层21与绝缘基板23的电路图案24的表面相接合。通过以上工序完成电子元器件10的制作。
用于烧结包含Ag粒子的导电性组合物的热处理优选为在例如200℃以上350℃以下的温度下进行加热，同时在例如0.25MPa以上30MPa以下的压力下进行加压。由此，含有Ag粒子的糊状导电性组合物烧结，从而能够形成具有较高的接合强度及优异的耐热性和散热性的第1Ag接合层4。
如上述所说明的那样，根据实施方式，通过在导电部(半导体元件的正面电极)的表面对以Cu为主要成分的第1金属膜进行成膜，能够在导电部的最表面形成与第1Ag接合层的密接性较高的第2金属膜。因此，在将导电部的最表面的第2金属膜与用于电连接导电部与其他构件的金属板相接合时，能够使用第1Ag接合层。由此，与使用焊料接合层来接合第2金属膜与金属板的情况相比，能够提高接合强度。此外，与使用焊料来接合导电部与金属板的情况相比，能够提高耐热性以达到能够耐受例如在高温度环境下的动作(例如175℃下的连续动作等)的程度。
此外，根据实施方式，通过在导电部表面对以Cu为主要成分的第1金属膜进行成膜，在第2金属膜内不会析出会导致与第1Ag接合层的接合强度下降的Ni粒子。由此，能够防止导电部与第1Ag接合层之间的接合强度下降。因而，能够使导电部与金属板经由第1Ag接合层牢固地接合。因此，利用P/C(功率循环)试验等所评价的可靠性得以提高。具体而言，对于利用第1Ag接合层来进行接合的电子元器件，在P/C试验中例如在第1Ag接合层上出现裂纹，从产生该裂纹的部分开始剥离直至损坏。因此，通过提高导电部与第1Ag接合层之间的接合强度，第1Ag接合层中不易产生裂纹，因而电子元器件的寿命得以提高。
此外，根据实施方式1，通过在导电部的最表面对以Ag为主要成分的第2金属膜进行成膜，例如即使在第1金属膜、第2金属膜包含有Ni的情况下，也能够抑制在第2金属膜的第1Ag接合层侧的表面层析出Ni粒子。由此，能够防止导电部与第1Ag接合层之间的接合强度下降。
此外，根据实施方式，通过使用第1～3Ag接合层来接合各构件，能够制作(制造)具备以下特性的电子元器件，即：第1～3的Ag接合层所具有的高熔点(约960℃左右)、热导率(100W/m·K以上300W/m·K以下)、以及电阻(1μΩcm以上3μΩcm以下)。由此，能够制作耐热性较高、散热性较高的电子元器件。此外，根据实施方式，由于利用以热传导率高于Ni的Cu为主要成分的材料来形成第1金属膜，与利用以Ni为主要成分的材料来形成第1金属膜的情况相比，能够得到较高的散热性。
(实施例1)
接着，对含有Ag粒子的接合层(Ag接合层)的接合强度进行验证。图4是表示银粒子材料和各金属单体之间的接合强度的特性图。首先，在硅晶片的表面形成金属层之后，制作切割成芯片尺寸为10mm×10mm的半导体芯片。接着，在半导体芯片的金属层上涂布含有Ag粒子的糊状导电性组合物(Ag粒子材料)。然后，在250℃的温度下加热5分钟，并进行加压，由此来烧结导电性组合物，从而在金属层上形成Ag接合层。对加热导电性组合物时的加压量进行各种变更，从而制作得到多个试料，并进行剪切强度试验，利用剪切力来评价各试料中金属层与Ag接合层之间的接合强度。
对硅晶片表面的金属层分别由Ag、Au、Cu、及Ni单体形成的各试料进行上述剪切强度试验。各金属层与Ag接合层的接合强度的剪切强度试验结果在图4中示出。根据图4所示的结果，对各金属，均可确认加压量越高则与Ag接合层的接合强度越高。此外，可确认与Ag接合层之间的接合强度因金属种类的不同而不同。具体而言，对于与Ag接合层的接合强度，Ag最大，然后按照Au、Cu及Ni的顺序依次减小。由此，可确认与Ni相比，Cu与Ag接合层的接合强度较大。
(实施例2)
接着，对半导体芯片20表面的导电部1与金属板5的接合强度进行验证。图5是表示关于实施方式所涉及的电子元器件的主要部分的接合强度的特性图。图6是将与图5相对应的电子元器件的主要部分的接合强度数值化后得到的图表。首先，按照实施方式，以5μm的厚度成膜得到Cu镀膜来作为第1金属膜2，并以0.1μm的厚度成膜得到Ag镀膜来作为第2金属膜3，然后经由第1Ag接合层4来接合金属板5，由此制作得到半导体芯片20(以下，设为实施例2)。
具体而言，按下述方式制作实施例2。首先，在6英寸的硅晶片的一个主面通过溅射法以5μm的厚度形成成为导电部1的铝硅(AlSi)电极，然后切割出芯片尺寸为10mm×10mm来作为半导体芯片20。接着，在进行镀敷预处理之后，通过无电解Cu镀敷处理，在导电部1上以5μm的厚度成膜得到Cu镀膜来作为第1金属膜2。接着，通过无电解Ag镀敷处理，在第1金属膜2上以0.1μm的厚度成膜得到Ag镀膜来作为第2金属膜3。
接着，在第2金属膜3上涂布含有Ag粒子的糊状导电性组合物(Ag粒子材料)。此时，使用具有以8mm×8mm进行开口得到的开口部、且厚度为100μm的金属掩模在第2金属膜3表面的与金属掩模的开口部面积相同的区域涂布导电性组合物。然后，在将实施了Ag镀敷的金属板5放置于Ag粒子材料上之后，在250℃的温度下加热5分钟并进行加压，由此来烧结导电性组合物，从而在第2金属膜3上形成第1Ag接合层4。由此，完成导电部1与金属板5经由第1Ag接合层4相接合的实施例2(第1金属膜2/第2金属膜3＝Cu/Ag)。
作为比较，制作第1、2的金属膜2、3的结构与实施例2不同的比较例1、2。比较例1中，以5μm的厚度成膜得到Ni镀膜来作为第1金属膜，以0.05μm的厚度成膜得到Au镀膜来作为第2金属膜(第1金属膜/第2金属膜＝Ni/Au)。比较例2中，以5μm的厚度成膜得到Ni镀膜来作为第1金属膜，以0.1μm的厚度成膜得到Ag镀膜来作为第2金属膜(第1金属膜/第2金属膜＝Ni/Ag)。比较例1、2中除第1、2的金属膜以外的结构与实施例2相同。除通过镀敷处理成膜得到的镀膜的材料和厚度以外，比较例1、2的制造方法与实施例2的制造方法相同。
在上述实施例2和比较例1、2中，对加热导电性组合物时的加压量进行各种变更，从而分别制作多个试料，并进行剪切强度试验，剪切强度试验的结果在图5、6中示出。剪切强度试验是利用剪切力来评价导电部1与金属板5之间的接合强度的强度试验。
根据图5、6所示的结果，可确认实施例2和比较例2中的接合强度要高于比较例1。具体而言，例如，在以10MPa的加压量对第1Ag接合层4进行烧结的情况下，对于导电部1与金属板5之间的接合强度，实施例2和比较例2中分别为60.1MPa和58.8MPa，而比较例1中为42.5MPa。即，可确认对于导电部1与金属板5之间的接合强度，将第2金属膜设为Ag镀膜的实施例2和比较例2大致相等，且比将第2金属膜设为Au镀膜的比较例1要高。
因此，可确认构成半导体元件的正面电极(导电部1)的最表面的第2金属膜3的金属对导电部1与金属板5之间的接合强度有较大影响。此外，可确认通过形成以Ag为主要成分的第2金属膜3，能够提高导电部1与金属板5之间的接合强度。此外，可确认越是增大烧结第1Ag接合层4时的加压量，越能够提高导电部1与金属板5之间的接合强度。加压量0MPa是指未加压的情况。
(实施例3)
接着，验证电子元器件10的接合强度。具体而言，对于制作作为产品的电子元器件10，按实施方式所示的那样，在将金属板5与半导体芯片20表面的导电部1相接合之前，将半导体芯片20与绝缘基板23的电路图案24相接合。因此，对将半导体芯片20与绝缘基板23的电路图案24相接合的工序对半导体芯片20表面的导电部1与金属板5之间的接合强度带来的影响进行验证。首先，测定向第2金属膜3内析出Ni的Ni析出量。
图7是表示构成实施方式所涉及的电子元器件的金属膜的含有成分和其含有率的特性图。图8是将与图7相对应的金属膜的含有成分和其含有率数值化后得到的图表。图7、图8中，加热前是表示未进行将半导体芯片20与绝缘基板23的电路图案24相接合的工序。即，加热前是指实施例2和比较例1、2。加热后是表示进行了将半导体芯片20与绝缘基板23的电路图案24相接合的工序，并制作得到实施方式所涉及的电子元器件(以下，设为实施例3)的情况(对于图9、图10也同样)。实施例3的除绝缘基板23和第3Ag接合层22以外的结构与实施例2相同。
具体而言，按下述方式制作实施例3。首先，与实施例2相同，准备形成有AlSi电极来作为导电部1的半导体芯片20，在导电部1上依次成膜得到Cu镀膜和Ag镀膜来作为第1、第2金属膜2、3。接着，在绝缘基板23的电路图案24上涂布含有Ag粒子的糊状导电性组合物(Ag粒子材料)。此时，使用具有开口大于芯片尺寸的开口部的金属掩模，在绝缘基板23的电路图案24表面的与金属掩模的开口部面积相同的区域涂布导电性组合物。
接着，以半导体芯片20的背面朝向绝缘基板23侧的方式将半导体芯片20放置在Ag粒子材料上，并在250℃的温度下加热5分钟，并以10MPa的压力进行加压，由此来烧结导电性组合物，从而在绝缘基板23的电路图案24上形成第3Ag接合层22。由此，半导体芯片20经由第3Ag接合层22接合在绝缘基板23的电路图案24上。接着，与实施例2同样地，在半导体芯片20的第2金属膜3上形成第1Ag接合层4，通过使导电部1与金属板5经由第1Ag接合层4相接合，来完成实施例3。实施例3中，用于烧结第1Ag接合层4的高温热处理中的加压量为10MPa。
作为加热后的比较，制作第1、2的金属膜2、3的结构与实施例3不同的比较例3、4。比较例3中除绝缘基板和第3Ag接合层以外的结构与比较例1相同。比较例4中除绝缘基板和第3Ag接合层以外的结构与比较例2相同。在上述实施例3和比较例3、4中，分别对第2金属膜内的Ni析出量进行测定，其结果在图7、8中示出。图7、8中，示出第2金属膜的第1Ag接合层侧的表面层的任意的多个部位中各含有成分的平均含有率(％)。
如图7、图8所示，可确认在设有Cu镀膜来作为第1金属膜2的实施例中，加热前(实施例2)和加热后(实施例3)中在第2金属膜3内均未析出Ni。另一方面，可确认在设有Ni镀膜来作为第1金属膜的比较例中，加热前(比较例1、2)和加热后(比较例3、4)中在第2金属膜3内均析出Ni。此外，可确认在设有Ni镀膜来作为第1金属膜的比较例中，与加热前(比较例1、2)相比，加热后(比较例3、4)中Ni含有率增大。
具体而言，在设有Au镀膜来作为第2金属膜的情况下，可确认第2金属膜的Ni含有率在加热前(比较例1)为1.8％，而在加热后(比较例3)变为13.8％。在设有Ag镀膜来作为第2金属膜的情况下，可确认第2金属膜的Ni含有率在加热前(比较例2)为0.9％，而在加热后(比较例4)变为2.8％。因此，可确认与设有Ag镀膜来作为第2金属膜的情况相比，设有Au镀膜来作为第2金属膜的情况下，Ni的析出较多。
接着，对第2金属膜3的Ni含有率与电子元器件10的接合强度之间的关系进行验证。图9是表示实施方式所涉及的电子元器件的接合强度的特性图。图10是将与图9相对应的电子元器件的接合强度数值化后得到的图表。测定实施例3和比较例3、4的接合强度得到的结果在图9、图10中示出。图9、图10中，实施例2和比较例1、2的接合强度是图5、图6所示的加压量为10MPa的情况下的接合强度。
根据图9、图10所示的结果，可确认在Ni含有率最多的比较例1、3(第1金属膜/第2金属膜＝Ni/Au)中，接合强度从42.5MPa大幅下降至6.6MPa(图9中用较细的虚线箭头示出)。此外，可确认即使在与比较例1、3相比Ni含有率较少的比较例2、4(第1金属膜/第2金属膜＝Ni/Ag)中，接合强度也从58.8MPa下降至39.8MPa(图9中用较粗的虚线箭头示出)。另一方面，可确认在未析出Ni的实施例2、3(第1金属膜2/第2金属膜3＝Cu/Ag)中，加热前和加热后的接合强度分别为60.1MPa和59.5MPa，几乎没有下降(图9中用实线箭头示出)。
因此，根据图7～图10所示出的结果，可确认通过形成以Cu为主要成分的第1金属膜2，即使在加热前和加热后，均能抑制电子元器件10的接合强度下降。并且，可确认通过形成以Cu为主要成分的第1金属膜2，与形成以Ni为主要成分的第1金属膜2的情况相比，能够提高第2金属膜3与第1Ag接合层4之间的密接性。此外，可确认通过形成以Ag为主要成分的第2金属膜3，在第2金属膜3内析出Ni的情况下，能够抑制加热后Ni的析出。
在上述本发明中，以半导体元件的正面电极与金属板相接合的情况为例进行了说明，但并不限于此，对于其他导电部与用于电连接该导电部与其他构件的金属板相接合的情况，也能够应用本发明。
工业上的实用性
如上所述，本发明所涉及的电子元器件和电子元器件的制造方法适用于具有通过接合各构件来进行电连接的结构的电子元器件等封装结构的半导体装置。
标号说明
1  导电部
2  第1金属膜(Cu镀膜)
3  第2金属膜(Ag镀膜)
4  含有Ag粒子的接合层
5  金属板
10  电子元器件
20  半导体芯片

Claims (14)

1.一种电子元器件，其特征在于，包括：
设置于半导体元件的表面的导电部；
设置于所述导电部的表面，且由以铜为主要成分的材料形成的第1金属膜；
设置于所述第1金属膜的表面，且由以与所述第1金属膜相比离子化倾向较小的金属为主要成分的材料形成的第2金属膜；以及
设置于所述第2金属膜的表面，且含有银粒子的接合层。
2.如权利要求1所述的电子元器件，其特征在于，
所述半导体元件由硅或碳化硅形成，
所述导电部由至少以铜或铝为主要成分的材料形成。
3.如权利要求1所述的电子元器件，其特征在于，
所述第2金属膜由以银为主要成分的材料形成。
4.如权利要求1所述的电子元器件，其特征在于，
所述第1金属膜是镀敷膜或蒸镀膜。
5.如权利要求1所述的电子元器件，其特征在于，
所述第2金属膜是镀敷膜或蒸镀膜。
6.如权利要求1所述的电子元器件，其特征在于，
所述接合层是在200℃以上350℃以下的温度下进行加热，并在0.25MPa以上30MPa以下的压力下进行加压而形成的烧结体。
7.如权利要求1至6的任一项所述的电子元器件，其特征在于，
所述第2金属膜内不包含会降低所述接合层与所述第2金属膜的接合强度的镍的析出物。
8.一种电子元器件的制造方法，其特征在于，包括：
在设置于半导体晶片的表面的导电部的表面，形成由以铜为主要成分的材料形成的第1金属膜的工序；
在所述第1金属膜的表面，利用以与所述第1金属膜相比离子化倾向较小的金属为主要成分的材料形成第2金属膜的工序；
在所述第2金属膜的表面，涂布含有银粒子的导电性材料的工序；以及
通过热处理对所述导电性材料进行烧结的工序。
9.如权利要求8所述的电子元器件的制造方法，其特征在于，
所述导电部是在由硅或碳化硅形成的所述半导体晶片的表面，利用至少以铜或铝为主要成分的材料形成得到的。
10.如权利要求8所述的电子元器件的制造方法，其特征在于，
所述第2金属膜由以银为主要成分的材料形成。
11.如权利要求8所述的电子元器件的制造方法，其特征在于，
所述第1金属膜通过镀敷法、溅射法或蒸镀法来形成。
12.如权利要求8所述的电子元器件的制造方法，其特征在于，
所述第2金属膜通过镀敷法、溅射法或蒸镀法来形成。
13.如权利要求8所述的电子元器件的制造方法，其特征在于，
在所述热处理中，通过在200℃以上350℃以下的温度下进行加热，并在0.25MPa以上30MPa以下的压力下进行加压，由此来对所述导电性材料进行烧结。
14.如权利要求8至13的任一项所述的电子元器件的制造方法，其特征在于，
在所述热处理中，使所述导电性材料的烧结体即接合层与所述第2金属膜的接合强度下降的镍不会在所述第2金属膜内析出。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107431019A (zh) * 2014-12-17 2017-12-01 爱法组装材料公司 芯片和芯片夹的安装方法
CN112823411A (zh) * 2018-09-28 2021-05-18 株式会社村田制作所 连接电极及连接电极的制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112014002061T5 (de) * 2013-10-29 2016-01-07 Fuji Electric Co., Ltd. Halbleitermodul
JP6630053B2 (ja) * 2015-03-25 2020-01-15 スタンレー電気株式会社 電子デバイスの製造方法
JP6491032B2 (ja) 2015-04-24 2019-03-27 スタンレー電気株式会社 抵抗器の製造方法、および、抵抗器
FR3038535B1 (fr) * 2015-07-10 2017-08-11 Commissariat Energie Atomique Assemblage comprenant deux elements de coefficient de dilatation thermique differents et un joint fritte heterogene en densite et procede de fabrication de l'assemblage
JP7062929B2 (ja) * 2017-11-30 2022-05-09 凸版印刷株式会社 タッチパネル
US10910340B1 (en) * 2019-10-14 2021-02-02 Heraeus Deutschland GmbH & Co. KG Silver sintering preparation and the use thereof for the connecting of electronic components
JP2021007182A (ja) * 2020-10-19 2021-01-21 三菱電機株式会社 半導体装置及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1620220A (zh) * 2000-02-09 2005-05-25 松下电器产业株式会社 复制材料及其制造方法以及用其制造的布线基片
CN1819172A (zh) * 2005-01-20 2006-08-16 日产自动车株式会社 半导体装置及其制造方法
US20120068321A1 (en) * 2010-09-17 2012-03-22 On Semiconductor Trading, Ltd. Semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07263493A (ja) 1994-03-18 1995-10-13 World Metal:Kk チップマウント方法
JP3484367B2 (ja) 1999-01-29 2004-01-06 三菱電機株式会社 無電解めっき方法およびその前処理方法
JP4096671B2 (ja) 2002-09-19 2008-06-04 株式会社村田製作所 電子部品のめっき方法、及び電子部品
JP4048427B2 (ja) 2002-09-30 2008-02-20 株式会社村田製作所 電子部品の製造方法、及び電子部品
JP4412072B2 (ja) 2003-10-09 2010-02-10 株式会社日立製作所 電子部品の実装方法，半導体モジュール及び半導体装置
US7393771B2 (en) 2004-06-29 2008-07-01 Hitachi, Ltd. Method for mounting an electronic part on a substrate using a liquid containing metal particles
JP4650784B2 (ja) 2004-11-05 2011-03-16 株式会社村田製作所 電子部品、及びめっき方法
JP2007180059A (ja) 2005-12-26 2007-07-12 Toshiba Corp 光半導体装置とその製造方法
JP4737116B2 (ja) 2007-02-28 2011-07-27 株式会社日立製作所 接合方法
JP2010050189A (ja) * 2008-08-20 2010-03-04 Hitachi Metals Ltd 接合材、半導体装置およびその製造方法
WO2012121355A1 (ja) * 2011-03-10 2012-09-13 富士電機株式会社 電子部品および電子部品の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1620220A (zh) * 2000-02-09 2005-05-25 松下电器产业株式会社 复制材料及其制造方法以及用其制造的布线基片
CN1819172A (zh) * 2005-01-20 2006-08-16 日产自动车株式会社 半导体装置及其制造方法
US20120068321A1 (en) * 2010-09-17 2012-03-22 On Semiconductor Trading, Ltd. Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107431019A (zh) * 2014-12-17 2017-12-01 爱法组装材料公司 芯片和芯片夹的安装方法
CN107431019B (zh) * 2014-12-17 2021-10-08 爱法组装材料公司 芯片和芯片夹的安装方法
CN112823411A (zh) * 2018-09-28 2021-05-18 株式会社村田制作所 连接电极及连接电极的制造方法
CN112823411B (zh) * 2018-09-28 2024-05-28 株式会社村田制作所 连接电极及连接电极的制造方法

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