JP5449145B2 - 接合方法及び接合装置 - Google Patents
接合方法及び接合装置 Download PDFInfo
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- JP5449145B2 JP5449145B2 JP2010510161A JP2010510161A JP5449145B2 JP 5449145 B2 JP5449145 B2 JP 5449145B2 JP 2010510161 A JP2010510161 A JP 2010510161A JP 2010510161 A JP2010510161 A JP 2010510161A JP 5449145 B2 JP5449145 B2 JP 5449145B2
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- H—ELECTRICITY
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1163—Chemical reaction, e.g. heating solder by exothermic reaction
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
Log(t)≦3(1000/T−2)
図6に示すように2段階以上の加熱カーブで加熱される場合は、曝露時間と加熱温度時間とは、以下の条件を満足することが望ましい。
Σ(log(tn)/{3(1000/Tn−2)}≦1
tn、Tn:n段目の時間、温度
さて、上記した構成の酸化膜除去装置10を用いて、外部引出電極5,8や突起電極6の表面を覆っている酸化膜の除去を行う。
次に、半導体チップ2および中間基板3を大気中に取り出した後(ステップS5)、フリップチップ接合機で両者の接合をおこなう(ステップS6)。その際、加圧前の接合されるべき面が曝される環境は温度、時間を以下の条件とする。
Log(t)≦3(1000/T−2) (1)
t;曝露時間(min)
T;加熱温度(K)
また、酸化膜還元処理を実施することにより、上記の酸化膜が急激に増加する加熱時間前であれば、酸化膜はほとんど存在せず、大気中に加熱しても接合することができた。もし、酸化膜還元処理を実施していなければ、この加熱条件よりずっと低温、短時間で酸化膜が成長する。
Log(t)≦3(1000/T−3) (3)
t;曝露時間(min)
T;加熱温度(K)
この式(3)も、式(1)、(2)と同様な過程で導出した。
Claims (4)
- 表面に被接合物をそれぞれ有する第1及び第2基板の前記被接合物の表面に対して、酸化膜除去装置内において、水素ラジカルによる酸化膜還元処理のみを行う過程と、
前記酸化膜還元処理を行った前記被接合物の位置あわせを、大気中で行い、その後に前記第1及び第2基板に荷重を加えて記第1基板の被接合物と前記第2基板の被接合物とを、接合する過程とを、
具備する接合方法。 - 請求項1記載の接合方法において、前記荷重を加えての接合は、100〜200℃の温度で行い、前記第1及び第2の基板に加える荷重は1MPa〜6MPaである接合方法。
- 請求項2記載の接合方法において、前記接合の荷重を付加する前の前記被接合物の大気中に放置される時間t、温度Tは、以下に示す範囲内に留める接合方法。
Log(t)≦3(1000/T−2) - 表面に被接合物をそれぞれ有する第1及び第2基板の前記被接合物の表面に対して、水素ラジカルによる酸化膜還元処理のみを行う手段と、
前記酸化膜還元処理を行った前記被接合物の位置あわせを、大気中で行う手段と、
前記位置あわせ後に、前記第1及び第2基板に荷重を加えて前記第1基板の被接合物と前記第2基板の被接合物とを、接合する手段とを、
具備する接合装置。
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JP2011181631A (ja) * | 2010-02-26 | 2011-09-15 | Tokyo Electron Ltd | 表面活性化方法、プログラム、コンピュータ記憶媒体及び表面活性化装置 |
JP5183659B2 (ja) * | 2010-03-23 | 2013-04-17 | 東京エレクトロン株式会社 | 基板処理装置、基板処理方法、プログラム及びコンピュータ記憶媒体 |
JP5656144B2 (ja) * | 2010-03-26 | 2015-01-21 | 国立大学法人群馬大学 | 金属部材の接合方法 |
JP2012038790A (ja) * | 2010-08-04 | 2012-02-23 | Hitachi Ltd | 電子部材ならびに電子部品とその製造方法 |
JP5779931B2 (ja) * | 2011-03-24 | 2015-09-16 | 富士通株式会社 | 半導体装置の製造方法 |
JP6011074B2 (ja) * | 2012-01-20 | 2016-10-19 | 富士通株式会社 | 電子装置の製造方法及び電子装置の製造装置 |
DE112012005906A5 (de) * | 2012-05-30 | 2014-10-30 | Ev Group E. Thallner Gmbh | Vorrichtung und Verfahren zum Bonden von Substraten |
JP6132316B2 (ja) * | 2012-06-05 | 2017-05-24 | 国立大学法人群馬大学 | 金属部材の接合方法 |
US9446467B2 (en) | 2013-03-14 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrate rinse module in hybrid bonding platform |
US9779965B2 (en) * | 2013-10-08 | 2017-10-03 | Kulicke And Soffa Industries, Inc. | Systems and methods for bonding semiconductor elements |
US9780065B2 (en) | 2013-10-08 | 2017-10-03 | Kulicke And Soffa Industries, Inc. | Systems and methods for bonding semiconductor elements |
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