CN103855097A - Sram单元中的接触塞及其形成方法 - Google Patents

Sram单元中的接触塞及其形成方法 Download PDF

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CN103855097A
CN103855097A CN201310165080.1A CN201310165080A CN103855097A CN 103855097 A CN103855097 A CN 103855097A CN 201310165080 A CN201310165080 A CN 201310165080A CN 103855097 A CN103855097 A CN 103855097A
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廖忠志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括在SRAM单元的一部分上方形成介电层。该SRAM单元包括第一上拉晶体管和第二上拉晶体管、与第一上拉晶体管和第二上拉晶体管形成交叉锁存的反相器的第一下拉晶体管和第二下拉晶体管、以及分别连接至第一上拉晶体管和第一下拉晶体管的漏极和第二上拉晶体管和第二下拉晶体管的漏极的第一传输门晶体管和第二传输门晶体管。在介电层上方形成第一掩模层并对其进行图案化。在介电层上形成第二掩模层并对其进行图案化。将第一掩模层和第二掩模层结合起来用作蚀刻掩模来蚀刻介电层，其中，在介电层中形成接触件开口。在接触件开口中形成接触塞。本发明还提供了SRAM单元中的接触塞及其形成方法。

Description

SRAM单元中的接触塞及其形成方法
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件及其形成方法。
背景技术
在深微技术中，接触塞的尺寸持续缩小以适合不断减小的栅极间距。为了缩小接触尺寸而不影响接触电阻，与方形接触塞相比较，采用长接触塞。通过采用长接触塞，可以减小接触塞的宽度，沿着栅极间距方向测量该接触塞的宽度。长接触塞具有更大的长度，沿着栅极布线(栅极长度方向)方向测量该长度。通过使用长接触塞，增加了有源接触尺寸和光刻曝光面积。
长接触塞可以实现高栅极密度和低接触电阻。然而，仍存在问题。例如，在相邻的长接触塞的端部可能发生线端短路和/或线端与线端桥接。这些可能导致接触件与鳍主动开路(active opening)(也被称为接触件短路)或接触件-接触件漏电(由接触件桥接导致的)。为了减少线端短路的可能性，需要更多的限制性的空间规则来增大相邻的接触塞的端部之间的间隔，或者在线端处需要更积极的光学邻近校正(OPC)。然而，这些解决方案会影响集成电路的尺寸。因为3D MOSFET具有非常窄的有源区域，所以这个问题在未来的鳍式MOSFET(3D MOSFET)中变得更严重。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种方法，包括：在静态随机存取存储器(SRAM)单元的一部分上方形成介电层，所述SRAM单元包括：第一上拉晶体管和第二上拉晶体管；第一下拉晶体管和第二下拉晶体管，与所述第一上拉晶体管和所述第二上拉晶体管形成交叉锁存的反相器；和第一传输门晶体管和第二传输门晶体管，分别连接至所述第一上拉晶体管和所述第一下拉晶体管的漏极以及所述第二上拉晶体管和所述第二下拉晶体管的漏极；在所述介电层上方形成并图案化第一掩模层；在所述介电层上方形成第二掩模层；将所述第一掩模层和所述第二掩模层结合起来用作蚀刻掩模来蚀刻所述介电层，在所述介电层中形成接触开口；以及在所述接触开口中形成接触塞。
在该方法中，所述第一掩模层包含选自基本上由基于氧化硅的电介质、氮氧化硅、氮化硅、多晶硅、非晶硅、含碳介电材料、含氮介电材料、有机材料、难熔金属以及它们的组合所组成的组的材料。
在该方法中，所述第二掩模层包含光刻胶，并且所述第二掩模层位于所述第一掩模层上方。
在该方法中，在图案化所述第一掩模层的步骤之后，所述第一掩模层形成其中具有第一长接触开口的连续层，所述第一长接触开口的长度方向平行于所述SRAM单元的长边界，并且所述第一长接触开口的长度大于或者等于所述长边界的长度。
在该方法中，所述连续层中进一步包含第二长接触开口，所述第二长接触开口的长度方向平行于所述SRAM单元的长边界，并且所述第二长接触开口的长度小于所述长边界的长度。
在该方法中，所述第二长接触开口延伸到所述SRAM单元的边界。
在该方法中，所述第二长接触开口未延伸到所述SRAM单元的任何边界。
在该方法中，在图案化所述第一掩模层的步骤之后，所述第一掩模层形成彼此分离的岛状件。
在该方法中，在形成所述接触塞时，同时形成附加接触塞，所述接触塞位于所述第一下拉晶体管的漏极上方并与所述第一下拉晶体管的漏极连接，而所述附加接触塞位于所述第一上拉晶体管的漏极上方并与所述第一上拉晶体管的漏极连接，并且所述接触塞和所述附加接触塞彼此分离。
在该方法中，所述接触塞在所述第一下拉晶体管的漏极和所述第一上拉晶体管的漏极上方延伸并且互连所述第一下拉晶体管的漏极和所述第一上拉晶体管的漏极。
根据本发明的另一方面，提供了一种方法，包括：形成包括多个栅电极和多个有源区域带的静态随机存取存储器(SRAM)单元，所述多个有源区域带与所述多个栅电极形成晶体管；在所述多个栅电极和所述多个有源区域带上方形成层间电介质(ILD)；在所述ILD上方形成第一掩模层，所述第一硬掩模层覆盖所述ILD的第一部分，并且通过所述第一掩模层中的开口暴露所述ILD的第二部分；形成第二掩模层，所述第二掩模层包括填充到所述第一掩模层中的部分开口中的部分；使用所述第一掩模层和所述第二掩模层作为蚀刻掩模来蚀刻所述ILD以在所述ILD中形成多个接触开口；以及在所述多个接触开口中形成多个接触塞。
在该方法中，所述第一掩模层中的开口包括：第一开口，与所述SRAM单元的第一边界重叠并且具有与所述SRAM单元的第一边界平行的长度方向；以及第二开口，与所述SRAM单元的第二边界重叠并且具有与所述SRAM单元的第二边界平行的长度方向，其中，所述第一边界和所述第二边界彼此平行，并且所述第一开口和所述第二开口均从所述SRAM单元的第三边界延伸至所述SRAM单元的第四边界，所述第三边界和所述第四边界与所述第一边界和所述第二边界垂直。
在该方法中，所述第二掩模层包含长度方向与所述第一开口的长度方向垂直的带。
在该方法中，所述第一掩模层包含硬掩模材料，而所述第二掩模层包含光刻胶。
在该方法中，形成所述多个接触塞的步骤包括：形成位于所述SRAM单元的下拉晶体管的漏极上方且连接至所述下拉晶体管的漏极的第一接触塞；以及形成位于所述SRAM单元的上拉晶体管的漏极上方且连接至所述上拉晶体管的漏极的第二接触塞，其中，所述方法进一步包括形成位于所述第一接触塞和所述第二接触塞上方并且互连所述第一接触塞和所述第二接触塞的金属连接件。
在该方法中，形成所述多个接触塞的步骤包括形成在所述SRAM单元的下拉晶体管的漏极和所述SRAM单元的上拉晶体管的漏极上方连续延伸且互连所述下拉晶体管的漏极和所述上拉晶体管的漏极的接触塞。
根据本发明的又一方面，提供了一种在非易失性计算机可读介质上实现的静态随机存取存储器(SRAM)单元布局，所述SRAM单元布局包括：多个栅电极的多个第一布局图案；多个鳍线的多个第二布局图案，所述多个第一布局图案和所述多个第二布局图案是以下部件的一部分：交叉锁存的反相器，包含第一上拉晶体管和第二上拉晶体管以及第一下拉晶体管和第二下拉晶体管；和两个传输门晶体管，连接至所述交叉锁存的反相器；第一掩模层的多个第三布局图案；以及第二掩模层的多个第四布局图案，其中，所述多个第三布局图案与所述多个第四布局图案不重叠的部分包含所述SRAM单元的接触塞图案。
在该SRAM单元布局中，所述接触塞图案包括：第一接触塞图案，与所述多个第二布局图案的第一漏极图案对准，所述第一漏极图案是所述第一上拉晶体管的漏极区域的布局图案；以及第二接触塞图案，与所述多个第二布局图案的第二漏极图案对准，所述第二漏极图案是所述第一下拉晶体管的漏极区域的布局图案，并且所述第一接触塞图案与所述第二接触塞图案间隔开。
在该SRAM单元布局中，所述接触塞图案包括：从所述第一上拉晶体管的漏极区域连续延伸到所述第一下拉晶体管的漏极区域的长接触塞图案。
在该SRAM单元布局中，所述多个第三布局图案包含与所述SRAM单元的第一边界重叠并且具有平行于所述第一边界的长度方向的第一开口图案。
在该SRAM单元布局中，所述多个第三布局图案进一步包含与所述SRAM单元的第二边界重叠并且具有平行于所述第二边界的长度方向的第二开口图案，并且所述第一边界和所述第二边界彼此平行。
在该SRAM单元布局中，所述第一开口图案从所述SRAM单元的第三边界延伸到所述SRAM单元的第四边界，并且所述第三边界和所述第四边界与所述第一边界垂直。
在该SRAM单元布局中，所述多个第一布局图案中的一个布局图案的长度不短于所述SRAM单元的相应长度。
附图说明
为了更充分地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1A和图1B是根据示例性实施例的静态随机存取存储器(SRAM)单元的电路图；
图2示出了阐述SRAM单元的层的示意性截面图；
图3A至图10是根据各个实施例的形成SRAM单元的中间阶段的俯视图和截面图；
图11和图12是根据可选实施例的形成SRAM单元的中间阶段的俯视图；
图13示出了根据示例性实施例的SRAM单元，其中，SRAM单元中的一些晶体管是多鳍式FinFET；
图14至图16是根据又一些可选实施例的形成SRAM单元的中间阶段的俯视图；
图17是包含多鳍式FinFET的SRAM单元的俯视图；
图18A和图18B示出了SRAM单元的重复形式；以及
图19至图24是根据又一些可选实施例的形成SRAM单元的中间阶段的俯视图。
具体实施方式
在下面详细讨论本发明的实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅是示例性的而不用于限制本发明的范围。
根据多个示例性实施例提供了静态随机存取存储器(SRAM)单元。讨论了实施例的变型例。在各个视图和示例性实施例中，相同的参考标号用于指定相同的元件。虽然使用六晶体管(6T)SRAM单元作为实例来说明实施例的构思，但是实施例可以很容易地应用于具有不同数量的晶体管的其它SRAM单元，诸如8TSRAM单元。
图1A示出了根据一些实施例的SRAM单元10的电路图。SRAM单元10包括传输门晶体管PG-1和PG-2和上拉晶体管PU-1和PU-2(其是P型金属氧化物半导体(PMOS)晶体管)以及下拉晶体管PD-1和PD-2(其是N型金属氧化物半导体(NMOS)晶体管)。传输门晶体管PG-1和PG-2的栅极连接至确定是否选择SRAM单元10的字线WL。由上拉晶体管PU-1和PU-2以及下拉晶体管PD-1和PD-2所形成的锁存器存储比特，其中，将比特的互补值存储在数据节点110和数据节点112中。通过位线BL和BLB可以将存储的比特写入SRAM单元10中或者从SRAM单元10中读取该存储的比特。
上拉晶体管PU-1和PU-2的源极连接至具有正电源电压(和线)Vdd的电压节点Vdd。下拉晶体管PD-1和PD-2的源极连接至电源电压(和线)Vss，该电源电压节点Vss进一步连接至电源电压/线Vss(例如，电接地)。晶体管PU-1和PD-1的栅极连接至晶体管PU-2和PD-2的漏极，该连接节点是数据节点110。晶体管PU-2和PD-2的栅极连接至晶体管PU-1和PD-1的漏极，该连接节点是数据节点112。传输门晶体管PG-1的源极/漏极区域连接至位线BL。传输门晶体管PG-2的源极/漏极区域连接至位线BLB。
图1B示出SRAM单元10的可选电路图，其中，将图1A中的晶体管PU-1和PD-1表示为第一反相器Inverter-1，并将晶体管PU-2和PD-2表示为第二反相器Inverter-2。第一反相器Inverter-1的输出端连接至晶体管PG-1和第二反相器Inverter-2的输入端。第二反相器Inverter-2的输出端连接至晶体管PG-2和第二反相器Inverter-2的输入端。
图2示出了SRAM单元10的示意性截面图，其中，各层形成在半导体芯片或晶圆上。注意到，图2示意性地示出了互连结构和晶体管的多层，并且可能不反映SRAM单元10的实际截面图。互连结构包括栅极接触层；OD(其中，术语“OD”表示“有源区”)层；通孔层Via_0、Via_1和Via_2；以及金属层M1、M2和M3。每一层都包括一个或多个介电层以及形成在其中的导电部件。位于同一层处的导电部件可以具有彼此基本上齐平的顶面、彼此基本上齐平的底面，并且可以同时被形成。栅极接触层中的部件将晶体管(诸如所示的示例性晶体管PU-1和PU-2)的栅电极连接至上覆层，诸如Via_0层。OD层中的部件将晶体管的源极和漏极区域和阱区的拾取区等连接至上覆层，诸如Via_0层。
图3示出根据示例性实施例的SRAM单元10的布局。在一些实施例中，布局具有图形数据库系统(GDS)格式并且可以在诸如硬盘的有形的非易失性存储介质上实现。通过计算机存取和处理该布局。而且，如在整个说明书中示出的布局和加工步骤中的图案可以形成在具有透明和不透明图案的光刻掩模上，该光刻掩模用于暴露的光刻胶，使得形成如在整个说明书中示出的部件，以具有所示的图案(形状)。因此，本发明中的布局也可以表示结合了在相应布局所示的图案的光刻掩模。例如，图7A中的图案56和60也是布局中的布局图案。而且，图3A还表示在半导体晶圆上形成的电路结构的俯视图。在图3A至图10中，根据一些示例性实施例讨论用于形成SRAM单元10的工艺步骤。
参照图3A，使用形成矩形的虚线10A、10B、10C和10D示出SRAM单元10的外部边界。在两个p阱区域12之间形成N阱区域11。栅电极16与下面的有源区域20形成上拉晶体管PU-1，该上拉晶体管PU-1可以是n阱区域11的一部分并且可以是基于鳍的。栅电极16进一步与下面的有源区域14形成下拉晶体管PD-1，该下拉晶体管PD-1可以是p阱区域12的一部分。栅电极18与下面的有源区域14形成传输门晶体管PG-1。栅电极36与下面的有源区域40形成上拉晶体管PU-2，该上拉晶体管PU-2可以是n阱区域11的一部分。栅电极36进一步与下面的有源区域34形成下拉晶体管PD-2，该下拉晶体管PD-2可以是p阱区域12的一部分。栅电极38与下面的有源区域34形成传输门晶体管PG-2。根据一些实施例，有源区域14、20、34和40可以是半导体鳍(其为长带)。根据一些实施例，晶体管PG-1和PG-2、PU-1和PU-2以及PD-1和PD-2可以是鳍式场效应晶体管(FinFET)。
在晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2上方，形成一层或多个介电层50。在图3B和图3C中也示出了介电层50，图3B和图3C分别是通过图3A中的平面剖切线B-B和C-C所截取的截面图。参照图3B和3C，在一些实施例中，(一层或多层)介电层50包括层间介电(ILD)层50，形成该层间介电(ILD)层50以覆盖晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2(图3A)的源极和漏极区域。该源极和漏极区域可以是图3A中的有源区域14、20、34和40的鳍部分。而且，在图2中示出ILD层50，其中，示意性示出了晶体管XORT1和XORT2以表示晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2。也如图3B和图3C所示，在ILD50上方形成作为覆盖层的硬掩模层52。
如图3B和图3C所示，在半导体衬底48(其可以是硅衬底)上方形成介电层50，但是在衬底48中可以包含其它半导体材料，诸如硅锗、硅碳、III-V族化合物半导体材料等。图3B示出在半导体衬底48中形成的诸如浅沟槽隔离(STI)区域49的绝缘区域。在图3C中，示出了栅叠层51，其中，栅叠层51表示晶体管PG-2和PD-2(图3A)的栅叠层。在栅叠层51的侧壁上形成栅极间隔件53。ILD50由介电材料形成，该介电材料可以是介电常数(k值)小于约3.0的低k介电材料，但是也可以使用具有更高k值的介电材料。例如，介电层50可以包含基于氧化硅的介电材料，诸如磷硅酸盐玻璃(PSG)、硼硅酸盐(BSG)、掺硼磷硅酸盐玻璃(BPSG)、原硅酸四乙酯(TEOS)氧化物等。介电层50也可以包含选自氮氧化硅、氮化硅、含碳的电介质和含氮的电介质的材料。
在介电层50上方形成硬掩模层52，并且硬掩模层52与ILD50相比由具有足够的蚀刻选择性的材料形成，从而在后续工艺步骤中，可以图案化并去除硬掩模层52而不对介电层50造成明显的损害。在一些示例性实施例中，硬掩模层52包含选自基于氧化硅的电介质、氮氧化硅、氮化硅、多晶硅、非晶硅、含碳的电介质、含氮的电介质、有机材料、难熔金属及它们的组合的材料。
在硬掩模层52上方，形成并图案化光刻胶54(其在图3C中示出)以在其中形成长开口56。光刻胶54的形成可以包括印刷或旋涂。光刻胶54的图案化可以包括使用波长等于例如193nm的光(ArF光)、电子束或远紫外线(EUV)光进行曝光。图4示出在其中包括多个长开口56的图案化的光刻胶54的俯视图。示出了单元边界10A、10B、10C和10D以表明示例性开口56的位置相对于单元边界10A、10B、10C和10D的位置。在一些实施例中，光刻胶开口56与长边界10A和10B平行，并且从短边界10C一直延伸到短边界10D，其中，短边界10C和10D短于长边界10A和10B。光刻胶开口56可以彼此平行。而且，一些光刻胶开口56可以与单元边界10A和10B重叠。
图5是包括图案化的光刻胶54和下面的晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2的示图。图4和图5表明，根据一些示例性实施例，除了形成光刻胶开口56以暴露出下面的部件，还形成图案化的光刻胶54作为覆盖层。
接下来，使用光刻胶54作为蚀刻掩模对硬掩模层52实施蚀刻步骤，使得如图6A、图6B和图6C所示，在硬掩模层52中形成开口58。除了现已形成开口58，图6A的俯视图类似于图5的俯视图。开口58与光刻胶开口56对准。图6B和图6C分别是通过图6A中的平面剖切线B-B和C-C所截取的截面图。图6B示出光刻胶开口56的平面，并因此在该平面中未示出光刻胶54。在图6C中，示出与上面的光刻胶开口56对准的三个开口58。如图6A所示，介电层50的一些部分与半导体鳍14、20、34和40的一些源极/漏极部分重叠，此外如图6C所示，介电层50的这些部分通过开口56和58暴露出来。
参照图7A、图7B和图7C，去除光刻胶54，在如图6C所示的生成的结构上方形成阻挡层60(包括60A和60B)，然后对其进行图案化。图7B和图7C分别是由图7A中的平面剖切线B-B和C-C所截取的截面图。根据一些示例性实施例，阻挡层60包含光刻胶，但阻挡层60也可以由与下面的硬掩模层52和介电层50(图7B和图7C)的材料不同的其它材料形成。根据一些实施例，阻挡层60包括阻挡层部分60A，该阻挡层部分可以是长度方向(longitudinal direction)与开口58的长度方向垂直的带。此外，可以形成小于部分60A的阻挡层部分60B。部分60B是用于阻止所生成的接触塞桥接的定制部分。
如图7A、图7B和图7C所示，在介电层50上方存在两种掩模层。根据一些示例性实施例，第一掩模层可以是图案化的硬掩模层52，而第二掩模层可以是图案化的阻挡层60。第一掩模层和第二掩模层的每一个均覆盖(阻挡)介电层50的一些部分并保持一些其它部分未被覆盖。第一掩模层和第二掩模层结合起来保持介电层50的部分50A(图7A、图7B和图7C)未被覆盖。覆盖介电层50的其余部分。
图7A、图7B和图7C中的第一掩模层52和第二掩模层60结合起来用作蚀刻掩模来蚀刻介电层50的暴露部分50A。在蚀刻步骤之后，去除阻挡层60和硬掩模层52。图8A、图8B和图8C示出所生成的结构。图8B和图8C分别是通过图8A中的平面剖切线B-B和C-C所截取的截面图。作为蚀刻的结果在介电层50中形成接触件开口(contact opening)62。如图8A所示，通过接触件开口62暴露鳍14、20、34和40的源极/漏极部分。
参照图9A、图9B和图9C，用导体材料填充图8A至图8C中的接触件开口62以形成接触塞64，该接触塞64连接至晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2的源极和漏极区域。图9B和图9C分别是通过图9A中的平面剖切线B-B和C-C所截取的截面图。接触塞64可以包含铜、钛、钽、钨、铝、或它们的合金。接触塞64可以对应于图2中的OD层接触塞。
接触塞64是分立的接触塞。参照图10，接触塞64包括接触塞64A1、64A2、64B1和64B2，其位于晶体管PD-1、PU-1、PU-2和PD-2的漏极区域上方并且与晶体管PD-1、PU-1、PU-2和PD-2的漏极区域连接。可以在接触塞64的上方形成诸如接触塞、金属线、通孔或它们的组合的其它金属连接件66(包括66A和66B)，并且这些金属连接件66可以进一步互连接触塞64。例如，金属连接件66A位于接触塞64A1和64A2上方并且互连接触塞64A1和64A2。金属连接件66B位于接触塞64B1和64B2上方并且互连接触塞64B1和64B2。
图11和图12示出根据可选实施例的形成SRAM单元10的中间阶段的俯视图。除非另有说明，否则在这些实施例中(以及在图13至图17的实施例中)的部件的材料和形成方法与在图1至图10所示的实施例中用相同参考编号表示的相同元件基本上相同。因此，关于图11和图12所示的部件的形成工艺和材料的具体细节可以在图1至图10所示的实施例的论述中找到。
参照图11，形成晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2，并且在其上方形成(一层或多层)介电层50，其中介电层50的截面图与图3B和图3C所示的基本相同。接下来，在介电层50上方形成阻挡层60’并对阻挡层60’进行图案化。可以使用选自与图3A至图3C中的硬掩模层52相同的候选材料组的材料来形成阻挡层60’。阻挡层60’可以具有与图7A中的阻挡层60相同的布局并覆盖SRAM单元10与图7A中的阻挡层60相同部分。
接下来，如图12所示，在图11的结构上方形成掩模层52’。图案化掩模层52’以形成开口58，除了开口58现位于掩模层52’中，该开口58可以具有与图4中的开口56相似的形状、尺寸和位置。例如，开口58可以具有等于SRAM单元10的长边界10A和10B的长度并且可以与SRAM单元10的长边界10A和10B重叠。可以使用选自与图7A至图7C中的层60相同的候选材料组的材料来形成掩模层52’。阻挡层60’和掩模层52’结合起来覆盖(阻挡)介电层50的一些部分，并且保留介电层50的部分50A未被覆盖。
接下来，阻挡层60’和掩模层52’结合起来用作蚀刻掩模来蚀刻下面的介电层50(也参见图8A至图8C)，以形成接触件开口62。然后，去除阻挡层60’和掩模层52’。所生成的结构与图8A至图8C中的结构相同。在随后的步骤中，实施图9A、图9B、图9C和图10的工艺来完成SRAM单元10的形成。
图13示出了根据可选实施例的SRAM单元10的俯视图。除了与图10中的单鳍晶体管PG-1、PD-1、PG-2和PD-2相比，晶体管PG-1、PD-1、PG-2和PD-2是多鳍晶体管，这些实施例类似于图10中的实施例。虽然示出了晶体管PG-1、PD-1、PG-2和PD-2中的每一个都包含两个鳍，但是它们可以包含多于两个鳍，诸如三个鳍、四个鳍或更多个鳍。形成工艺可以与图3至图12所示相同，并因此在此不再论述。在图13中，示出掩模层图案60以表明它们的位置相对于晶体管的位置，但是在形成接触塞64时，已经去除了掩模层图案60。
图14至图16示出了根据可选实施例的形成SRAM单元10的中间阶段的俯视图。参照图14，形成晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2，以及形成(一层或多层)介电层50和掩模层52”，其中，图14中的结构的截面图与图3B和图3C的截面图基本相同。接下来，如图15所示，在介电层50和掩模层52”上方形成掩模层60”并对其进行图案化。根据一些实施例，如图14和图16所示，首先形成其中包括开口58的掩模层52”，然后在掩模层52”上方形成掩模层60”。相应的工艺可以与图3A至图10所示的工艺基本相同，其中，掩模层52”的形成对应于硬掩模层52的形成，以及掩模层60”的形成对应于阻挡层60的形成。在可选实施例中，首先形成掩模层60”，然后在掩模层60”上方形成掩模层52”。相应的工艺可以与图11、图12和图9A至图10所示的工艺基本相同，其中，掩模层60”的形成对应于阻挡层60’的形成，以及掩模层52”的形成对应于掩模层52’的形成。可以观察到，在图15中，掩模层60”形成岛状件(islands)(而不是长带)并具有与掩模层60(图7A)和60’(图12)的图案不同的图案。结果，蚀刻部分50A(其是介电层50的未被掩模层52”和60”覆盖的部分)以在介电层50中形成开口。
在随后的步骤中，如图16所示，填充由于蚀刻介电层50而生成的开口以形成接触塞64。接触塞64包括是长接触件的64C和64D。接触塞64C互连晶体管PD-1和PU-1的漏极区域以形成数据节点110(也参照图1)的一部分。接触塞64D互连晶体管PD-2和PU-2的漏极区域以形成数据节点112(也参照图1)的一部分。换句话说，接触塞64C执行与图10中的接触塞64A1、64A2和金属连接件66A相同的功能，而接触塞64D执行与图10中的接触塞64B1、64B2和金属连接件66B相同的功能。因此，虽然掩模层60”比图7A中的掩模层60和图11中的掩模层60’具有更复杂的布局，但是当采用图14至图16中的实施例时，可以省略金属连接件66A和66B的形成。
图17示出根据可选实施例的SRAM单元10的俯视图。除了与图16中的单鳍晶体管PG-1、PD-1、PG-2和PD-2相比，晶体管PG-1、PD-1、PG-2和PD-2是多鳍晶体管，这些实施例与图16中的实施例相似。虽然示出了晶体管PG-1、PD-1、PG-2和PD-2包含两个鳍，但是它们可以包含两个以上的鳍，诸如三个鳍、四个鳍或更多个鳍。形成工艺可以与图14至图16所示的工艺相同，因此在此不再论述。
在上述实施例中，示出并论述了单个SRAM单元来说明实施例。可以理解，SRAM阵列可以包含多个SRAM单元。为了形成SRAM阵列，可以使用如图18A和图18B的方案。图18B中的SRAM单元10-11、10-12、10-21和10-22具有完全相同的结构，并且可以具有图10、图13、图16、图17等中的任何结构。SRAM单元10-11、10-12、10-21和10-22设置在第一行、第二行、第一列和第二列中。在SRAM单元10-11、10-12、10-21和10-22中的每一个单元中都示出的符号“F”以表示该SRAM单元的定向。可以理解符号“F”仅用于表明SRAM单元的方向并且不是相应的SRAM单元的一部分。SRAM单元10-11和SRAM单元10-12相对于所示的Y轴是对称的。SRAM单元10-21和SRAM单元10-22相对于所示的Y轴是对称的。SRAM单元10-11和SRAM单元10-21相对于所示的X轴是对称的。SRAM单元10-12和SRAM单元10-22相对于所示的X轴是对称的。可以按照多个行和列来复制和分配SRAM单元10-11、10-12、10-21和10-22(作为一组)以形成SRAM阵列。
图19至图21示出了根据可选实施例的形成SRAM单元10的中间阶段的俯视图。除了开口58包括开口58A，该开口58A没有从SRAM单元10的一个边界一直延伸到相对边界，这些实施例类似于图14至图16中的实施例。开口58还包括从SRAM单元10的一个边界延伸到相对边界的开口58B。在这些实施例中，开口58A彼此分开并且可以对准成一条直线。开口58A也延伸到SRAM单元10的短边界并因此与相邻的SRAM单元10(未示出，请参照图18)中的开口58A(未示出)连接。在下文论述简单的工艺。
参照图19，形成晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2，以及形成(一层或多层)介电层50和掩模层52”，其中，图19中的结构的截面图与图3B和图3C的截面图基本相同。接下来，如图20所示，在介电层50和掩模层52”上方形成掩模层60”并对其进行图案化。根据一些实施例，如图19和图20所示，首先形成其中包括开口58的掩模层52”，接下来在掩模层52”上方形成掩模层60”。相应的工艺可以与图3A至图10所示的工艺基本相同，其中，掩模层52”的形成对应于硬掩模层52的形成，以及掩模层60”的形成对应于阻挡层60的形成。在可选实施例中，首先形成掩模层60”，然后，在掩模层60”上方形成掩模层52”。相应的工艺可以与图11、图12和图9A至图10所示的工艺基本相同，其中，掩模层60”的形成对应于阻挡层60’的形成，以及掩模层52”的形成对应于掩模层52’的形成。掩模层52”和掩模层60”结合起来保持介电层50的部分50A未被覆盖。可以观察到，当与图15相比时，在图20中，在SRAM单元10的中间具有小的掩模图案60”。因为在一些实施例中难以在SRAM单元10的中间形成小的掩模图案60”(图15)，所以首先形成断开的开口58A降低工艺难度。
在随后的步骤中，如图21所示，蚀刻介电层50以形成开口，然后填充该开口以形成接触塞64。还如图20和图21所示，开口58A与掩模层60”结合起来形成缩短的接触塞64C和64D。而且，开口58B与掩模层60”结合起来也形成缩短的接触塞。接触塞64C互连晶体管PD-1和PU-1的漏极区域以形成数据节点110(参照图1)的一部分。接触塞64D互连晶体管PD-2和PU-2的漏极区域以形成数据节点112(参照图1)的一部分。换句话说，接触塞64C执行与图10中的接触塞64A1、64A2和金属连接件66A相同的功能，而接触塞64D执行与图10中的接触塞64B1、64B2和金属连接件66B相同的功能。因此，虽然掩模层60”比图7A中的掩模层60具有更复杂的布局，但是当采用图19至图21中的实施例时，可以省略图10中的金属连接件66A和66B的形成。
图22至图24示出了根据可选实施例的形成SRAM单元10的中间阶段的俯视图。除了开口58包括未延伸到SRAM单元10的任何边界的开口58A，这些实施例类似于图19至图21中的实施例。开口58A彼此分开并且可以对准成一条直线。开口58A也未延伸到SRAM单元10的任何一个边界并因此与相邻的SRAM单元(未示出，请参照图18)中的开口58A(未示出)断开。在下文论述简单的工艺。
参照图22，形成晶体管PU-1、PU-2、PD-1、PD-2、PG-1和PG-2，以及形成(一层或多层)介电层50和掩模层52”，其中，开口58(包括58A和58B)形成在掩模层52”中。图22中的结构的截面图与图3B和图3C的截面图基本相同。接下来，如图23所示，在介电层50上方形成掩模层60”并对其进行图案化。根据一些实施例，如图22和图23所示，首先形成其中包括开口58的掩模层52”，然后在掩模层52”上方形成掩模层60”。图23示出相应的掩模层60”。可以观察到，因为开口58A最初(形成时)与SRAM单元10的短边界间隔开，所以掩模层60”不需要覆盖开口58A。在可选实施例中，首先形成掩模层60”，然后，在掩模层60”上方形成掩模层52”。相应的工艺可以与图11、图12和图9A至图10所示的工艺基本相同，其中，掩模层60”的形成对应于阻挡层60’的形成，以及掩模层52”的形成对应于掩模层52’的形成。图23和图24中的其余步骤分别与图20和图21中的基本相同，因而在此不再重复。
在实施例中，通过形成两个掩模层(例如，一个硬掩模层和一个阻挡层)，减轻了由于光刻工艺所带来的限制。例如，参照图16，接触塞64C的线端67B面对接触塞64D的线端67B，其中，线端67A和67B彼此靠近并具有非常小的间隔S1，间隔S1可以介于约20nm和约50nm之间。如果使用常规的光刻方法形成，则如此小的间隔S1可能会导致线端短路或线端与线端桥接。当使用FinFET形成SRAM单元时，由于FinFET的窄有源区域需要长接触件，这个问题将进一步恶化。然而，根据本发明的实施例，为了形成接触塞，形成宽和/或长的掩模层图案，而不是常规的窄和短的图案。因而减少了线端短路或线端与线端桥接问题。
根据一些实施例，一种方法包括在SRAM单元的一部分上方形成介电层。SRAM单元包括第一上拉晶体管和第二上拉晶体管、与第一上拉晶体管和第二上拉晶体管形成交叉锁存的反相器(cross-latched inverter)的第一下拉晶体管和第二下拉晶体管、以及分别连接至第一上拉晶体管和第一下拉晶体管的漏极和第二上拉晶体管和第二下拉晶体管的漏极的第一传输门晶体管和第二传输门晶体管。在介电层上方形成第一掩模层，并对第一掩模层进行图案化。在介电层上方形成第二掩模层，并对第二掩模层进行图案化。将第一掩模层和第二掩模层结合起来用作蚀刻掩模来蚀刻介电层，其中在介电层中形成接触件开口。在接触件开口中形成接触塞。
根据其它实施例，一种方法包括形成包括多个栅电极和多个有源区域带的SRAM单元，其中，多个有源区域带与多个栅电极形成晶体管。该方法进一步包括在多个栅电极和多个有源区域带上方形成ILD以及在ILD上方形成第一掩模层。第一掩模层覆盖ILD的第一部分，并且ILD的第二部分通过第一掩模层中的开口暴露出来。形成第二掩模层使其一部分填充到位于第一掩模层中的开口的一部分中。使用第一掩模层和第二掩模层作为蚀刻掩模来蚀刻ILD，以在ILD中形成多个接触件开口。在多个接触件开口中形成多个接触塞。
根据又一些实施例，在非易失性计算机可读介质上实现SRAM单元布局。SRAM单元布局包括多个栅电极的多个第一布局图案和多条鳍线的多个第二布局图案。多个第一布局图案和多个第二布局图案是包括第一上拉晶体管和第二上拉晶体管以及第一下拉晶体管和第二下拉晶体管的交叉锁存的反相器的一部分和连接至交叉锁存的反相器的两个传输门晶体管的一部分。SRAM单元布局进一步包括第一掩模层的多个第三布局图案和第二掩模层的多个第四布局图案，其中，多个第三布局图案与多个第四布局图案不重叠的部分包含SRAM单元的接触塞图案。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的精神和范围的情况下，进行各种改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求都构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种方法，包括：
在静态随机存取存储器(SRAM)单元的一部分上方形成介电层，所述SRAM单元包括：
第一上拉晶体管和第二上拉晶体管；
第一下拉晶体管和第二下拉晶体管，与所述第一上拉晶体管和所述第二上拉晶体管形成交叉锁存的反相器；和
第一传输门晶体管和第二传输门晶体管，分别连接至所述第一上拉晶体管和所述第一下拉晶体管的漏极以及所述第二上拉晶体管和所述第二下拉晶体管的漏极；
在所述介电层上方形成并图案化第一掩模层；
在所述介电层上方形成第二掩模层；
将所述第一掩模层和所述第二掩模层结合起来用作蚀刻掩模来蚀刻所述介电层，在所述介电层中形成接触开口；以及
在所述接触开口中形成接触塞。
2.根据权利要求1所述的方法，其中，所述第一掩模层包含选自基本上由基于氧化硅的电介质、氮氧化硅、氮化硅、多晶硅、非晶硅、含碳介电材料、含氮介电材料、有机材料、难熔金属以及它们的组合所组成的组的材料。
3.根据权利要求2所述的方法，其中，所述第二掩模层包含光刻胶，并且所述第二掩模层位于所述第一掩模层上方。
4.根据权利要求1所述的方法，其中，在图案化所述第一掩模层的步骤之后，所述第一掩模层形成其中具有第一长接触开口的连续层，所述第一长接触开口的长度方向平行于所述SRAM单元的长边界，并且所述第一长接触开口的长度大于或者等于所述长边界的长度。
5.根据权利要求4所述的方法，其中，所述连续层中进一步包含第二长接触开口，所述第二长接触开口的长度方向平行于所述SRAM单元的长边界，并且所述第二长接触开口的长度小于所述长边界的长度。
6.根据权利要求5所述的方法，其中，所述第二长接触开口延伸到所述SRAM单元的边界。
7.根据权利要求5所述的方法，其中，所述第二长接触开口未延伸到所述SRAM单元的任何边界。
8.根据权利要求1所述的方法，其中，在图案化所述第一掩模层的步骤之后，所述第一掩模层形成彼此分离的岛状件。
9.一种方法，包括：
形成包括多个栅电极和多个有源区域带的静态随机存取存储器(SRAM)单元，所述多个有源区域带与所述多个栅电极形成晶体管；
在所述多个栅电极和所述多个有源区域带上方形成层间电介质(ILD)；
在所述ILD上方形成第一掩模层，所述第一硬掩模层覆盖所述ILD的第一部分，并且通过所述第一掩模层中的开口暴露所述ILD的第二部分；
形成第二掩模层，所述第二掩模层包括填充到所述第一掩模层中的部分开口中的部分；
使用所述第一掩模层和所述第二掩模层作为蚀刻掩模来蚀刻所述ILD以在所述ILD中形成多个接触开口；以及
在所述多个接触开口中形成多个接触塞。
10.一种在非易失性计算机可读介质上实现的静态随机存取存储器(SRAM)单元布局，所述SRAM单元布局包括：
多个栅电极的多个第一布局图案；
多个鳍线的多个第二布局图案，所述多个第一布局图案和所述多个第二布局图案是以下部件的一部分：
交叉锁存的反相器，包含第一上拉晶体管和第二上拉晶体管以及第一下拉晶体管和第二下拉晶体管；和
两个传输门晶体管，连接至所述交叉锁存的反相器；
第一掩模层的多个第三布局图案；以及
第二掩模层的多个第四布局图案，其中，所述多个第三布局图案与所述多个第四布局图案不重叠的部分包含所述SRAM单元的接触塞图案。
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