TW201421272A - 靜態隨機存取記憶體裝置的製造方法及其佈局 - Google Patents

靜態隨機存取記憶體裝置的製造方法及其佈局 Download PDF

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TW201421272A
TW201421272A TW102141598A TW102141598A TW201421272A TW 201421272 A TW201421272 A TW 201421272A TW 102141598 A TW102141598 A TW 102141598A TW 102141598 A TW102141598 A TW 102141598A TW 201421272 A TW201421272 A TW 201421272A
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Jhon-Jhy Liaw
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Abstract

本發明提供一種靜態隨機存取記憶體裝置的製造方法及其佈局。上述方法包括於靜態隨機存取記憶體晶胞上形成介電層。靜態隨機存取記憶體晶胞包括第一和第二上拉電晶體；第一和第二下拉電晶體，與第一上拉電晶體和第二上拉電晶體形成交叉鎖定反相器；第一傳送閘電晶體和第二傳送閘電晶體，分別連接至第一上拉和下拉電晶體的汲極以及第二上拉和下拉電晶體的汲極。於介電層上形成和圖案化第一遮罩層。於介電層上形成第二遮罩層。利用第一遮罩層和第二遮罩層結合成的蝕刻遮罩蝕刻介電層，於介電層中形成接觸開口。於接觸開口中形成接觸插塞。

Description

靜態隨機存取記憶體裝置的製造方法及其佈局
本發明係有關於一種靜態隨機存取記憶體裝置的製造方法及其佈局，特別係有關於一種鰭式靜態隨機存取記憶體裝置的製造方法及其佈局。
在深微米技術中，會持續微縮接觸插塞的尺寸以符合日漸縮短的閘極間距。相較於正方形接觸插塞，在微縮接觸插塞的尺寸且不影響接觸電阻的情形下，係採用長接觸插塞。藉由使用長接觸插塞，可降低接觸插塞的寬度，且上述寬度係沿閘極間距方向量測。上述長接觸插塞有較大的長度，且上述長度係沿閘極繞線(閘極縱向)方向量測。藉由使用長接觸插塞，可增加主動區接觸尺寸和微影曝光面積兩者。
長接觸插塞可達到高閘極密度和低接觸電阻兩個目的。然而，仍會存在顧慮，舉例來說，在相鄰的長接觸插塞末端會發生線末短縮(line-end shortening)及/或線末對線末橋接(line-end to line-end bridging)問題。這些問題會導致接觸對鰭主動區開口(也被稱為接觸短路(contact shortening))或導致接觸對接觸橋接(也被稱為接觸橋接(contact bridging))。為了降低線末短縮(line-end shortening)問題的可能性，需要一種進一步限制的間距規則，以增加相鄰接觸插塞末端的間距，以及 在線末端需要一種更具侵略性的光學近場校正(optical proximity correction，OPC)方法。然而，這些解決方式會影響積體電路的尺寸。在未來的鰭式金氧半導體場效電晶體(fin-type MOSFET(簡稱為3D MOSFET))中，因為3D MOSFET的主動區非常窄，所以會更加惡化上述問題。
有鑑於此，本發明揭露之一實施例係提供一種靜態隨機存取記憶體裝置的製造方法，上述靜態隨機存取記憶體裝置的製造方法係包括於一靜態隨機存取記憶體晶胞上方形成一介電層。上述靜態隨機存取記憶體晶胞包括一第一上拉電晶體和一第二上拉電晶體；一第一下拉電晶體和一第二下拉電晶體，與上述第一上拉電晶體和上述第二上拉電晶體形成一交叉鎖定反相器；一第一傳送閘電晶體和一第二傳送閘電晶體，分別連接至上述第一上拉電晶體和上述第一下拉電晶體的汲極以及上述第二上拉電晶體和上述第二下拉電晶體的汲極。於上述介電層上方形成和圖案化一第一遮罩層。於上述介電層上方形成一第二遮罩層。利用上述第一遮罩層和上述第二遮罩層結合而成的一蝕刻遮罩，蝕刻上述介電層，其中於上述介電層中形成一接觸開口。於上述接觸開口中形成一接觸插塞。
本發明揭露之另一實施例係提供一種靜態隨機存取記憶體裝置的製造方法，上述靜態隨機存取記憶體裝置的製造方法係包括形成一靜態隨機存取記憶體晶胞，其包括複數個閘極和複數個主動區條狀物，其中上述些主動區條狀物與上述些閘極係形成電晶體；於上述些閘極與上述些主動區條狀物上 方形成一介電層；於上述介電層上方形成一第一遮罩層，其中上述第一遮罩層覆蓋上述介電層的第一部分，且上述介電層的第二部分從上述第一遮罩層中的開口中暴露出來；形成一第二遮罩層，其中上述第二遮罩層包括填充部分上述第一遮罩層中的上述些開口的部分；利用上述第一遮罩層和上述第二遮罩層成為的一蝕刻遮罩，蝕刻上述介電層，以於上述介電層中形成複數個接觸開口。於上述些接觸開口中形成複數個接觸插塞。
本發明揭露之又一實施例係提供一種靜態隨機存取記憶體裝置的佈局，其用於一非暫時性電腦可讀取媒體上，上述靜態隨機存取記憶體裝置的佈局包括複數個閘極的一第一複數個佈局圖案；複數個鰭線的一第二複數個佈局圖案，其中上述第一複數個佈局圖案和上述第二複數個佈局圖案為：包括一第一和一第二下拉電晶體和一第一和一第二下拉電晶體的複數個交叉鎖定反相器；以及兩個傳送閘電晶體，耦接至上述些交叉鎖定反相器。上述靜態隨機存取記憶體裝置的佈局更包括一第一遮罩層的一第三複數個佈局圖案的部分；一第二遮罩層的一第四複數個佈局圖案，其中上述第三複數個佈局圖案的部分並未重疊於上述第四複數個佈局圖案，且第四複數個佈局圖案包括上述靜態隨機存取記憶體裝置的接觸插塞圖案。
10、10-11、10-12、10-21、10-22‧‧‧靜態隨機存取記憶體晶胞
110、112‧‧‧資料節點
10A、10B、10C、10D‧‧‧外邊界
11‧‧‧N型井區
12‧‧‧P型井區
16、18、36、38‧‧‧閘極
14、20、34、40‧‧‧主動區
48‧‧‧半導體基板
49‧‧‧淺溝槽隔絕區
50‧‧‧介電層
50A‧‧‧部分
51‧‧‧閘極堆疊
52、52’‧‧‧硬遮罩層
52”‧‧‧遮罩層
53‧‧‧閘極間隙壁
54‧‧‧光阻
56‧‧‧長開口
58‧‧‧開口
60、60A、60B、60’‧‧‧覆蓋層
60”‧‧‧遮罩層
62‧‧‧接觸開口
64、64A1、64A2、64B1、64B2、64C、64D‧‧‧接觸插塞
66、66A、66B‧‧‧金屬連接物
67A、67B‧‧‧線末端
PD-1、PD-2‧‧‧下拉電晶體
PG-1、PG-2‧‧‧傳送閘電晶體
PU-1、PU-2‧‧‧上拉電晶體
WL‧‧‧字元線
BL、BLB‧‧‧位元線
Vdd‧‧‧電壓節點
Vss‧‧‧電源供應電壓
I-1‧‧‧第一反相器
I-2‧‧‧第二反相器
GC‧‧‧閘極接觸層別
ODC‧‧‧主動區接觸層別
V_0、V_1、V_2‧‧‧介層孔層別
M1、M2、M3‧‧‧金屬層
XORT-1、XORT-2‧‧‧電晶體
S1‧‧‧間距
R1‧‧‧第一列
R2‧‧‧第二列
C1‧‧‧第一行
C2‧‧‧第二行
第1A和1B圖為本發明實施例之靜態隨機存取記憶體晶胞(SRAM cell)的電路圖。
第2圖為本發明實施例之一靜態隨機存取記憶體晶胞 (SRAM cell)的剖面示意圖。
第3A-3C、4-5、6A-9A、6B-9B、6C-9C、10圖為本發明不同實施例之靜態隨機存取記憶體晶胞(SRAM cell)的製造方法的中間製程步驟的俯視圖和剖面圖。
第11、12圖為本發明不同實施例之靜態隨機存取記憶體晶胞(SRAM cell)的製造方法的中間製程步驟的上視圖。
第13圖顯示本發明實施例之一靜態隨機存取記憶體晶胞(SRAM cell)，其中靜態隨機存取記憶體晶胞中的一些電晶體為多鰭的鰭式電晶體。
第14-16圖為本發明其他實施例之靜態隨機存取記憶體晶胞(SRAM cell)的製造方法的中間製程步驟的俯視圖。
第17圖顯示本發明實施例之靜態隨機存取記憶體晶胞(SRAM cell)俯視圖，其包括多鰭的鰭式電晶體。
第18圖顯示本發明實施例之重覆的靜態隨機存取記憶體晶胞(SRAM cell)。
第19-24圖為本發明其他實施例之靜態隨機存取記憶體晶胞(SRAM cell)的製造方法的中間製程步驟的俯視圖。
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。雖 然係使用六電晶體SRAM晶胞(6T SRAM)為實施例來說明本發明的概念，但是本發明實施例也可應用於具不同數目電晶體的SRAM晶胞，例如八電晶體SRAM晶胞(8T SRAM)。
本發明不同實施例係提供一種靜態隨機存取記憶體晶胞(SRAM cell)。以下會說明本發明實施例的不同處。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。
第1A圖顯示本發明一些實施例之靜態隨機存取記憶體晶胞(SRAM cell)10的電路圖。SRAM晶胞10可包括P型金氧半導體(PMOS)電晶體的傳送閘電晶體PG-1、PG-2和上拉電晶體PU-1、PU-2，以及N型金氧半導體(NMOS)電晶體的下拉電晶體PD-1、PD-2。傳送閘電晶體PG-1、PG-2的閘極係連接至字元線WL，上述字元線WL係決定SRAM晶胞10是否被選擇。由上拉電晶體PU-1、PU-2和下拉電晶體PD-1、PD-2形成的閂(latch)係儲存一個位元(bit)，其中位元的互補值係儲存於資料節點110和資料節點112。可利用位元線BL和BLB從SRAM晶胞10寫入和讀取上述儲存的位元。
上拉電晶體PU-1、PU-2的源極係連接至電壓節點Vdd，其承載正電源供應電壓(和正電源供應電壓線)Vdd。上述下拉電晶體PD-1、PD-2的源極係連接至電源供應電壓(和線)Vss，其進一步連接至電源供應電壓/線Vss(例如為一電性接地)。上拉電晶體PU-1和下拉電晶體PD-1的閘極係連接至上拉電晶體PU-2和下拉電晶體PD-2的汲極，且上拉電晶體PU-2和下拉電晶體PD-2的汲極連接至資料節點110。上拉電晶體PU-2和下拉電晶體PD-2的閘極係連接至上拉電晶體PU-1和下拉電晶 體PD-1的汲極，且上拉電晶體PU-1和下拉電晶體PD-1的汲極連接至資料節點112。傳送閘電晶體PG-1的一源/汲極區係連接至位元線BL。傳送閘電晶體PG-2的一源/汲極區係連接至位元線BLB。
第1B圖靜態隨機存取記憶體晶胞(SRAM cell)10的另一種電路圖，其中如第1A圖所示的上拉電晶體PU-1和下拉電晶體PD-1係表示為第一反相器I-1，而上拉電晶體PU-2和下拉電晶體PD-2係表示為第二反相器I-2。第二反相器I-2的輸出連接至傳送閘電晶體PG-2和第二反相器I-2的輸入。
第2圖係顯示靜態隨機存取記憶體晶胞(SRAM cell)10的剖面示意圖，且於一半導體晶片或晶圓上形成SRAM晶胞10不同層。注意第2圖係僅為示意圖，顯示內連線結構和電晶體的不同層，但非反應SRAM晶胞10真實的剖面圖。上述內連線結構包括閘極接觸層別(gate contact level)GC、一主動區接觸層別(active region contact level)ODC、介層孔層別(via level)V_0、V_1、V_2以及金屬層M1、M2、M3。每一個層別(level)包括一或多個介電層和形成於其中的導電物。位於相同層別的上述導電物可具有大體上彼此對齊的頂面，大體上彼此對齊的底面，且可同時形成位於相同層別的上述導電物。位於閘極接觸層別GC的(導電)物係將電晶體的閘極(例如實施例顯示的上拉電晶體PU-1、PU-2)連接至位於上方的一層別，例如介層孔層別V_0。位於主動區接觸層別ODC係將電晶體的源汲極區、井區的打線區或類似的區域連接至位於上方的一層別，例如介層孔層別V_0。
第3圖係顯示靜態隨機存取記憶體晶胞(SRAM cell)10的佈局。在本發明一些實施例中，上述佈局係具有圖形資料庫系統(graphic database system，GDS)的形式，且應用於例如為一硬碟的有形非暫時性儲存媒體(tangible non-transitory storage medium)。可利用一電腦來存取和處理上述佈局。並且，可於微影遮罩上形成上述佈局中的圖案和說明書中的處理步驟，使微影遮罩具有透明和不透明的圖案，且微影遮罩係用於曝光光阻，使說明書中所述的元件形成具有圖示的圖案(形狀)。因此，本發明實施例的佈局也可表示為合併各別顯示佈局的圖案的微影遮罩。舉例來說，第7A圖中的圖案56和60也可為佈局中的佈局圖案。並且，第3A圖也可表示為形成於一半導體晶片上的一電路結構的一俯視圖。在第3A-10圖中，本發明一些實施例會討論形成SRAM晶胞10的製程步驟。
請參考第3A圖，係使用虛線10A、10B、10C和10D來顯示SRAM晶胞10的外邊界，且虛線10A、10B、10C和10D形成長方形。N型井區11係形成於兩個P型井區12之間。閘極16和其下的主動區20係形成上拉電晶體PU-1，而主動區20可為N型井區11的一部分，且上拉電晶體PU-1可為鰭式電晶體。閘極16和其下的主動區14也可形成下拉電晶體PD-1，而主動區20可為P型井區12的一部分。閘極18和其下的主動區14形成傳送閘電晶體PG-1。閘極36和其下的主動區40形成上拉電晶體PU-2，而主動區40可為N型井區11的一部分。閘極36和其下的主動區34也可形成下拉電晶體PD-2，而主動區34可為P型井區12的一部分。閘極38和其下的主動區34形成傳送閘電晶體 PG-2。在本發明一些實施例中，主動區14、20、34和40可為半導體鰭狀物(其為長條物)。在本發明一些實施例中，傳送閘電晶體PG-1、PG-2和下拉電晶體PD-1、PD-2可為鰭式場效電晶體(FINFET)。
於所有的上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2的上方形成一介電層或複數個介電層50。介電層50也顯示於第3B、3C圖中，而第3B、3C圖分別為第3A圖中沿B-B切線和C-C切線的剖面圖。請參考第3B、3C圖，在本發明一些實施例中，介電層50可包括層間介電層(ILD)50，其形成覆蓋上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2的源極和汲極區(第3A圖)。上述源極和汲極區可為第3A圖中的主動區14、20、34和40的鰭狀物部分。並且，如第2圖所示的介電層50，其中電晶體XORT-1和XORT-2係用以表示為各別的上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2。硬遮罩層52係於層間介電層(ILD)50上方形成為一毯覆層，也顯示於第3B、3C圖中。
如第3B、3C圖所示，介電層50形成於半導體基板48的上方，而半導體基板48可為一矽基板，然而半導體基板48中也可以包含例如矽鍺、碳化矽、三-五族化合物半導體材料或類似材料的其他半導體材料。第3B圖顯示形成於半導體基板48中之例如淺溝槽隔絕區(STI region)49的絕緣區。在第3C圖中，顯示閘極堆疊51，其中閘極堆疊51係顯示傳送閘電晶體PG-2和下拉電晶體PD-2的閘極堆疊(第3A圖)。閘極間隙壁53 係形成於閘極堆疊51的側壁上。層間介電層(ILD)50可由一介電材料形成，上述介電材料可為介電常數(k)小於3.0的一低介電常數材料，然而也可使用具高介電常數的介電常數材料。舉例來說，介電層50可包括例如磷矽玻璃(PSG)、硼矽玻璃(BSG)、硼磷矽玻璃(BPSG)、四乙氧基矽烷(TEOS)氧化物或類似材料的氧化矽基介電材料。介電層50也可包括係擇自氮氧化矽、氮化矽、含碳介電質、含氮介電質所組成之族群的一材質。
硬遮罩層52係形成於介電層50上方，且可由相對於介電層50而言具充足蝕刻選擇比的一材料形成，使後續的蝕刻製程步驟中，可圖案化硬遮罩層52而不會對介電層50造成明顯的損傷。在本發明一些實施例中，硬遮罩層52可包括擇自氧化矽基介電材料、氮氧化矽、氮化矽、多晶矽、非晶矽、含碳介電質、含氮介電質、有機材料、耐火材料和上述組合所組成之族群的一材質。
如第3C圖所示，係形成和圖案化位於硬遮罩層52於上方的光阻54，以於光阻54中形成長開口56。光阻54的形成方式可包括網印法或旋轉塗佈法。圖案化光阻54的方式可包括使用波長例如等於193nm(ArF光)的光、電子束或深紫外光(EUV)的一曝光法。第4圖顯示圖案化光阻54的俯視圖，其中包括複數個長開口56。圖式所示的SRAM晶胞10的外邊界10A、10B、10C和10D係顯示本發明實施例的長開口56的位置相對於SRAM晶胞10的外邊界10A、10B、10C和10D的位置。在本發明一些實施例中，光阻長開口56係平行較長的外邊界10A和10B，且從SRAM晶胞10的較短的外邊界10C延伸至SRAM晶胞 10的較短的外邊界10D，其中較短的外邊界10C和10D係短於較長的外邊界10A和10B。光阻長開口56係可彼此平行。並且，一些光阻長開口56可重疊於SRAM晶胞10的外邊界10A和10B。
第5圖為包括圖案化光阻54及下方的上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2的示意圖。在本發明一些實施例中，第4、5圖係顯示，除了形成以暴露下方物體的光阻長開口56之外，圖案化光阻54係形成為一毯覆層。
接著，如第6A、6B和6C圖所示，使用圖案化光阻54做為一蝕刻罩幕，於硬遮罩層52上進行一蝕刻步驟，以於硬遮罩層52中形成開口58。第6A圖係顯示類似於第5圖的俯視圖，除了第6A圖係形成開口58。開口58係對準光阻長開口56。第6B和6C圖分別為沿第6A圖中的B-B和C-C切線的剖面圖。第6B圖係顯示光阻長開口56的平面，因此圖案化光阻54並未顯示於此平面。在第6C圖中，顯示三個開口58且對準其下方的光阻長開口56。如第6A圖所示，介電層50包括重疊於一些半導體鰭狀物(主動區)14、20、34和40的源/汲極部分，且部分介電層50從光阻長開口56和開口58暴露出來，也如第6C圖所示。
請參考第7A、7B和7C圖，移除如第6C圖所示的圖案化光阻54，且於如第6C圖所示的結構上方形成一覆蓋層60(包括覆蓋層部分60A和60B)，接著圖案化覆蓋層60。在本發明一些實施例中，覆蓋層60包括一光阻，然而覆蓋層60也可為其他材料，上述其他材料不同於其下方硬遮罩層52和介電層50的材料(第7B和7C圖)。在本發明一些實施例中，覆蓋層60包括 覆蓋層部分60A，其可為長條物，且上述長條物的一長軸方向垂直於開口58的一長軸方向。另外，可形成小於覆蓋層部分60A的覆蓋層部分60B。覆蓋層部分60B為客製化部分，其可用於防止最終接觸孔插塞產生橋接問題(bridging)。
如第7A、7B和7C圖所示，在介電層50上方有兩個遮罩層。在本發明一些實施例中，第一遮罩層可為圖案化的硬遮罩層52，而第二遮罩層可為圖案化的覆蓋層60。第一遮罩層和第二遮罩層係各別覆蓋介電層50的一些部分，且留下一些未覆蓋的其他部分。第一遮罩層和第二遮罩層的組合係留下介電層50的未覆蓋的部分50A(第7A、7B和7C圖)。介電層50剩下的部分係被覆蓋。
第7A、7B和7C圖中的硬遮罩層52和覆蓋層60係組合做為一蝕刻罩幕，來蝕刻暴露出來的介電層50的部分50A。進行蝕刻步驟之後，移除覆蓋層60和硬遮罩層52。第8A、8B和8C圖係顯示最終的結構。第8B和8C圖分別為沿第8A圖中的B-B和C-C切線的剖面圖，在第8A圖中，半導體鰭狀物(主動區)14、20、34和40的源/汲極部分會從接觸開口62暴露出來。
請參考第9A、9B和9C圖，以一導電材料填充在第8B和8C圖中的接觸開口62以形成接觸插塞64，上述係連接至上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2的源/汲極區。第9B和9C圖分別為沿第9A圖中的B-B和C-C切線的剖面圖，在第9A圖中，接觸插塞64可包括銅、鈦，鉭、鎢、鋁或上述合金。接觸插塞64可對應至第2圖所示的主動區接觸層別ODC的接觸插塞。
接觸插塞64為分離的接觸插塞。請參考第10圖，接觸插塞64可包括接觸插塞64A1、64A2、64B1和64B2，位於上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2的汲極區上方且連接至上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2的汲極區。例如接觸插塞、金屬線、介層孔插塞或上述組合的額外的金屬連接物66(包括金屬連接物66A、66B)可形成於接觸插塞64上方，且內部連接至接觸插塞64。舉例來說，金屬連接物66A形成於接觸插塞64A1、64A2且內部連接至接觸插塞64A1、64A2。金屬連接物66B形成於接觸插塞64B1、64B2且內部連接至接觸插塞64B1、64B2。
第11、12圖為本發明不同實施例之SRAM晶胞10的製造方法的中間製程步驟的上視圖。除了特別提及，在這些實施例(以及第13、17圖中的實施例)的元件的材料和形成方法實質上相同於如第1至10圖所示之以類似元件符號標示的類似元件。因此，如第11、12圖所示的元件的材料和形成方法可於如第1至10圖所示之實施例的討論中得知。
請參考第11圖，形成上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2，且於上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2上方形成(複數個)介電層50，其中介電層50的剖面圖實質上與如第3B、3C圖所示的介電層50相同。接著，於介電層50上方形成覆蓋層60’且圖案化覆蓋層60’。可使用擇自與第3A-3C圖中的硬遮罩層52相同的材料族群來形成覆蓋層60’。覆蓋層60’可與第7A圖中的覆蓋層60具有相同的佈局且覆蓋 SRAM晶胞10的相同部分。
接著，如第12圖所示，於第11圖所示的結構上方形成硬遮罩層52’。圖案化硬遮罩層52’以形成(長)開口56’，除了目前(長)開口56’位於硬遮罩層52’中之外，(長)開口56’的形狀、尺寸和位置係類似於第4圖中的(長)開口56。舉例來說，(長)開口56的長度可等於SRAM晶胞10的(長)外邊界10A、10B，且可與SRAM晶胞10的(長)外邊界10A、10B重疊。可使用擇自與第3A-3C圖中的覆蓋層60相同的材料族群來形成硬遮罩層52’。覆蓋層60’和硬遮罩層52’的組合係覆蓋(遮蓋)介電層50的一些部分，且留下介電層50未覆蓋的部分50A。
接著，覆蓋層60’和硬遮罩層52’的組合係用做為一蝕刻遮罩，蝕刻下方的介電層50(可同時參考第8A-8C圖)以形成接觸開口62。然後，移除覆蓋層60’和硬遮罩層52’。最終結構與第8A-8C圖所示的結構相同。在後續步驟中，進行第9A、9B、9C和10圖中的步驟以完成SRAM晶胞10的形成方法。
第13圖係顯示本發明其他實施例之SRAM晶胞10的俯視圖。相較於第10圖中為單一鰭式電晶體的傳送閘電晶體PG-1、下拉電晶體PD-1、傳送閘電晶體PG-2、下拉電晶體PD-2而言，第13圖為多重鰭式電晶體的傳送閘電晶體PG-1、下拉電晶體PD-1、傳送閘電晶體PG-2、下拉電晶體PD-2之外，這些實施例類似於第10圖所示的實施例。雖然，第13圖所示傳送閘電晶體PG-1、下拉電晶體PD-1、傳送閘電晶體PG-2、下拉電晶體PD-2的每一個包括兩個鰭狀物，然而上述電晶體也可包括多於兩個的鰭狀物，例如三個鰭狀物、四個鰭狀物或多個鰭狀物。 而第13圖顯示的本發明其他實施例之SRAM晶胞10的製造方法係與第3至12圖中顯示的製造方法相同，因而在此不予說明。在第13圖中，雖然此時已經形成接觸插塞64，且已經移除覆蓋層60，然而圖中顯示的覆蓋層(圖案)60的位置為與電晶體位置的相對位置。
第14-16圖為本發明其他實施例之SRAM晶胞10的製造方法的中間製程步驟的俯視圖。請參考第14圖，形成上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2，且於上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2，且形成介電層50和遮罩層52”，其中如第14圖所示結構的剖面圖實質上與第3B和3C圖所示結構相同。接著，如第15圖所示，於介電層50和遮罩層52”上方形成遮罩層60”，且圖案化遮罩層60”。如第14-16圖所示，在本發明一些實施例中，會先形成遮罩層52”，且遮罩層52”中包括開口58，接著於遮罩層52”上方形成遮罩層60”。上述各別的製程可與第3A至10圖所示的製程相同，且遮罩層52”的形成方式係對應於硬遮罩層52的形成方式，而遮罩層60”的形成方式係對應於覆蓋層60的形成方式。在本發明其他實施例中，會先形成遮罩層60”，接著於遮罩層60”上方形成遮罩層52”。上述各別的製程可與第11、12和9A至10圖所示的製程相同，且遮罩層60”的形成方式係對應於覆蓋層60的形成方式，而遮罩層52”的形成方式係對應於硬遮罩層52的形成方式。可以得知在第15圖中，遮罩層60”係形成為島狀(而非長條狀)，且遮罩層60”的圖案不同於遮罩層60(第7A圖)和遮罩層60’(第12圖)。結果， 會蝕刻部分50A，其為介電層50之未被遮罩層52”和60”覆蓋的部分，以於介電層50中形成開口。
在後續步驟中，填充因為蝕刻介電層50形成的開口而形成如第16圖顯示的接觸插塞64。接觸插塞64可包括接觸插塞64C、64D，而接觸插塞64C、64D為長形接觸。接觸插塞64C係內部連接至下拉電晶體PD-1和上拉電晶體PU-1的汲極區，以形成資料節點110(參考第1圖)的一部分。接觸插塞64D係內部連接至下拉電晶體PD-2和上拉電晶體PU-2的汲極區，以形成資料節點112(參考第1圖)的一部分。換句話說，接觸插塞64C與第10圖中的接觸插塞64A1、64A2和金屬連接物66A進行相同的功能，而接觸插塞64D與第10圖中的接觸插塞64B1、64B2和金屬連接物66B進行相同的功能。因此，雖然遮罩層60”具有較第7A圖中的遮罩層60和第11圖中的遮罩層60’複雜的佈局，而在使用第14-16圖中的實施例時，可省略第10圖中的金屬連接物66A、66B的製程。
第17圖係顯示本發明其他實施例之SRAM晶胞10的俯視圖。相較於第16圖中為單一鰭式電晶體的傳送閘電晶體PG-1、下拉電晶體PD-1、傳送閘電晶體PG-2、下拉電晶體PD-2而言，第17圖為多重鰭式電晶體的傳送閘電晶體PG-1、下拉電晶體PD-1、傳送閘電晶體PG-2、下拉電晶體PD-2之外，這些實施例類似於第16圖所示的實施例。雖然，第17圖所示傳送閘電晶體PG-1、下拉電晶體PD-1、傳送閘電晶體PG-2、下拉電晶體PD-2的每一個包括兩個鰭狀物，然而上述電晶體也可包括多於兩個的鰭狀物，例如三個鰭狀物、四個鰭狀物或多個鰭狀物。 而第17圖顯示的本發明其他實施例之SRAM晶胞10的製造方法係與第14至16圖中顯示的製造方法相同，因而在此不予說明。
在前述實施例中，係以一單一SRAM晶胞表示且用以說明實施例。可以理解一SRAM陣列可以包括複數個SRAM晶胞。可利用第18圖的示意圖來形成一SRAM陣列。第18圖中的SRAM晶胞10-11、10-12、10-21、10-22具有完全相同的結構，且可具有第10、13、16、17圖中的任何結構或類似的結構。SRAM晶胞10-11、10-12、10-21、10-22係設置於一第一列R1、一第二列R2、一第一行C1和一第二行C2。每一個SRAM晶胞10-11、10-12、10-21、10-22中顯示的符號”F”係表示SRAM晶胞的取向。可以理解符號”F”僅用來表示的方向，而並非為SRAM晶胞的一部分。SRAM晶胞10-11和10-12係相對Y軸對稱。SRAM晶胞10-21和10-22係相對Y軸對稱。SRAM晶胞10-11和SRAM晶胞10-21係相對X軸對稱。SRAM晶胞10-12和SRAM晶胞10-22係相對X軸對稱。SRAM晶胞10-11、10-12、10-21、10-22的一族群可被複製和配置為複數列和複數行以形成SRAM陣列。
第19至21圖係顯示本發明其他實施例之SRAM晶胞10的製造方法的中間製程步驟的俯視圖。除了第19至21圖的實施例包括開口58A的開口58並未從SRAM晶胞10的一邊界一路延伸至SRAM晶胞10的相對邊界之外，第19至21圖顯示的這些實施例係類似於第14至16圖中的實施例。開口58也可包括開口58B，從SRAM晶胞10的一邊界延伸至SRAM晶胞10的相對邊界。在這些實施例中，開口58A係彼此隔開，且可對齊至一條直線。開口58A也會延伸至SRAM晶胞10的短邊界，且因此會 連接至相鄰SRAM晶胞(圖未顯示)的開口58A(圖未顯示)。以下會說明簡要的製程。
請參考第19圖，形成上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2，且於上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2，且形成介電層50和遮罩層52”，其中如第19圖所示結構的剖面圖實質上與第3B和3C圖所示結構相同。接著，如第20圖所示，於介電層50和遮罩層52”上方形成遮罩層60”，且圖案化遮罩層60”。如第19和20圖所示，在本發明一些實施例中，會先形成遮罩層52”，且遮罩層52”中包括開口58，接著於遮罩層52”上方形成遮罩層60”。上述各別的製程可與第3A至10圖所示的製程相同，且遮罩層52”的形成方式係對應於硬遮罩層52的形成方式，而遮罩層60”的形成方式係對應於覆蓋層60的形成方式。在本發明其他實施例中，會先形成遮罩層60”，接著於遮罩層60”上方形成遮罩層52”。上述各別的製程可與第11、12和9A至10圖所示的製程相同，且遮罩層60”的形成方式係對應於覆蓋層60’的形成方式，而遮罩層52”的形成方式係對應於硬遮罩層52’的形成方式。遮罩層52”和遮罩層60”的組合會留下介電層50的部分50A未被覆蓋。可以得知相較於第15圖，在第20圖中，在SRAM晶胞10的中間沒有小的遮罩層(圖案)60”(第15圖)。由於在一些實施例中，在SRAM晶胞10的中間難以形成小的遮罩層(圖案)60”(第15圖)，所以一開始形成未連接的開口58A會降低製程困難度。
在後續步驟中，蝕刻介電層50以形成開口，之後 於填充上述開口以形成如第21圖中所示的接觸插塞64。如第20和21圖中所示，開口58A結合遮罩層60”會縮短接觸插塞64C、64D。並且，開口58B結合遮罩層60”會縮短接觸插塞。接觸插塞64C係內部連接至下拉電晶體PD-1和上拉電晶體PU-1的汲極區，以形成資料節點110(參考第1圖)的一部分。接觸插塞64D係內部連接至下拉電晶體PD-2和上拉電晶體PU-2的汲極區，以形成資料節點112(參考第1圖)的一部分。換句話說，接觸插塞64C與第10圖中的接觸插塞64A1、64A2和金屬連接物66A進行相同的功能，而接觸插塞64D與第10圖中的接觸插塞64B1、64B2和金屬連接物66B進行相同的功能。因此，雖然遮罩層60”具有較第7A圖中的遮罩層60更複雜的佈局，而在使用第19-21圖中的實施例時，可省略第10圖中的金屬連接物66A、66B的製程。
第22至24圖係顯示本發明其他實施例之SRAM晶胞10的製造方法的中間製程步驟的俯視圖。除了第22至24圖的實施例包括開口58A的開口58並未延伸至SRAM晶胞10的任何邊界之外，第22至24圖顯示的這些實施例係類似於第19至21圖中的實施例。開口58A係彼此隔開，且可對齊至一條直線。開口58A不會延伸至SRAM晶胞10的任何邊界，且因此不會連接至相鄰SRAM晶胞(圖未顯示，請參考第18圖)的開口58A(圖未顯示)。以下會說明簡要的製程。
請參考第22圖，形成上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體PG-1、PG-2，且於上拉電晶體PU-1、PU-2、下拉電晶體PD-1、PD-2、傳送閘電晶體 PG-1、PG-2，且形成介電層50和遮罩層52”，且遮罩層52”中具有開口58(包括開口58A、58B)。如第22圖所示結構的剖面圖實質上與第3B和3C圖所示結構相同。接著，如第23圖所示，於介電層50上方形成遮罩層60”，且圖案化遮罩層60”。如第22和23圖所示，在本發明一些實施例中，會先形成遮罩層52”，且遮罩層52”中包括開口58，接著於遮罩層52”上方形成遮罩層60”。第23圖係顯示各別的遮罩層60”。可以觀察到由於開口58A會先(形成)與SRAM晶胞10的短邊界隔開，所以遮罩層60”不需覆蓋開口58A。在本發明其他實施例中，會先形成遮罩層60”，接著於遮罩層60”上方形成遮罩層52”。上述各別的製程可與第11、12和9A至10圖所示的製程相同，且遮罩層60”的形成方式係對應於覆蓋層60’的形成方式，而遮罩層52”的形成方式係對應於硬遮罩層52’的形成方式。第23和24圖中的後續的製程步驟實質上會各別相同於第20和21圖中的製程步驟，因而在此不再重覆說明。
在本發明實施例中，藉由形成兩個遮罩層，例如一硬遮罩層和一覆蓋層，可以緩和微影製程的限制。舉例來說，請參考第16圖，接觸插塞64C具有線末端67A，其面對於接觸插塞64D的線末端67B，其中線末端67A和67B彼此接近，且相距一非常小的間距S1，上述間距S1可約介於20nm至50nm之間。如果使用習知的微影製程，例如間距S1會導致線末端縮短或線末端對線末端橋接等問題。當使用鰭式電晶體來做為SRAM晶胞時，會因為鰭式電晶體的窄主動區需要長接觸，所以會更加惡化上述問題。然而，在本發明實施例中，接觸製程 會形成寬及/或長遮罩層圖案，而非習知技術的窄和短的圖案。因此會降低線末短縮(line-end shortening)或線末對線末橋接(line-end to line-end bridging)等問題。
本發明一些實施例中，一種靜態隨機存取記憶體裝置的製造方法係包括於一靜態隨機存取記憶體晶胞上方形成一介電層。上述靜態隨機存取記憶體晶胞包括一第一上拉電晶體和一第二上拉電晶體；一第一下拉電晶體和一第二下拉電晶體，與上述第一上拉電晶體和上述第二上拉電晶體形成一交叉鎖定反相器；一第一傳送閘電晶體和一第二傳送閘電晶體，分別連接至上述第一上拉電晶體和上述第一下拉電晶體的汲極以及上述第二上拉電晶體和上述第二下拉電晶體的汲極。於上述介電層上方形成和圖案化一第一遮罩層。於上述介電層上方形成一第二遮罩層。利用上述第一遮罩層和上述第二遮罩層結合而成的一蝕刻遮罩，蝕刻上述介電層，其中於上述介電層中形成一接觸開口。於上述接觸開口中形成一接觸插塞。
本發明其他實施例中，一種靜態隨機存取記憶體裝置的製造方法係包括形成一靜態隨機存取記憶體晶胞，其包括複數個閘極和複數個主動區條狀物，其中上述些主動區條狀物與上述些閘極係形成電晶體；於上述些閘極與上述些主動區條狀物上方形成一介電層；於上述介電層上方形成一第一遮罩層，其中上述第一遮罩層覆蓋上述介電層的第一部分，且上述介電層的第二部分從上述第一遮罩層中的開口中暴露出來；形成一第二遮罩層，其中上述第二遮罩層包括填充部分上述第一遮罩層中的上述些開口的部分；利用上述第一遮罩層和上述第 二遮罩層成為的一蝕刻遮罩，蝕刻上述介電層，以於上述介電層中形成複數個接觸開口。於上述些接觸開口中形成複數個接觸插塞。
本發明其他實施例中，提供一種靜態隨機存取記憶體裝置的佈局，其用於一非暫時性電腦可讀取媒體上，上述靜態隨機存取記憶體裝置的佈局包括複數個閘極的一第一複數個佈局圖案；複數個鰭線的一第二複數個佈局圖案，其中上述第一複數個佈局圖案和上述第二複數個佈局圖案為：包括一第一和一第二下拉電晶體和一第一和一第二下拉電晶體的複數個交叉鎖定反相器；以及兩個傳送閘電晶體，耦接至上述些交叉鎖定反相器。上述靜態隨機存取記憶體裝置的佈局更包括一第一遮罩層的一第三複數個佈局圖案的部分；一第二遮罩層的一第四複數個佈局圖案，其中上述第三複數個佈局圖案的部分並未重疊於上述第四複數個佈局圖案，且第四複數個佈局圖案包括上述靜態隨機存取記憶體裝置的接觸插塞圖案。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何該發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
10‧‧‧靜態隨機存取記憶體晶胞
14、34‧‧‧主動區
20、40‧‧‧主動區
64、64A1、64A2、64B1、64B2‧‧‧接觸插塞
66、66A、66B‧‧‧金屬連接物
PD-1、PD-2‧‧‧下拉電晶體
PG-1、PG-2‧‧‧傳送閘電晶體
PU-1、PU-2‧‧‧上拉電晶體

Claims (10)

  1. 一種靜態隨機存取記憶體裝置的製造方法，包括下列步驟：於一靜態隨機存取記憶體晶胞上方形成一介電層，其中該靜態隨機存取記憶體晶胞包括：一第一上拉電晶體和一第二上拉電晶體；一第一下拉電晶體和一第二下拉電晶體，其中該第一下拉電晶體、該第二下拉電晶體、該第一上拉電晶體和該第二上拉電晶體形成一交叉鎖定反相器；一第一傳送閘電晶體和一第二傳送閘電晶體，分別連接至該第一上拉電晶體和該第一下拉電晶體的汲極以及該第二上拉電晶體和該第二下拉電晶體的汲極；於該介電層上方形成和圖案化一第一遮罩層；於該介電層上方形成一第二遮罩層；使用該第一遮罩層和該第二遮罩層組合做為一蝕刻遮罩，蝕刻該介電層，其中於該介電層中形成一接觸開口；以及於該接觸開口中形成一接觸插塞。
  2. 如申請專利範圍第1項所述之靜態隨機存取記憶體裝置的製造方法，其中圖案化該第一遮罩層之後，該第一遮罩層係形成一連續層，其中該連續層中具有一第一長接觸開口和一第二長接觸開口，其中該第一長接觸開口具有平行於該靜態隨機存取記憶體晶胞的一長邊的一縱向方向，且其中該第一長接觸開口具有一長度，該第一長接觸開口的該長度大於或等於該長邊的一長度，且其中該第二長接觸開口具有平行於該靜態隨機存取記憶體晶胞的該長邊的一縱 向方向，且其中該第二長接觸開口具有一長度，該第二長接觸開口的該長度小於該長邊的該長度。
  3. 如申請專利範圍第2項所述之靜態隨機存取記憶體裝置的製造方法，其中該第二長接觸開口延伸至該靜態隨機存取記憶體晶胞的一邊界。
  4. 如申請專利範圍第2項所述之靜態隨機存取記憶體裝置的製造方法，其中該第二長接觸開口並未延伸至該靜態隨機存取記憶體晶胞的任何邊界。
  5. 如申請專利範圍第1項所述之靜態隨機存取記憶體裝置的製造方法，其中當形成該接觸插塞時，同時形成一額外接觸插塞，其中該接觸插塞係位於該第一下拉電晶體的該汲極上方且連接至該第一下拉電晶體的該汲極，且該額外接觸插塞位於該第一上拉電晶體的該汲極上方且連接至該第一上拉電晶體的該汲極，且其中該接觸插塞和該額外接觸插塞彼此隔開。
  6. 如申請專利範圍第1項所述之靜態隨機存取記憶體裝置的製造方法，其中該接觸插塞係連續延伸於該第一下拉電晶體的該汲極和該第一上拉電晶體的該汲極的上方，且內部連線至該第一下拉電晶體的該汲極和該第一上拉電晶體的該汲極。
  7. 一種靜態隨機存取記憶體裝置的佈局，其用於一非暫時性電腦可讀取媒體上，該靜態隨機存取記憶體裝置的佈局包括：複數個閘極的一第一複數個佈局圖案； 複數個鰭線的一第二複數個佈局圖案，其中該第一複數個佈局圖案和該第二複數個佈局圖案為：包括一第一和一第二下拉電晶體和一第一和一第二下拉電晶體的複數個交叉鎖定反相器；兩個傳送閘電晶體，耦接至該些交叉鎖定反相器的部分；一第一遮罩層的一第三複數個佈局圖案；以及一第二遮罩層的一第四複數個佈局圖案，其中該第三複數個佈局圖案的部分並未重疊於該第四複數個佈局圖案，且第四複數個佈局圖案包括該靜態隨機存取記憶體裝置的接觸插塞圖案。
  8. 如申請專利範圍第7項所述之靜態隨機存取記憶體裝置的佈局，其中該第三複數個佈局圖案包括：一第一開口圖案，與該靜態隨機存取記憶體晶胞的一第一邊界重疊，且該第一開口圖案具有平行於該靜態隨機存取記憶體晶胞的該第一邊界的一縱向方向；以及一第二開口圖案，與該靜態隨機存取記憶體晶胞的一第二邊界重疊，且該第二開口圖案具有平行於該靜態隨機存取記憶體晶胞的該第二邊界的一縱向方向，且該第一邊界和該第二邊界彼此垂直。
  9. 如申請專利範圍第8項所述之靜態隨機存取記憶體裝置的佈局，其中該第一開口圖案從該靜態隨機存取記憶體晶胞的一第三邊界延伸至該靜態隨機存取記憶體晶胞的一第四邊界，且該第三邊界和該第四邊界垂直於該第一邊界。
  10. 如申請專利範圍第7項所述之靜態隨機存取記憶體裝置的 佈局，其中該第一複數個佈局圖案的長度不短於該靜態隨機存取記憶體晶胞的一各別長度。
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