CN108257960B - 静态随机存取存储元件 - Google Patents

静态随机存取存储元件 Download PDF

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CN108257960B
CN108257960B CN201710849991.4A CN201710849991A CN108257960B CN 108257960 B CN108257960 B CN 108257960B CN 201710849991 A CN201710849991 A CN 201710849991A CN 108257960 B CN108257960 B CN 108257960B
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CN108257960A (zh
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黄莉萍
黄俊宪
郭有策
龙镜丞
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United Microelectronics Corp
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明公开一种静态随机存取存储元件。此静态随机存取存储元件是由存储单元中两个作为载入晶体管的P通道栅极、两个作为驱动晶体管的N通道栅极、以及两个作为存取晶体管的N通道栅极所组成。作为存取晶体管的N通道栅极附近会设置一虚置栅极，该两者间隔有一位线节点，其中该虚置栅极是经由一金属层电连接到一接地电压。

Description

静态随机存取存储元件
技术领域
本发明涉及集成电路元件的领域相关，特别是涉及含有鳍式场效晶体管的静态随机存取存储单元。
背景技术
集成电路的功能与效能在过去的四十年间有着爆炸性的成长。在集成电路的演进中，电路的功能密度(即每芯片区域中互连元件的数量)一般会随着图形尺寸(即制作工艺所能制作出的最小部件或是线结构)的缩小而增长。电路尺寸的微缩是有益于增加生产效率并降低相关成本，但同时也会增加IC制作以及制作工艺的复杂度。一般的互补式金属氧化物半导体IC元件中会有两种主要的组成部件，亦即晶体管与导线。经由尺寸的微缩，晶体管的效能与密度都能获得改善得以如前述般增进IC的效能与功能性。然而，将晶体管彼此互联的导线(互连结构)却会因尺寸微缩的关系而劣化。因此在现今的IC电路中是导线对于IC的效能、功能性以及功耗有主要的影响。
为增进功能密度，半导体装置中常常整合有逻辑电路与内嵌式静态随机存取存储单元(static random-access memory,SRAM)，这类的应用遍及工业与科研用的子系统、车用电子、移动电话、数码相机、以及微处理器等等。SRAM具有不需刷新即可保存数据的优点，其单元中会含有不同数目的晶体管，通常被称为晶体管数目，如六晶体管(6T)SRAM、八晶体管(8T)SRAM等。这些晶体管一般会构成数据栓锁来存储一个位数据。其他的晶体管则可加入来控制该些晶体管的存取。SRAM单元通常会排列成具有多个行与列的阵列型态。每列SRAM单元都连接到一字符线，其会决定是否选择当前的SRAM单元。每行SRAM单元都连接到一位线(或是一对互补的位线)，其是用来将位数据写入或从SRAM单元中读取数据。
仅靠尺寸微缩的动作已无法满足SRAM的高密度需求。举例言之，传统平面式晶体管的SRAM单元结构在半导体尺寸小到一定程度以下会出现效能劣化以及漏电等问题。为了克服此难题，业界提出了鳍式或多鳍式的三维晶体管架构，亦即鳍式场效晶体管(FinFETs)。鳍式场效晶体管应用在金属氧化物半场效晶体管结构中可以有效控制其短通道效应。为了要达到最佳的控制并缩减面积，一般会希望鳍状结构能越薄越好，制作这类超薄型态的鳍状结构的其中一方法就是间隙壁光刻制作工艺，其作法为在心轴(mandrel)图形的侧壁上形成间隙壁，之后将心轴图形移除后该间隙壁就可作为硅基板蚀刻制作工艺中的蚀刻掩模。心轴图形与间隙壁的尺寸将会决定鳍状结构的宽度与节距。对于该些心轴图形与间隙壁的关键尺寸的一致度上的控制是对于内嵌式FinFET SRAM设计的一大挑战。
近来在FinFET晶体管技术方面的进程已得以制作出高阶的FinFET SRAM单元。然而先进半导体科技中所需要的极小特征尺寸仍然容易诱发装置的漏电问题。举例言之，在附近有虚置单元或浮置栅状态的字符线的设计下，SRAM中的位单元产生次临界漏电流的问题。此时电流会因为邻近的虚置字符线没有完全关闭的缘故从位单元流向虚置单元。为因应现今对于更小型电子装置的需求，如何解决这类半导体漏电流问题变得更重要且迫切。
发明内容
本发明的其中一目的在于提出一种静态随机存取存储元件(SRAM)，其在使用虚置图形减轻微负载效应的情况下能更抵抗漏电损，且可在不影响现有的布局设计与制作工艺规划的前提下借着加入对应的虚置图形来进一步改善图形的一致度。
为了达到上述目的，本发明的一实施例中提出了一种SRAM元件，其包含一基底、一存储单元设置在该基底上，其中该存储单元含有两个作为载入晶体管的P通道栅极、两个作为驱动晶体管的N通道栅极、以及两个作为存取晶体管的N通道栅极，还包含至少一虚置栅极邻近该作为存取晶体管的N通道栅极，其中该虚置栅极与邻近该虚置栅极的N通道栅极都跨过一主动区域。一位线节点设置在该虚置栅极以及邻近该虚置栅极的N通道栅极之间，其中该位线节点电连接到该主动区域。一金属层电连接至该虚置栅极，而该虚置栅极经由该金属层电连接至一接地电压。
为了达到上述目的，本发明的另一实施例中提出了一种SRAM元件，其包含一基底、一存储单元设置在该基底上，其中该存储单元含有两个作为载入晶体管的P通道栅极、两个作为驱动晶体管的N通道栅极、以及两个作为存取晶体管的N通道栅极，还包含至少一虚置栅极邻近该作为存取晶体管的N通道栅极，其中该虚置栅极与邻近该虚置栅极的N通道栅极都跨过一主动区域。一位线节点设置在该虚置栅极以及邻近该虚置栅极的N通道栅极之间，其中该位线节点是电连接到该主动区域。基底上设有一接载(pick-up)阱区邻近该虚置栅极，且一接载电力线电连接该接载阱区，其中该接载电力线延伸至该虚置栅极上并与之电连接，而该虚置栅极经由该接载电力线电连接至一接地电压。
本发明的SRAM元件具有一经由金属线接地而完全关闭的虚置栅极。如此，邻近该虚置栅极的位线不会再因被该虚置栅极拉降(pull down)而引发次临界漏电流问题，进而避免SRAM的位线失效的情形发生。
无疑地，本发明的这类目的与其他目的在阅者读过下文以多种图示与绘图来描述的优选实施例细节说明后将变得更为显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些图示描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些图示中：
图1为一静态随机存取存储单元(SRAM)的电路图；
图2为本发明实施例一静态随机存取存储单元的布局图；
图3为本发明实施例一静态随机存取存储单元的布局图，其中包含了层间介电层与第一金属层的布局图形；
图4为以图3中截线A-A’所做的截面图；以及
图5为一静态随机存取存储单元的布局图综览，其中包含了主动层(OD)的导体图形分布。
需注意本说明书中的所有图示都为图例性质，为了清楚与方便图示说明之故，图示中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
符号说明
100 SRAM单元
102,104 位线节点
110,112 数据节点
110a OD层接触插塞
110b 栅极接触插塞
114,116 Vdd节点
118,120 Vss节点
122 栅电极
124 主动区域
126 主动区域
128 栅电极
130 栅电极
132 主动区域
138,140 虚置栅电极
142 虚置位线节点
144 虚置Vdd节点
146 接载接触插塞
150 Vdd线
152,154,156 导孔
158 接载电力线
160,162 导孔
164 第一导体图形
166 第二导体图形
200 虚置单元
BL,BLB 位线
DG 虚置栅极晶体管
PD-1,PD-2 拉降晶体管
PG-1,PG-2 传送栅晶体管
PU-1,PU-2 拉升晶体管
具体实施方式
下文将要进行本发明实施例的讨论，然而。需了解该些实施例是提出了许多可应用的发明概念，在其所述特定的上下文背景中可据以多种广泛的方式来施行体现。这些所讨论的特定实施例为说明之用，并未限定本发明公开的范畴。
根据本发明数种实施范例，其中提出了一种静态随机存取存储单元(SRAM)，实施例中将讨论其多种变体。通篇图示中会用相同的参考符号来标示修改后或不同实施例中对应或类似的元件特征。
图1中描绘出根据本发明实施例依SRAM单元100的电路图。SRAM单元100含有作为载入晶体管的拉升(pull-up)晶体管PU-1与PU-2，其为P通道金属氧化物半导体(PMOS)晶体管，以及作为存取晶体管的传送栅(pass gate)晶体管PG-1与PG-2以及作为驱动晶体管的拉降(pull-down)晶体管PD-1与PD-2，其为N通道金属氧化物半导体(NMOS)晶体管。传送栅晶体管PG-1与PG-2的栅极是由字符线WL(未示出)来控制的，其决定该SRAM单元100是否被选择。拉升晶体管PU-1与PU-2以及拉降晶体管PD-1与PD-2构成了栓锁来存储位，其中位的互补值分别存储在数据节点110与数据节点112中。被存储的位会经由位线BL或BLB写入或者是从SRAM单元100中读取。SRAM单元100经由具有正电压Vdd的供能节点114,116供压。SRAM单元100也会连接至一供压Vss，其可为一接地端。晶体管PU-1与PD-1构成了一第一反向器，晶体管PU-2与PD-2构成了一第二反向器。第一反向器的输入端是连接至传送栅晶体管PG-1以及第二反向器的输出端，而输出端是连接至传送栅晶体管PG-2以及第二反向器的输入端，形成双栓锁结构。
复参照图1，拉升晶体管PU-1与PU-2的源极端会分别连接至Vdd节点114与Vdd节点116，其复连接至供压(线)Vdd。拉降晶体管PD-1与PD-2的源极端则会分别连接至Vss节点118与Vss节点120，其复连接至供压(线)Vss。晶体管PU-2与PD-2的栅极会连接至晶体管PU-1与PD-1的漏极，此连接点称为数据节点112。传送栅晶体管PG-1的源/漏极会连接至位线BL的位线节点102处，传送栅晶体管PG-2的源/漏极会连接至位线BLB的位线节点104处。
图2是绘示出\根据本发明实施范例一SRAM单元100的布局。在某些实施例中，此布局是以图形数据系统(Graphic Database System,GDS)的格式存在，且其可以有形的非暂态存储媒介如硬盘的方式来体现。此布局可通过电脑来存取并加以处理。再者，通篇说明中所描绘的布局可以透光或不透光图形的形式形成在光刻光掩模上，此光刻光掩模会用于光致抗蚀剂曝光，如此说明中所描绘的特征图形会形成具有实体的特征图形(形状)。故此，本发明中的每个布局也可代表了多个含有所示特征图形的光刻光掩模。
在实施例中，为了简明之故，图2并没有完整地表示出SRAM单元100的所有布局，SRAM单元100中只有一半的部件，即组成单一反向器的一传送栅晶体管PG-1、一拉降晶体管PD-1以及一拉升晶体管PU-1在图中有绘示出。这些部位应已足够让本领域的一般技术人员了解并据以实施本发明。此外，图中还示有一边缘单元(后文中将称为虚置单元)200邻近SRAM单元100。在半导体领域中，此虚置单元200通常会设置在SRAM阵列与周边区域之间，作为一虚置区域来对付微负载效应(micro loading effect)的问题。SRAM单元100与虚置单元200的外边界会使用虚线来表示，如图中的长方形所示。
请参照图2，图中也有示出Vdd节点114、Vdd节点116、Vss节点118、位线节点102与104等部件。栅电极122与下方的主动区域(n型阱区域，可为鳍式)1构成了一拉升晶体管PU-1。栅电极122还与另一下方的主动区域(p型阱区域，可为鳍式)126构成了一拉降晶体管PD-1。栅电极128与下方的主动区域126则构成了一传送栅晶体管PG-1。栅电极130与下方的主动区域(n型阱区域，可为鳍式)132则构成了一拉升晶体管PU-2。根据本发明实施例，晶体管PG-1,PU-1,PU-2以及PD-1可为鳍式场效晶体管(Fin Field-Effect Transistors)。
如图2所示，数据节点110含有一OD层(主动区层)接触插塞110a以及栅极接触插塞110b。OD层接触插塞110a的长轴方向为Y方向，其与栅电极122,128,130的延伸方向平行。OD层接触插塞110a的两端会分别延伸至主动区域124与主动区域(漏极区)126的上方并与之电连接。栅极接触插塞110b有一部分位于栅电极130上方并与之电连接。在实施例中，栅极接触插塞110b的长轴方向为X方向。
再者，栅极接触插塞110b会与OD层接触插塞110a的一端重叠。故此，当图2的布局在实体的半导体芯片上的SRAM单元中实作时，栅极接触插塞110b会与OD层接触插塞110a结合形成一数据节点110，其可使用相同的金属填充制作工艺来形成一整合连续的数据节点110。图2上半部SRAM单元100的另一数据节点112具有与数据节点110完全相同的组态，为简明之故，其相关的说明文中不再多予赘述。
复参照图2。在SRAM单元100设置在存储阵列最外围区域的情况下，栅电极128,130或位线节点102与Vdd节点116等靠近单元边界的布局图形会受到微负载效应的影响，其会产生不正常的图案而严重影响到存储元件的电性。为了解决此问题，最外围的SRAM单元100以及周边区域(未示出)之间通常会设置虚置单元，以提供虚置图形来补偿微负载效应。
如图2所示，实施例中有数个虚置图形是设置来补偿微负载效应的，其中虚置栅电极138与虚置栅电极140是设置在靠近SRAM单元100的虚置单元200边缘。虚置栅电极138与栅电极128是设置成以位线节点102为中心对称，而虚置栅电极140与栅电极130是设置成以Vdd节点116为中心对称。虚置位线节点142与位线节点102是设置成以虚置栅电极138为中心对称，而虚置Vdd节点144与Vdd节点116设置成以虚置栅电极140为中心对称。需注意虚置栅电极138与栅电极128一样都跨过同个主动区域126并形成一虚置栅极晶体管DG。此外，在本发明一实施例中，虚置单元200也可能会提供一区域作为接载(pick-up)区域。虚置位线节点142的附近可设置一接载接触插塞146来经由接载电力线在下层的接载阱区(P型阱)以及接地电压或共同电压Vss之间提供电力连接。或者，在其他实施例中，虚置单元200也可能设置在存储阵列之中，而非介于存储阵列和周边区域之间。举例言之，虚置单元可作为两组存储单元之间的间隔单元，来提供接载电力或是补偿虚置图形。
图3绘示出根据本发明实施例一SRAM单元的布局，其中包含了层间介电层(ILD)与第一金属层(M1)的布局图形。M1层形成有位线BL与Vdd线150，其呈X方向走向穿过SRAM单元100以及虚置单元200并与主动区域124,126平行。在一连接机制范例中，位线连接至下层的导孔152，其复连接至下层的位线节点102。Vdd线150连接至下层的导孔154,156，其复分别连接至下层的Vdd节点114与Vdd节点116，以提供供压Vdd。Vdd节点114还会提供供压Vdd到主动区域124、数据节点110以及传送栅晶体管PG-1与拉降晶体管PD-1之间的主动区域126。SRAM中另一由Vdd节点116与数据节点112组成的反向器具有相同的运作方式，为了简明之故，其相关说明将不再多予赘述。
就现有的连接机制来说，邻近传送栅晶体管PG-1的虚置栅极晶体管DG不会连接任何电压或电力线，而在浮置状态下关闭。然而在此状态下位线节点102与邻近的虚置位线节点142之间仍然容易因为浮置状态下的虚置栅极晶体管DG未完全关闭之故诱发出漏电路径。在此状态下位线节点102会受到虚置栅极晶体管DG的拉降而导致SRAM位线失效问题。
为了解决这样的漏电问题，请参照图3，本发明中提出了在M1层中形成接载电力线158从接载区域延伸至虚置栅电极138处。此接载电力线158与位线BL以及Vdd线150相同呈X方向走向而与主动区域124与126平行。在一连接机制范例中，接载电力线158连接至下层的导孔160与162，其复分别连接至下方OD层中的接载接触插塞146与虚置栅电极138。由于接载接触插塞146是通过其他金属层的电力线与一接地电压或是一共同电压Vss连接，与该接载接触插塞146连接的虚置栅电极138也会被电连接至接地电压或共同电压Vss，如此，虚置栅极晶体管DG会被接地并完全关闭，不会再有电流从位线节点102端流到虚置位线节点142，因而解决了SRAM位线失效问题。或者，在其他实施例方面，虚置栅极晶体管DG也可以经由其他金属线接地或接共同电压，并没有限定一定要使用接载电力线158。
此外，实施例中还提出一个额外的第一导体图形164设置在OD层中的虚置栅电极138上，其中该第一导体图形164与栅电极128上的一常规的第二导体图形166以位线节点102为中心对称。如图4所示，其描绘出一SRAM单元的布局综览，其中具有OD层中的导体图形分布。在实施例中，M0层的图形可包含数据节点110的栅极接触插塞110b、虚置电极上的第一导体图形164以极栅电极上的第二导体图形166，其中第一导体图形164与第二导体图形166如同栅极接触插塞110b般作为栅极接触来与其上Via_0层的导孔连接。在实施例中，此位于虚置栅电极上的额外第一导体图形164不仅可作为一接触插塞来连接导孔，也有助于补偿M0层的图形，使该层的布局更为均匀一致。
图5为以图3中截线A-A’所作的截面示意图，其中的层结构都是形成在一半导体基底或是晶片10上。需注意图5仅是示意性地描绘出多层的互连结构与其中的晶体管，其可能未完全反映出SRAM单元100与虚置单元200中真实的截面态样。图中的互连结构包含一OD层(OD代表主动区域)、一导孔层Via_0、以及一金属层M1，其中M0层包含在OD层中。图中的每一层都含有一或多层的介电层或是形成于其中的导体结构特征。位于同层的导体结构特征可能会有彼此齐平的顶面与底面，并且可能同时形成。OD层是将晶体管的栅电极(如所绘示的晶体管范例DG,PG-1,PD-1以及PU-1等)连接至上方的Via_0等层。OD层也会将晶体管的源/漏极区与接载阱区等区域连接至上方的Via_0等层。
从图5中可以看出，接载接触插塞146会与基底10上的接载阱区106接触，复经由导孔160连接至上方的接载电力线158。此接载电力线158会通过其他金属层的电力线与一接地电压或是一共同电压Vss连接，达成其接载(pick-up)功效。接载电力线158复会延伸至虚置栅电极138上方，并经由导孔162与第一导体图形164来与之电连接，以提供接地电压或是共同电压Vss到虚置栅极晶体管DG。如此，虚置栅极晶体管DG会被接地并完全关闭，不会再有电流从位线节点经由主动区流到虚置位线节点处。
在实施例中，位线与带有Vss供压的Vss线(未示出)可设置在M2层并呈现与位线BL与Vdd线150垂直的Y方向走向。在一连接机制范例中，位线经由导孔连接至下方OD层中的传送栅晶体管PG-1与PG-2，Vss线则连接至下方OD层中的导孔，其复连接至主动区域126部位，该主动区域部位可作为图2中拉降晶体管PD-1的源极。由于本发明中字符线与Vss线的布局与连接为半导体领域的现有技术，为了简明之故，其相关的组态与图示文中将不再多予赘述，避免模糊了本发明的重点。
根据上述公开，本发明提出了一种静态随机存取存储元件，其在使用虚置图形减轻微负载效应的情况下能更抵抗漏电损，且可在不影响现有的布局设计与制作工艺规划的前提下借着在M0层加入对应的虚置图形以及接触图形来进一步改善图形的一致度。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种静态随机存取存储元件，包含：
基底；
存储单元，位于该基底上，其中该存储单元包含两个作为载入晶体管的P通道栅极、两个作为驱动晶体管的N通道栅极、以及两个作为存取晶体管的N通道栅极；
至少一虚置栅极，位于该基底上并邻近该作为存取晶体管的N通道栅极，其中该虚置栅极与该作为存取晶体管的N通道栅极跨过同一主动区域；
位线节点，位于该虚置栅极与该作为存取晶体管的N通道栅极之间，其中该位线节点电连接至该主动区域；以及
金属层，电连接至该虚置栅极，其中该虚置栅极经由该金属层电连接至一接地电压。
2.如权利要求1所述的静态随机存取存储元件，还包含第一导体图形与第二导体图形，分别位于该虚置栅极与该作为存取晶体管的N通道栅极上，其中该第一导体图形与第二导体图形是以该位线节点为中心对称。
3.如权利要求2所述的静态随机存取存储元件，还包含导孔，电连接该第一导体图形与该金属层。
4.如权利要求1所述的静态随机存取存储元件，其中该虚置栅极与该作为存取晶体管的N通道栅极是以该位线节点为中心对称。
5.如权利要求1所述的静态随机存取存储元件，还包含虚置位线节点，该虚置位线节点与该位线节点以该虚置栅极为中心对称，其中该虚置位线节点电连接至该主动区域。
6.如权利要求5所述的静态随机存取存储元件，其中该虚置栅极以及该虚置位线节点位于邻近该存储单元的一虚置单元中。
7.如权利要求1所述的静态随机存取存储元件，其中该作为存取晶体管的N通道栅极电连接至一字符线。
8.如权利要求1所述的静态随机存取存储元件，其中该作为载入晶体管的P通道栅极是一拉升栅(pull-up gate)，该作为驱动晶体管的N通道栅极是一拉降栅(pull-down gate)，该作为存取晶体管的N通道栅极是一传送栅(pass gate)。
9.一种静态随机存取存储元件，包含：
基底；
存储单元，位于该基底上，其中该存储单元包含两个作为载入晶体管的P通道栅极、两个作为驱动晶体管的N通道栅极、以及两个作为存取晶体管的N通道栅极；
至少一虚置栅极，位于该基底上并邻近该作为存取晶体管的N通道栅极，其中该虚置栅极与该作为存取晶体管的N通道栅极跨过同一主动区域；
位线节点，位于该虚置栅极与该作为存取晶体管的N通道栅极之间，其中该位线节点电连接至该主动区域；
接载(pick-up)阱区，位于该基底上且邻近该虚置栅极；以及
接载电力线，电连接至该接载阱区，其中该接载电力线延伸到该虚置栅极上并与该虚置栅极电连接，且该虚置栅极经由该接载电力线电连接至一接地电压。
10.如权利要求9所述的静态随机存取存储元件，其中该接载阱区是一P型阱区域。
11.如权利要求10所述的静态随机存取存储元件，还包含第一导体图形与第二导体图形，分别位于该虚置栅极与该作为存取晶体管的N通道栅极上，其中该第一导体图形与第二导体图形是以该位线节点为中心对称。
12.如权利要求11所述的静态随机存取存储元件，还包含导孔，电连接该第一导体图形与该接载电力线。
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