CN103811430A - 层叠封装结构及其形成方法 - Google Patents

层叠封装结构及其形成方法 Download PDF

Info

Publication number
CN103811430A
CN103811430A CN201310250366.XA CN201310250366A CN103811430A CN 103811430 A CN103811430 A CN 103811430A CN 201310250366 A CN201310250366 A CN 201310250366A CN 103811430 A CN103811430 A CN 103811430A
Authority
CN
China
Prior art keywords
tube core
substrate
group
package
potted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310250366.XA
Other languages
English (en)
Other versions
CN103811430B (zh
Inventor
陈孟泽
黄贵伟
蔡再宗
洪艾蒂
郑明达
刘重希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103811430A publication Critical patent/CN103811430A/zh
Application granted granted Critical
Publication of CN103811430B publication Critical patent/CN103811430B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种半导体器件包括第一封装元件和第二封装元件。第一封装元件具有形成在第一衬底上的第一管芯。第二封装元件具有在形成第二衬底上的第二管芯。热隔离材料附接至第一管芯，其中，热隔离材料使第二管芯与第一管芯热绝缘，并且热隔离材料的热导率在约0.024W/mK至约0.2W/mK的范围内。第一组导电元件将第一封装元件耦合至第二封装元件。本发明还提出了层叠封装件及其形成方法。

Description

层叠封装结构及其形成方法
技术领域
本发明一般地涉及半导体技术领域，更具体地，涉及层叠封装件及其形成方法。
背景技术
层叠封装件(POP)由于其允许更高密度的电子器件而成为越来越受欢迎的集成电路封装技术。
传统的层叠封装结构可以包括底部封装元件和顶部封装元件。底部封装元件可以包括附接至底部衬底的底部管芯，而顶部封装元件可以包括附接至顶部衬底的顶部管芯。通常通过诸如焊球的导电元件组将底部封装元件耦合至顶部封装元件。在运行中，两个封装元件都产生热量。然而由底部管芯产生的多余热量会损害顶部管芯，尤其是在底部管芯为器件管芯的情况下。热量也可能导致层叠封装结构中的热应力和翘曲从而导致焊球破裂。即使在层叠封装结构中使用模塑料，也不能完全消除多余热量和翘曲的问题。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：第一封装元件，具有形成在第一衬底上的第一管芯；第二封装元件，具有形成在第二衬底上的第二管芯；第一组导电元件，将所述第一封装元件耦合至所述第二封装元件；以及热隔离材料，处于所述第一封装元件和所述第二封装元件之间。
该半导体器件还包括：第二组导电元件，将所述第一管芯耦合至所述第一衬底；以及第三组导电元件，将所述第二管芯耦合至所述第二衬底。
在该半导体器件中，所述第三组导电元件包括接合引线。
该半导体器件还包括模塑料，所述模塑料模制在所述第一衬底上并环绕所述第一管芯、所述第一组导电元件和所述第二组导电元件，并且所述模塑料还模制在所述第二衬底上并环绕所述第二管芯和所述第三组导电元件。
在该半导体器件中，所述第一管芯是逻辑芯片。
在该半导体器件中，所述第二管芯是存储芯片。
在该半导体器件中，所述热隔离材料是其中具有空气或真空的密封环。
在该半导体器件中，所述热隔离材料包括选自由蜡、管芯附接膜(DAF)、气凝胶、胶带、热界面材料(TIM)和粘合剂所组成的组的材料。
在该半导体器件中，所述热隔离材料的厚度在约10微米至约100微米的范围内。
在该半导体器件中，所述热隔离材料是具有约0.024W/mK至约0.2W/mK的热导率的材料。
根据本发明的另一方面，提供了一种层叠封装件，包括：底部封装元件，具有形成在底部衬底上的至少一个底部管芯；顶部封装元件，具有形成在顶部衬底上的至少一个顶部管芯；热隔离材料，附接至所述底部管芯，其中，所述热隔离材料的热导率在约0.024W/mK至约0.2W/mK的范围内；以及第一组导电元件，将所述底部衬底耦合至所述顶部衬底。
该层叠封装件还包括：第二组导电元件，将所述至少一个底部管芯耦合至所述底部衬底；以及第三组导电元件，将所述至少一个顶部管芯耦合至所述顶部衬底。
该层叠封装件还包括模塑料，所述模塑料模制在所述底部衬底上并环绕所述底部管芯、所述第一组导电元件和所述第二组导电元件，并且所述模塑料还模制在所述顶部衬底上并环绕所述顶部管芯和所述第三组导电元件。
在该层叠封装件中，所述热隔离材料是其中具有空气或真空的密封环。
在该层叠封装件中，所述热隔离材料包括选自由蜡、管芯附接膜(DAF)、气凝胶、胶带、热界面材料(TIM)和粘合剂所组成的组的材料。
在该层叠封装件中，所述热隔离材料的厚度在约10微米至约100微米的范围内。
该层叠封装件还包括环绕第二组导电元件和第三组导电元件的底部填充物。
根据本发明的又一方面，提供了一种形成封装件的方法，包括提供第一封装元件，所述第一封装元件具有形成在第一衬底上的第一管芯；提供第二封装元件，所述第二封装元件具有形成在第二衬底上的第二管芯；将热隔离材料附接至所述第一管芯，所述热隔离材料基本使所述第二管芯与所述第一管芯热绝缘；以及通过第一组导电元件将所述第一封装元件耦合至所述第二封装元件。
该方法还包括：通过第二组导电元件将所述第一管芯耦合至所述第一衬底；以及通过第三组导电元件将所述第二管芯耦合至所述第二衬底。
该方法还包括：在所述第一封装元件和所述第二封装元件上方形成模塑料。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有按比例绘制。实际上，为了清楚讨论起见，各种部件的尺寸可以被任意增大或缩小。
图1是根据本发明的各个实施例的制造层叠封装结构的方法的流程图。
图2至图6是根据本发明的各个实施例的处于制造层叠封装结构的各个中间阶段的顶部封装件和/或底部封装件的截面图。
具体实施方式
在以下描述中，阐述了许多特定的细节以提供本发明的实施例的完全理解。然而，本领域的普通技术人员应意识到没有这些特定的细节也可实施本发明的实施例。在一些实例中，没有详细描述公知的结构和工艺从而避免了本发明的不必要的模糊的实施例。
整个本说明书中引用“一个实施例”或“某个实施例”意味着本发明的至少一个实施例包括关于所述实施例而描述的特定部件、结构或特征。因此在本说明书的各个位置出现的短语“在一个实施中”或“在某个实施例中”不一定都指同一个实施例。而且，在一个或多个实施例中可以以任何合适的方式组合特定部件、结构或特征。应理解，以下附图没有按比例绘制；而这些附图只是为了阐明。
图1是根据本发明的各个方面制造层叠封装件的方法100的流程图。参考图1，方法包括框110，其中，提供了第一封装元件，该第一封装元件具有形成在第一衬底上的第一管芯。方法100包括框120，其中，提供第二封装元件，该第二封装元件具有形成在第二衬底上的第二管芯。方法100包括框130，其中，热隔离材料附接至第一管芯。该热隔离材料使第二管芯与第一管芯基本上热绝缘。方法100包括框140，其中，第一封装元件通过导电元件组与第二封装元件耦合。
应该理解，可以在图1所示的框110至140之前、期间或之后实施其他工艺以完成层叠封装结构的制造，但是为了简明，本文不详细讨论这些其他工艺。
图2至图6是根据图1的方法100的实施例处于制造层叠封装结构的各个制造阶段的顶部封装件和/或底部封装件的示意性部分截面侧视图。应该理解，为了更好地理解本发明的发明构思已经简化了图2至图6。应该认识到，本文描述的材料、几何形状、尺寸、结构和工艺参数仅仅是示例性的，并不意图和不应该被解释为限制本文要求保护的发明。许多选择和改变对于知晓本发明的本领域的那些技术人员来说是显而易见的。
将参考图2至图6讨论层叠封装结构的实施例。图2示出在层叠封装结构中使用的顶部封装件1。可以利用塑料球栅阵列(PBGA)封装件组装工艺等形成顶部封装件1，该顶部封装件1包括多个堆叠管芯2，该多个堆叠管芯2可以通过接触件16(位于相应的堆叠管芯2上)、接合引线6和接触件12(位于顶部衬底10上)引线接合至顶部衬底10。独立堆叠管芯可以包括存储芯片、逻辑芯片、处理器芯片等。尽管图2示出三个堆叠管芯，但这仅是为了说明。同样地，引线接合的使用仅仅是示例性的，而且电连接堆叠管芯的其他方法在本发明的预期范围内。例如，也可以预期使用焊料凸块、焊球、铜柱、导电凸块、焊料保护件(solder cap)、导电柱、导电球、凸块底部金属化层和/或其他连接元件以将堆叠管芯2连接至顶部衬底10。在一些实施例中，底部填充物(未示出)分配在堆叠管芯2和顶部衬底10之间的间隙中，从而加强层叠封装结构的强度。
顶部衬底10可以是由非导电聚合物层(诸如双马来酰亚胺三嗪(BT))和图案化的(或非图案化的)导电层的交替层所组成的层压电路板。如上所述，顶部衬底10具有位于第一面(为了方便，有时在本文中称为顶面)上的用于电连接至堆叠管芯2的接触件12。顶部衬底10还具有位于第二面(为了方便，有时在本文中称为底面)上的用于电连接至以下将要详述的其他元件的底部接触件24。焊球36附接至衬底10的底部接触件24。焊球36允许顶部封装件1和底部封装件34(在图2中未示出，但在图3和图4中示出)之间的电连接和/或热连接。在所示的实施例中，焊球36为堆叠管芯2提供信号和功率的电传导。此外，可以使用诸如导电凸块、导电球、导电柱等的其他连接元件代替焊球36。
在一些实施例中，对顶部封装件1施加模塑料35从而提供机械刚度和提高层叠封装结构的机械强度。应该相信，该机械刚度防止或至少降低例如由所得到的封装件的元件之间的热膨胀失配而导致的翘曲的严重程度。可以使用例如压塑成型或转印成型在衬底10上模制模塑料35并使模塑料35环绕堆叠管芯2和接合引线6。然后，可以实施固化步骤以使模塑料35凝固。模塑料35可以包括基于聚合物的材料、底部填充物、模制底部填充物(MUF)、环氧树脂等。
如图5所示，顶部封装件1通过焊球36附接至底部封装件34。如图3所示，底部封装件34包括管芯37，管芯37是附接至底部衬底38的倒装芯片，并且管芯37通过连接元件39电连接至底部衬底38。管芯37可以包括逻辑芯片、处理器芯片、存储芯片等。例如，连接元件39可以包括焊料凸块、焊球、铜柱、导电凸块、焊料保护件、导电柱、导电球和凸块底部金属化层。在一些实施例中，底部填充物(未示出)分配在管芯37和底部衬底38之间的间隙中从而加强层叠封装结构的强度。通过与底部衬底38一面上的连接元件39和底部衬底38的另一面上的连接元件42对准的通孔(未示出)来提供管芯37和下面的主板或其他电路(未示出)之间的电连接。同样地，通过焊球36、通孔和连接元件42来提供顶部衬底10和下面的主板或其他电路的电连接。
在运行中，分别包括管芯37和堆叠管芯2的底部封装件34和顶部封装件1都产生热量。管芯37(尤其是在底部管芯是处理器管芯的情况下)产生的热量会损害顶部管芯或堆叠管芯2。热量也可能导致层叠封装结构中的热应力和翘曲从而导致诸如焊球的连接元件破裂。如图3所示，本发明的层叠封装结构的优点是底部封装件34的附接至管芯37之上并使堆叠管芯2与管芯37所产生的热量热绝缘的热隔离材料50。在一个实施例中，因为由于热隔离材料50，顶部封装件1和底部封装件34与热绝缘，所以其他优点是更好地控制层叠封装结构中的翘曲。换句话说，热隔离材料50阻止了作为顶部封装件1和底部封装件34之间的热膨胀系数(CTE)失配的结果可能发生的翘曲。
在一些实施例中，热隔离材料50是热导率为约0.024W/mK至约0.2W/mK的材料。热隔离材料50可以包括多孔膜、蜡膜、管芯附接膜(DAF)、气凝胶、胶带、热界面材料(TIM)或粘合剂。在热隔离材料50是TIM的情况下，TIM可以包括焊膏、粘合剂或热脂。在一些实施例中，热隔离材料50的厚度在约10微米至约100微米的范围内。图5示出层叠封装结构中的热隔离材料50，其中底部封装件34附接至顶部封装件1。
在其他实施例中，如图4和图6所示热隔离材料50是在其中具有空气或真空77的密封环55，该密封环55位于底部封装件34附接至顶部封装件1的层叠封装结构中。空气或真空在正常运行条件下是理想热绝缘体。在其他实施例中，密封环55提供约0W/mK的热导率。密封环50分配在管芯37上，以在以下将要阐述的模制工艺期间提供真空间隙。
在一些实施例中，在对管芯37施加热隔离材料50或密封环55之后，对底部封装件34施加模塑料35，以提供机械刚度和提高层叠封装结构的机械强度。可以使用例如压塑成型或转印成型在衬底38上模制模塑料35并使模塑料35环绕管芯37和连接元件39。然后可以执行固化步骤从而使模塑料35凝固。模塑料35可以包括基于聚合物的材料、底部填充物剂、模制底部填充物(MUF)、环氧树脂等。再参考图4，为了形成空气或真空77，环绕密封环55形成模塑料35从而在其中封装空气或真空77。
图2至图6示出的层叠封装结构仅是为了说明的目的并不用于限制。可以考虑其他的实施例。
本发明的一个或多个实施例的优点可以包括以下优点中的一个或多个。
在一个或多个实施例中，在包括具有顶部管芯的顶部封装件和具有底部管芯的底部封装件的层叠封装结构中，顶部管芯基本上与底部管芯所产生的热量绝缘。
在一个或多个实施例中，由于顶部封装件和底部封装件基本上与热绝缘，所以更好地控制层叠封装结构中的翘曲。
本发明已经描述了各个示例性实施例。根据一个实施例，半导体器件包括第一封装元件和第二封装元件。第一封装元件具有在第一衬底上形成的第一管芯。第二封装元件具有在第二衬底上形成的第二管芯。第一组导电元件将第一封装元件耦合至第二封装元件。热隔离材料被施加在第一管芯上并处于第一封装元件和第二封装元件之间，其中热隔离材料使第二管芯与第一管芯热绝缘。在一些实施例中，热隔离材料包括密封环和气隙。
根据另一个实施例，层叠封装件包括底部封装元件和顶部封装元件。底部封装元件至少具有形成在底部衬底上的底部管芯。顶部封装元件至少具有形成在顶部衬底上的顶部管芯。热隔离材料附接至底部管芯，其中，热隔离材料使顶部管芯与底部管芯热绝缘。热隔离材料的热导率在约0.024W/mK至约0.2W/mK的范围内。第一组导电元件将底部衬底耦合至顶部衬底。在一些实施例中，热隔离材料包括密封环和气隙。
根据又一个实施例，公开了形成封装件的方法。提供了第一封装元件，该第一封装元件具有形成在第一衬底上的第一管芯。提供了第二封装元件，该第二封装元件具有形成在第二衬底上的第二管芯。热隔离材料附接至第一管芯，其中，热隔离材料使第二管芯与第一管芯热绝缘。第一封装元件通过第一组导电元件耦合至第二封装元件。在一些实施例中，热隔离材料包括密封环和气隙。
在以上详细的描述中，已经描述了具体的示例性实施例。然而，对于本领域普通技术人员来说，很明显在不背离本发明的宽泛主旨和范围的情况下，可以对本发明作出各种更改、结构、工艺和改变。因此，说明书和附图是为了说明而不用于限定。据了解本发明的实施例可以使用各种其它组合和环境且可以在权利要求的范围内进行改变或更改。

Claims (10)

1.一种半导体器件，包括：
第一封装元件，具有形成在第一衬底上的第一管芯；
第二封装元件，具有形成在第二衬底上的第二管芯；
第一组导电元件，将所述第一封装元件耦合至所述第二封装元件；以及
热隔离材料，处于所述第一封装元件和所述第二封装元件之间。
2.根据权利要求1所述的半导体器件，还包括：
第二组导电元件，将所述第一管芯耦合至所述第一衬底；以及
第三组导电元件，将所述第二管芯耦合至所述第二衬底。
3.根据权利要求2所述的半导体器件，其中，所述第三组导电元件包括接合引线。
4.根据权利要求2所述的半导体器件，还包括模塑料，所述模塑料模制在所述第一衬底上并环绕所述第一管芯、所述第一组导电元件和所述第二组导电元件，并且所述模塑料还模制在所述第二衬底上并环绕所述第二管芯和所述第三组导电元件。
5.根据权利要求1所述的半导体器件，其中，所述第一管芯是逻辑芯片。
6.根据权利要求1所述的半导体器件，其中，所述第二管芯是存储芯片。
7.根据权利要求1所述的半导体器件，其中，所述热隔离材料是其中具有空气或真空的密封环。
8.根据权利要求1所述的半导体器件，其中，所述热隔离材料包括选自由蜡、管芯附接膜(DAF)、气凝胶、胶带、热界面材料(TIM)和粘合剂所组成的组的材料。
9.一种层叠封装件，包括：
底部封装元件，具有形成在底部衬底上的至少一个底部管芯；
顶部封装元件，具有形成在顶部衬底上的至少一个顶部管芯；
热隔离材料，附接至所述底部管芯，其中，所述热隔离材料的热导率在约0.024W/mK至约0.2W/mK的范围内；以及
第一组导电元件，将所述底部衬底耦合至所述顶部衬底。
10.一种形成封装件的方法，包括
提供第一封装元件，所述第一封装元件具有形成在第一衬底上的第一管芯；
提供第二封装元件，所述第二封装元件具有形成在第二衬底上的第二管芯；
将热隔离材料附接至所述第一管芯，所述热隔离材料基本使所述第二管芯与所述第一管芯热绝缘；以及
通过第一组导电元件将所述第一封装元件耦合至所述第二封装元件。
CN201310250366.XA 2012-11-08 2013-06-21 层叠封装结构及其形成方法 Active CN103811430B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/671,665 US9418971B2 (en) 2012-11-08 2012-11-08 Package-on-package structure including a thermal isolation material and method of forming the same
US13/671,665 2012-11-08

Publications (2)

Publication Number Publication Date
CN103811430A true CN103811430A (zh) 2014-05-21
CN103811430B CN103811430B (zh) 2017-05-03

Family

ID=50621621

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310250366.XA Active CN103811430B (zh) 2012-11-08 2013-06-21 层叠封装结构及其形成方法

Country Status (3)

Country Link
US (4) US9418971B2 (zh)
KR (1) KR101531746B1 (zh)
CN (1) CN103811430B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039369A (zh) * 2015-01-23 2017-08-11 三星半导体(中国)研究开发有限公司 封装、包括该封装的封装堆叠结构及其制造方法
CN108140639A (zh) * 2015-10-02 2018-06-08 高通股份有限公司 包括集成电路(IC)封装之间的间隙控制器的层叠封装(PoP)器件

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9263377B2 (en) * 2012-11-08 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures with dams encircling air gaps and methods for forming the same
CN203026500U (zh) * 2012-12-25 2013-06-26 华为终端有限公司 堆叠封装器件
US8883563B1 (en) * 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) * 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9379097B2 (en) 2014-07-28 2016-06-28 Apple Inc. Fan-out PoP stacking process
US9799626B2 (en) 2014-09-15 2017-10-24 Invensas Corporation Semiconductor packages and other circuit modules with porous and non-porous stabilizing layers
KR102307490B1 (ko) 2014-10-27 2021-10-05 삼성전자주식회사 반도체 패키지
KR102285332B1 (ko) * 2014-11-11 2021-08-04 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 장치
US9589936B2 (en) * 2014-11-20 2017-03-07 Apple Inc. 3D integration of fanout wafer level packages
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10115675B2 (en) * 2016-06-28 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of fabricating a packaged semiconductor device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN108780790B (zh) * 2017-01-04 2020-10-27 华为技术有限公司 一种堆叠封装结构及终端
CN110060961B (zh) * 2018-01-19 2021-07-09 华为技术有限公司 一种晶圆封装器件
WO2020166567A1 (ja) * 2019-02-15 2020-08-20 株式会社村田製作所 電子モジュール及び電子モジュールの製造方法
US11854935B2 (en) * 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias
US11069383B1 (en) 2020-04-06 2021-07-20 Seagate Technology Llc Thermal interface materials for immersion cooled data storage devices
US20220051962A1 (en) * 2020-08-12 2022-02-17 Micron Technology, Inc. Semiconductor device assemblies and systems with internal thermal barriers and methods for making the same
US11830821B2 (en) * 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700467A (zh) * 2004-05-20 2005-11-23 株式会社东芝 半导体器件
CN101261983A (zh) * 2007-03-07 2008-09-10 奥林巴斯映像株式会社 具有摄像元件的半导体装置
US20100110651A1 (en) * 2008-11-06 2010-05-06 International Buisness Machines Corporation Integrated Circuit Coating For Improved Thermal Isolation
CN101869008A (zh) * 2007-12-26 2010-10-20 松下电器产业株式会社 半导体装置和多层配线基板
US20110304015A1 (en) * 2010-06-10 2011-12-15 Samsung Electronics Co., Ltd. Semiconductor package
WO2012058074A2 (en) * 2010-10-28 2012-05-03 Rambus Inc. Thermal isolation in 3d chip stacks using gap structures and contactless communications

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
JP4036694B2 (ja) 2002-03-28 2008-01-23 シャープ株式会社 積層型半導体装置
US8970049B2 (en) 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
US7629695B2 (en) * 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US7492039B2 (en) * 2004-08-19 2009-02-17 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
KR100498708B1 (ko) * 2004-11-08 2005-07-01 옵토팩 주식회사 반도체 소자용 전자패키지 및 그 패키징 방법
US7456088B2 (en) * 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
KR100809701B1 (ko) 2006-09-05 2008-03-06 삼성전자주식회사 칩간 열전달 차단 스페이서를 포함하는 멀티칩 패키지
DE102007040117A1 (de) 2007-08-24 2009-02-26 Robert Bosch Gmbh Verfahren und Motorsteuereinheit zur Aussetzerkennung bei einem Teilmotorbetrieb
KR20120089150A (ko) 2011-02-01 2012-08-09 삼성전자주식회사 패키지 온 패키지
US8503498B2 (en) * 2011-03-23 2013-08-06 Rohm Co., Ltd. Multi-beam semiconductor laser apparatus
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US9728652B2 (en) * 2012-01-25 2017-08-08 Infineon Technologies Ag Sensor device and method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700467A (zh) * 2004-05-20 2005-11-23 株式会社东芝 半导体器件
CN101261983A (zh) * 2007-03-07 2008-09-10 奥林巴斯映像株式会社 具有摄像元件的半导体装置
CN101869008A (zh) * 2007-12-26 2010-10-20 松下电器产业株式会社 半导体装置和多层配线基板
US20100110651A1 (en) * 2008-11-06 2010-05-06 International Buisness Machines Corporation Integrated Circuit Coating For Improved Thermal Isolation
US20110304015A1 (en) * 2010-06-10 2011-12-15 Samsung Electronics Co., Ltd. Semiconductor package
WO2012058074A2 (en) * 2010-10-28 2012-05-03 Rambus Inc. Thermal isolation in 3d chip stacks using gap structures and contactless communications

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039369A (zh) * 2015-01-23 2017-08-11 三星半导体(中国)研究开发有限公司 封装、包括该封装的封装堆叠结构及其制造方法
CN108140639A (zh) * 2015-10-02 2018-06-08 高通股份有限公司 包括集成电路(IC)封装之间的间隙控制器的层叠封装(PoP)器件

Also Published As

Publication number Publication date
US10490539B2 (en) 2019-11-26
US20200020677A1 (en) 2020-01-16
US20160343698A1 (en) 2016-11-24
KR20140059696A (ko) 2014-05-16
US11776945B2 (en) 2023-10-03
KR101531746B1 (ko) 2015-07-06
US9418971B2 (en) 2016-08-16
CN103811430B (zh) 2017-05-03
US20140124955A1 (en) 2014-05-08
US20230378153A1 (en) 2023-11-23

Similar Documents

Publication Publication Date Title
CN103811430A (zh) 层叠封装结构及其形成方法
KR100630741B1 (ko) 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US6462405B1 (en) Semiconductor package
CN103035593B (zh) 封装结构上的封装件及其制造方法
CN103515326A (zh) 具有用于翘曲控制的基于聚合物的材料的堆叠式封装结构
US5783866A (en) Low cost ball grid array device and method of manufacture thereof
CN103633075A (zh) 叠层封装半导体器件
US10475752B2 (en) Semiconductor package structure and method of making the same
KR20090092292A (ko) 회로 다이의 패키징 방법 및 전자 디바이스
TWI681523B (zh) 用於封裝上元件之電路之機械相容的以及導電及導熱的引線架
US20220013471A1 (en) Ic package
CN103915405A (zh) 半导体器件和制造半导体器件的方法
TW202141718A (zh) 半導體模組及其製造方法
CN108878377B (zh) 功率模块及其制作方法以及空调器
JP2003258158A (ja) 半導体装置の製造方法
US9117741B2 (en) Semiconductor device
US20040061243A1 (en) Window-type semiconductor package and fabrication method thereof
US11417581B2 (en) Package structure
CN207602549U (zh) 一种三维芯片堆叠芯片尺寸封装结构
CN100394569C (zh) 防止封装元件溢胶的方法
US20060091567A1 (en) Cavity-down Package and Method for Fabricating the same
KR101697643B1 (ko) 이형필름을 포함하는 반도체 패키지 및 이의 제조방법
CN210926000U (zh) 一种引线框架
KR101708870B1 (ko) 적층형 반도체 패키지 및 이의 제조방법
CN101118861A (zh) 晶片封装结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant