CN103563085B - 垂直隧穿负微分电阻器件 - Google Patents

垂直隧穿负微分电阻器件 Download PDF

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CN103563085B
CN103563085B CN201180071330.4A CN201180071330A CN103563085B CN 103563085 B CN103563085 B CN 103563085B CN 201180071330 A CN201180071330 A CN 201180071330A CN 103563085 B CN103563085 B CN 103563085B
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CN103563085A (zh
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R·皮拉里塞泰
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Intel Corp
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Abstract

本公开内容涉及微电子器件的制造，该微电子器件具有形成在其中的至少一个负微分电阻器件。在至少一个实施例中，可以利用量子阱来形成所述负微分电阻器件。本说明书的负微分电阻器件的实施例可以达到高的峰值驱动电流以实现高性能，并且可以达到高的峰谷电流比以实现低功耗和噪声容限，这允许它们用于逻辑和/或存储器集成电路。

Description

垂直隧穿负微分电阻器件
技术领域
本公开内容总体上涉及可以包括形成在其中的负微分电阻器件的微电子器件的制造。
背景技术
概括地说，本公开内容涉及可以包括形成在其中的负微分电阻器件的微电子器件的制造。
发明内容
根据本公开内容的实施例，一种微电子器件包括：微电子衬底；所述微电子衬底上的缓冲层；所述缓冲层上的底部阻挡层；所述底部阻挡层上的下量子阱；所述下量子阱上的阻挡层；所述阻挡层上的上量子阱；所述上量子阱上的顶部阻挡层；所述顶部阻挡层上的栅极，所述栅极包括栅极电极和位于所述栅极电极与所述顶部阻挡层之间的栅极电介质；上量子阱接触部，其延伸穿过所述顶部阻挡层并且耦合到所述上量子阱；以及下量子阱接触部，其耦合到所述下量子阱，其中，所述下量子阱接触部延伸穿过所述顶部阻挡层、所述上量子阱、以及所述阻挡层，并且其中，所述下量子阱接触部利用电介质材料与所述顶部阻挡层和所述上量子阱电隔离。
根据本公开内容的另一实施例，一种制造微电子器件的方法包括：提供微电子衬底；在所述微电子衬底上形成缓冲层；在所述缓冲层上形成底部阻挡层；在所述底部阻挡层上形成下量子阱；在所述下量子阱上形成阻挡层；在所述阻挡层上形成上量子阱；在所述上量子阱上形成顶部阻挡层；所述顶部阻挡层上形成栅极，包括在所述顶部阻挡层上形成栅极电介质以及在所述栅极电介质上形成栅极电极；形成上量子阱接触部，所述上量子阱接触部延伸穿过所述顶部阻挡层并且耦合到所述上量子阱；以及形成耦合到所述下量子阱的下量子阱接触部，包括：形成穿过所述顶部阻挡层和所述上量子阱的开口部；在所述开口部的侧壁上沉积电介质材料；使所述开口部延伸穿过所述阻挡层，以暴露所述下量子阱的一部分；以及沉积导电材料以填充所述开口部。
附图说明
本公开内容的主题将在说明书的总结部分被特别指出并清楚地要求。从下面的描述和所附的权利要求、并且结合附图，本公开内容的前述及其他特点将得以更加完整体现。应当理解这些附图描述了根据本公开内容的仅仅几个实施例，因此并不能认为是对其范围的限制。将通过使用附图而以附加的特性和细节对本公开内容进行描述，使得可以更容易确定本公开内容的优点，其中：
图1-13示出了根据本说明书的实施例的形成垂直隧穿负微分电阻器件的过程的侧截面示意图。
图14示出了根据本说明书的实施例的电流流过垂直隧穿负微分电阻器件的侧截面示意图。
图15是根据本说明书的实施例的系统的示意图。
具体实施方式
在下面的具体实施方式中，将参考以示例形式示出具体实施例的附图，所要求保护的主题可以在这些实施例中实施。这些实施例被描述得足够详细以让本领域技术人员实施本主题。应当理解，各种实施例虽然互不相同，也不一定互相排斥。例如，这里结合某一实施例所描述的特征、结构或特性可以运用在其他实施例内而不脱离所要求保护的主题的精神和范围。本说明书内所引用的“一个实施例”或“一实施例”意指就该实施例描述的特定的特征、结构或特性包含在本发明所涵盖的至少一个实施方式中。所以，短语“一个实施例”或“在一实施例中”的使用并不必然指向同一个实施例。此外，应当理解在每个所公开的实施例中的个体元件的位置和布置可以在不脱离所要求保护的主题的精神和范围的情况下做出修改。因此，下面的具体实施方式不应理解为具有限制意义，而本主题的范围仅由适当解释的所附权利要求、连同所附权利要求享有权利的等同形式的整个范围所限定。在附图中，相同的附图标记指代所有几个附图中相同的或相似的元件或功能，且其中所描绘的元件并不必须彼此成比例，而为了更易于理解本说明书上下文中的元件，可以放大或缩小个体元件。
在本说明书的各种实施例中，可以利用量子阱来形成负微分电阻器件，其中，这样的器件用于微电子器件应用。负微分电阻是某些电路的特性，其中进入电路的电压的增大可能导致通过同一电路的电流的减小，其中，这个特性表现在电路的工作范围的至少某些部分中。如本领域技术人员将理解的那样，本说明书的负微分电阻器件的实施例可以达到高的峰值驱动电流以实现高性能并且可以达到高的峰谷电流比以实现低功耗和噪声容限。因此，本说明书的实施例可以在逻辑和/或存储器集成电路中使用。
图1是根据本说明书的一个实施例的层叠结构100的截面示意图。层叠结构100可以包括微电子衬底102，例如适当的包含硅的材料。可以在微电子衬底102上形成缓冲层104。在本说明书的一个实施例中，所述缓冲层104可以由砷化镓(GaAs)形成。
应当理解的是，可以在形成缓冲层104之前在微电子衬底102上形成成核层(未示出)，并且所述缓冲层104可以包括多个层。也可以对缓冲层104进行分级(grade)，以提供滑动位错(gliding dislocation)和对微电子衬底102和将形成在缓冲层104之上的底部阻挡层之间的晶格失配的控制。
在形成缓冲层104之后，可以在缓冲层104上形成底部阻挡层106。在一个实施例中，底部阻挡层106可以由具有比将形成在底部阻挡层106上的量子阱的材料更大的带隙的材料形成。在一个实施例中，底部阻挡层106可以包括铟铝砷(InxAl1-xAs)。在另一个实施例中，底部阻挡层106可以被分级。在具体实施例中，底部阻挡层106可以包括铟铝砷(InxAl1- xAs)，其中可以从x等于零到x等于0.52进行分级。因此，在底部阻挡层106和缓冲层104之间的界面处的成分可以以砷化铝(AlAs)开始且可以以在其另一个边界的In0.52Al0.48As结束。在另一个实施例中，底部阻挡层106可以包括铟铝砷(InxAl1-xAs)，其中分级可以是线性的，通过从砷化铝(AlAs)直到达到铟铝砷的成分(例如In0.52Al0.48As)以线性增加的方式在形成期间改变铟的供给。在又一个实施例中，底部阻挡层106可以包括具有非线性分级的铟铝砷(InxAl1-xAs)，其中，可以以非线性地增加的方式提供铟供给以使得底部阻挡层106可以在该底部缓冲层106的物理中点具有大于或小于一半浓度的铟。如本领域技术人员将理解的那样，通过形成底部缓冲层106，位错可以沿着其中的相对对角面滑动。
在形成底部阻挡层106之后，可以在其上形成下量子阱108。在一个实施例中，下量子阱108可以由具有比底部阻挡层106的带隙更小的带隙的材料形成。在一个实施例中，下量子阱108可以从铟镓砷形成。在具体实施例中，下量子阱108可以是铟镓砷，即InxGa1-xAs，其中x在大约0.53和0.8之间。在实施例中，可以对下量子阱108进行掺杂以提高效率。在各种实施例中，可以用p型掺杂剂(例如硼)或n型掺杂剂(例如磷)来对下量子阱108进行掺杂。可以通过本领域任何公知技术来实现对下量子阱108的掺杂。此外，如本领域技术人员将理解的那样，下量子阱108可以被直接掺杂或通过经由随后形成的层或多个层的Δ掺杂(delta doping)进行掺杂。此外，如本领域技术人员将理解的那样，下量子阱108可以被调制掺杂(modulation dope)。
可以在下量子阱108之上形成阻挡层112。在一个实施例中，阻挡层112可以包含铟铝砷，例如InxAl1-xAs。
可以在阻挡层112其上形成上量子阱114。在一个实施例中，上量子阱114可以由铟镓砷形成。在具体实施例中，上量子阱108可以包含铟镓砷，即InxGa1-xAs，其中x在大约0.53和0.8之间。在一个实施例中，可以对上量子阱114进行掺杂以提高效率。在各种实施例中，可以用p型掺杂剂(例如硼)或n型掺杂剂(例如磷)来对上量子阱114进行掺杂。可以通过本领域任何公知技术来实现对上量子阱114的掺杂。此外，如本领域技术人员将理解的那样，上量子阱114可以被直接掺杂或通过经由随后形成的层或多个层的Δ掺杂进行掺杂。此外，如本领域技术人员将理解的那样，上量子阱114可以被调制掺杂。
在一个实施例中，下量子阱108和上量子阱114两者均可以是未掺杂的。在另一个实施例中，下量子阱108和上量子阱114两者均可以是掺杂的。在进一步的实施例中，下量子阱108和上量子阱114中的一个可以是掺杂的，而另一个是未掺杂的。
可以在上量子阱114之上任选地形成顶部阻挡层116。在一个实施例中，顶部阻挡层116可以包含铟铝砷，例如InxAl1-xAs。
应当理解的是，图1所示的层叠结构100仅仅是示例性的，并且如本领域技术人员将理解的那样，为了达到期望的结果，其可以包括多个缓冲层、阻挡层、调制掺杂光晕层(halo layer)、间隔层等。此外，在不偏离本说明书的情况下，可以使用多种材料和系统。进一步应当理解的是，层叠结构100中的各个层可以通过本领域任何公知技术来制造，这些技术包括但不限于：化学气相沉积(“CVD”)、物理气相沉积(“PVD”)、原子层沉积(“ALD”)、分子束外延(MBE)、金属有机化学气相沉积外延(MOCVD epi)、超高真空CVD外延(UHCVD epi)和降低温度的CVD外延(RTCVD epi)。
如图2所示，可以在顶部阻挡层116上对掩模118进行构图。可以通过本领域任何公知技术来形成掩模118，所述技术包括但不限于光刻。然后可以如图3所示那样蚀刻图2的层叠结构100，其中，由掩模118保护的所述层(缓冲层104、底部阻挡层106、下量子阱108、阻挡层112、上量子阱114和顶部阻挡层116)保留下来，从而形成双量子阱堆叠结构120。在本说明书的各个实施例中，所述蚀刻可以选择性地停止在缓冲层104中或缓冲层104上，如图3所示，或者可以选择性地停止在底部阻挡层106上或底部阻挡层106中。
如图4所示，掩模118可以被除去，并且邻接双量子阱堆叠结构120形成电介质材料122。在一个实施例中，电介质材料122可以被均厚沉积在双量子阱堆叠结构120之上，然后被平坦化以具有与顶部阻挡层116的外表面126基本齐平的外表面124。电介质材料122可以包括但不限于：二氧化硅(SiO2)、氮氧化硅(SiOxNy)和氮化硅(Si3N4)。可以通过本领域公知的任何技术来平坦化电介质材料122，这些技术包括但不限于：湿法或干法蚀刻和化学机械抛光。
如图5所示，可以在顶部阻挡层外表面126上形成栅极电极132。如将描述的那样，栅极电极132可以用来调整上量子阱114中的电子密度。在一个实施例中，栅极电介质134可以形成在栅极电极132和顶部阻挡层116之间。栅极电介质134可以是任何适当的电介质材料，包括但不限于高K(高介电常数)材料，例如，氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。如本领域技术人员将理解的那样，可以通过公知的技术来制造栅极电极132和/或栅极电介质134，这些技术例如是化学气相沉积(“CVD”)、物理气相沉积(“PVD”)、原子层沉积(“ALD”)，并且随后用公知的光刻和蚀刻技术来进行构图。
如图6所示，可以邻接栅极电极132的侧面138形成栅极电介质间隔体136。栅极电介质间隔体136可以由任何适当的电介质材料形成，包括但不限于二氧化硅(SiO2)和氮化硅(Si3N4)。如本领域技术人员将理解的那样，可以通过任何公知的技术来制造栅极电介质间隔体136，这些技术包括但不限于共形沉积和随后的蚀刻。
如图7所示，可以在栅极电极132、栅极电介质间隔体136、顶部阻挡层外表面126和电介质材料外表面124之上形成层间电介质142。层间电介质142可以是任何适当的电介质材料，包括但不限于二氧化硅(SiO2)。如本领域技术人员将理解的那样，可以通过任何公知的技术来制造层间电介质142，这些技术包括但不限于沉积和随后的平坦化。
如图8所示，第一开口部144可以形成为穿过层间电介质142和顶部阻挡层116以暴露上量子阱114的部分。可以通过本领域公知的任何技术来形成第一开口部144，这些技术包括但不限于：光刻蚀刻、激光钻孔、离子钻孔、湿法蚀刻、干法蚀刻或它们的任意结合。在一个实施例中，可以使用光刻蚀刻技术，其中，在层间电介质142上对掩模(未示出)进行构图。然后，可以用相对于上量子阱114的材料具有选择性的蚀刻剂通过掩模(未示出)来蚀刻层间电介质142和顶部阻挡层116，以使得蚀刻停止在上量子阱114上或上量子阱114中。
如图9所示，可以在第一开口部144(参见图8)中形成上量子阱接触部146。可以通过本领域中任何公知的技术来形成上量子阱接触部146。在一个实施例中，可以例如通过化学气相沉积(“CVD”)、物理气相沉积(“PVD”)、原子层沉积(“ALD”)等在第一开口部144(参见图8)中和在层间电介质142的外表面148上沉积导电材料。然后可以从层间电介质外表面148除去导电材料的部分，例如通过化学机械抛光或蚀刻从层间电介质外表面148除去导电材料的部分，以形成上量子阱接触部146。导电材料可以包括但不限于：铜、铝、银、钛、金、它们的合金等。
如图10-13所示，然后可以形成下量子阱接触部。如图10所示，可以穿过层间电介质142、顶部阻挡层116和上量子阱114形成第二开口部152。可以通过本领域中公知的任何技术来形成第二开口部152，这些技术包括但不限于：光刻蚀刻、激光钻孔、离子钻孔、湿法蚀刻、干法蚀刻或它们的任意结合。在一个实施例中，可以使用光刻蚀刻技术，其中，在层间电介质142上对掩模(未示出)进行构图。然后，可以用相对于上量子阱114的材料具有选择性的第一蚀刻剂通过掩模(未示出)来蚀刻层间电介质142和顶部阻挡层116，以使得蚀刻停止在上量子阱114上或上量子阱114中。然后可以采用第二蚀刻剂来蚀刻穿过上量子阱114。第二蚀刻剂可以相对于阻挡层112的材料具有选择性，以使得蚀刻停止在阻挡层112上或阻挡层112中。
如图11所示，为了将上量子阱114与随后形成的下量子阱接触部隔离，可以在第二开口部152的侧壁156上形成接触部电介质间隔体154。接触部电介质间隔体154可以由任何适当的电介质材料形成，包括但不限于二氧化硅(SiO2)和氮化硅(Si3N4)。如本领域中技术人员将理解的那样，可以通过任何公知的技术来制造接触部电介质间隔体154，这些技术包括但不限于共形沉积和随后的蚀刻以暴露第二开口部152内的阻挡层112的部分。
然后可以采用第三蚀刻剂来穿过阻挡层112延伸第二开口部152。第三蚀刻剂可以相对于下量子阱108的材料具有选择性，以使得蚀刻停止在下量子阱108上或下量子阱108中。应当理解的是，第三蚀刻剂可以和第一蚀刻剂相同。
如图13所示，可以在第二开口部152(参见图12)中形成下量子阱接触部158。可以通过本领域中任何公知的技术来形成下量子阱接触部158。在一个实施例中，可以例如通过化学气相沉积(“CVD”)、物理气相沉积(“PVD”)、原子层沉积(“ALD”)等在第二开口部152(参见图12)中和在层间电介质外表面142上沉积导电材料。可以从层间电介质外表面148除去导电材料的部分，例如通过化学机械抛光或蚀刻从层间电介质外表面148除去导电材料的部分，以形成下量子阱接触部158。导电材料可以包括但不限于：铜、铝、银、钛、金、它们的合金等。
应当理解的是，在适当的情况下，可以同时执行用于形成上量子阱接触部146和下量子阱接触部158的各个制造步骤，例如蚀刻、沉淀和光刻构图。
如图13所示，所得到的微电子器件160是双量子阱系统，其中，上量子阱114和下量子阱108中的每一个相对于另一个均基本上是平面的。换言之，上量子阱114和下量子阱108基本上是二维(2D)的，并且由上量子阱114和下量子阱108形成的平面基本上彼此平行。由于上量子阱114和下量子阱108各自具有独立的接触部(即分别是上量子阱接触部146和下量子阱接触部158)且由阻挡层112分隔开，所以上量子阱114和下量子阱108彼此不直接电接触。
微电子器件160的操作基于上量子阱114和下量子阱108之间的直接垂直隧穿。换言之，其基于基本上平行的二维(2D)量子阱之间的隧穿。底层器件的物理特性在于，能量-动量守恒仅当电子密度在上量子阱114和下量子阱108之间匹配时才允许进行隧穿。栅极电极132可以用来调整上量子阱114的电子密度以匹配电子密度，从而操作微电子器件160。因此，如本领域技术人员将理解的那样，通过使用漏极偏置或栅极偏置以使得上量子阱114和下量子阱108中的电子密度不平衡，可以在微电子器件160的IV特性中实现负微分电阻。
在图14中示出的一个示例中，电流(如线162所示)可以从漏极164流到上量子阱接触部146，经过上量子阱接触部146流到上量子阱114中，隧穿阻挡层112进入下量子阱108，并且经过下量子阱接触部158流到与下量子阱接触部158连接的源极166。
微电子器件160可以达到高的峰值驱动电流以实现性能，并且可以达到高的峰谷电流比以实现低功耗和噪声容限。这是因为如下事实：能量-动量守恒可以急剧地抑制上量子阱114和下量子阱108之间的隧穿电流。因此，微电子器件160可能被用作振荡器，或用于存储器和/或逻辑集成电路应用。
虽然本说明书中的双量子阱结构120用铟镓砷量子阱和铟铝砷阻挡层(即InGaAs/InAlAs系统)的示例来描述，但是本领域技术人员应当理解的是，可以用各种量子阱系统来制造双量子阱结构120。在一个实施例中，可以用各种III-V族量子阱系统来制造量子阱系统，这些III-V族量子阱系统包括但不限于：砷化镓/铝镓砷系统(GaAs/AlGaAs)、砷化镓/砷化铝系统(GaAs/AlAs)、锑化铟/铟铝锑系统(InSb/InAlSb)、锑化铟/铟镓锑系统(InSb/InGaSb)等。在另一个实施例中，可以用各种II-VI族量子阱系统来制造量子阱系统，这些II-VI族量子阱系统包括但不限于：硒化锌/锌镉硒系统(ZnSe/ZnCdSe)。在又一个实施例中，可以用硅和锗来制造量子阱系统，所述硅和锗包括但不限于：锗/锗化硅系统(Ge/SiGe)、锗化硅/硅系统(SiGe/硅)等。如本领域技术人员将理解的那样，在其它的实施例中，可以由4族量子阱系统来制造量子阱系统，或者可以由任何适用的通用异质结构、双量子阱系统来制造量子阱系统。
图15是利用本说明书的主题的电子系统200的示意图。电子系统200可以是任何电子设备，包括但不限于便携式设备，例如，便携式计算机、移动电话、数字照相机、数字音乐播放器、网络平板、个人数字助理、传呼机、即时通信设备或其它的设备。电子系统200可以适用于无线地发送和/或接收信息，例如通过无线局域网(WLAN)系统，无线个人局域网(WPAN)系统和/或蜂窝式网络。
在实施例中，电子系统200可以包括系统总线220以电耦合电子系统200的各个部件。系统总线220可以是单总线或根据多个实施例的总线的任意结合。电子系统200可以包括向集成电路210提供电力的电压源230。在某些实施例中，电压源230可以通过系统总线220向集成电路210提供电流。
集成电路210可以与系统总线220电耦合且包括任何电路或根据实施例的电路的结合。在实施例中，集成电路210可以包括处理器212，该处理器212能够是任何类型。如这里所使用的，处理器212可以表示任何类型的电路，例如但不限于微处理器、微控制器、图形处理器、数字信号处理器或另一种处理器。在集成电路210中可以包括的其它类型的电路是定制电路或专用集成电路(ASIC)，例如用于在诸如蜂窝式电话、传呼机、便携式计算机、双向无线电设备和类似的电子系统之类的无线设备中使用的通信电路214。在实施例中，处理器210可以包括管芯上存储器216，例如静态随机存取存储器(SRAM)。在另一个实施例中，集成电路210可以包括嵌入式管芯上存储器216，例如嵌入式动态随机存取存储器(eDRAM)，其可以用作处理器212的高速缓冲存储器。
在实施例中，电子系统200也包括外部存储器240，该外部存储器240又可以包括适用于特定应用的一个或多个存储器元件，例如：RAM或非易失性存储器(例如闪速存储器)形式的主存储器242；一个或多个硬盘驱动器244；和/或管理可移动介质246的一个或多个驱动器，所述可移动介质例如软盘、紧致盘(CD)、数字可变盘(DVD)、闪速存储键和本领域公知的其它可移动介质。
电子系统200可以包括：输入设备270(例如，键盘、鼠标、轨迹球、游戏控制器、话筒等)和输出(I/O)设备(例如，显示设备250和音频输出260)。
如这里所示的，集成电路210和/或主存储器242可以包括至少一个本说明书的负微分电阻器件。集成电路210和/或主存储器242可以以多种不同的实施例来实现，例如电子系统、计算机系统等。本说明书中的垂直隧穿负微分电阻器件和本领域公认的它们的等同形式可以包括在制造集成电路的一个或多个方法和制造电子组件的一个或多个方法中。如这里所描述的，元件、材料、几何形状、尺寸和操作顺序都可以改变以适应垂直隧穿负微分电阻器件。
已经在具体的实施例中描述了本发明，应当理解由所附权利要求限定的本发明并不受上述说明中所列举的特定细节的限制，因为在不脱离本发明精神和范围的情况下，可以对本发明作出许多明显的变化。

Claims (12)

1.一种微电子器件，包括：
微电子衬底；
所述微电子衬底上的缓冲层；
所述缓冲层上的底部阻挡层；
所述底部阻挡层上的下量子阱；
所述下量子阱上的阻挡层；
所述阻挡层上的上量子阱；
所述上量子阱上的顶部阻挡层；
所述顶部阻挡层上的栅极，所述栅极包括栅极电极和位于所述栅极电极与所述顶部阻挡层之间的栅极电介质；
上量子阱接触部，其延伸穿过所述顶部阻挡层并且耦合到所述上量子阱；以及
下量子阱接触部，其耦合到所述下量子阱，其中，所述下量子阱接触部延伸穿过所述顶部阻挡层、所述上量子阱、以及所述阻挡层，并且其中，所述下量子阱接触部利用电介质材料与所述顶部阻挡层和所述上量子阱电隔离。
2.如权利要求1所述的微电子器件，其中，所述上量子阱和所述下量子阱中的至少一个包含铟镓砷。
3.如权利要求1所述的微电子器件，其中，所述阻挡层包括铟铝砷。
4.如权利要求1所述的微电子器件，其中，所述上量子阱和所述下量子阱中的至少一个是n型掺杂的。
5.如权利要求1所述的微电子器件，其中，所述上量子阱和所述下量子阱中的至少一个是p型掺杂的。
6.如权利要求1所述的微电子器件，其中，所述栅极电极适用于调整所述上量子阱中的电流密度。
7.一种制造微电子器件的方法，包括：
提供微电子衬底；
在所述微电子衬底上形成缓冲层；
在所述缓冲层上形成底部阻挡层；
在所述底部阻挡层上形成下量子阱；
在所述下量子阱上形成阻挡层；
在所述阻挡层上形成上量子阱；
在所述上量子阱上形成顶部阻挡层；
在所述顶部阻挡层上形成栅极，包括在所述顶部阻挡层上形成栅极电介质以及在所述栅极电介质上形成栅极电极；
形成上量子阱接触部，所述上量子阱接触部延伸穿过所述顶部阻挡层并且耦合到所述上量子阱；以及
形成耦合到所述下量子阱的下量子阱接触部包括：
形成穿过所述顶部阻挡层和所述上量子阱的开口部；
在所述开口部的侧壁上沉积电介质材料；
使所述开口部延伸穿过所述阻挡层，以暴露所述下量子阱的一部分；以及
沉积导电材料以填充所述开口部。
8.如权利要求7所述的方法，其中，形成所述下量子阱包括：形成铟镓砷下量子阱。
9.如权利要求7所述的方法，其中，形成所述上量子阱包括：形成铟镓砷上量子阱。
10.如权利要求7所述的方法，其中，形成所述阻挡层包括：形成铟铝砷阻挡层。
11.如权利要求7所述的方法，进一步包括：对所述上量子阱和所述下量子阱中的至少一个进行n型掺杂。
12.如权利要求7所述的方法，进一步包括：对所述上量子阱和所述下量子阱中的至少一个进行p型掺杂。
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