TW201448206A - 垂直穿隧負微分電阻裝置 - Google Patents

垂直穿隧負微分電阻裝置 Download PDF

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TW201448206A
TW201448206A TW103129520A TW103129520A TW201448206A TW 201448206 A TW201448206 A TW 201448206A TW 103129520 A TW103129520 A TW 103129520A TW 103129520 A TW103129520 A TW 103129520A TW 201448206 A TW201448206 A TW 201448206A
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quantum well
barrier layer
forming
microelectronic
upper quantum
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TWI528553B (zh
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Ravi Pillarisetty
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Intel Corp
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Abstract

本揭示係有關於微電子裝置的製造,這些微電子裝置具有形成於其中的至少一個負微分電阻裝置。在至少一個實施例中,這些負微分電阻裝置係可利用量子井來予以形成。本說明的負微分電阻裝置之實施例可達成能夠高性能的高峰值驅動電流,以及能夠低的功耗及雜訊容限之高峰谷電流比,這允許其使能夠被使用於邏輯及/或記憶體積體電路中。

Description

垂直穿隧負微分電阻裝置
本揭示內容一般係有關微電子裝置的製造,微電子裝置可包括形成於其中的負微分電阻裝置。
100‧‧‧層狀結構
102‧‧‧微電子基板
104‧‧‧緩衝層
106‧‧‧底部阻障層
108‧‧‧下量子井
112‧‧‧阻障層
114‧‧‧上量子井
116‧‧‧上阻障層
118‧‧‧掩罩
120‧‧‧雙量子井堆疊結構
122‧‧‧介電材料
124‧‧‧外表面
126‧‧‧外表面
132‧‧‧閘極電極
134‧‧‧閘極介電質
136‧‧‧閘極介電質間隙物
138‧‧‧側面
142‧‧‧層間介電質
144‧‧‧第一開口
146‧‧‧上量子井接點
148‧‧‧外表面
152‧‧‧第二開口
154‧‧‧接點介電質間隙物
156‧‧‧側壁
158‧‧‧下量子井接點
160‧‧‧微電子裝置
162‧‧‧線
164‧‧‧汲極
166‧‧‧源極
200‧‧‧電子系統
210‧‧‧積體電路
212‧‧‧處理器
214‧‧‧通訊電路
216‧‧‧晶粒上記憶體
220‧‧‧系統匯流排
230‧‧‧電壓源
240‧‧‧外部記憶體
242‧‧‧主記憶體
244‧‧‧硬碟機
246‧‧‧可移除式媒體
250‧‧‧顯示裝置
260‧‧‧音訊輸出
270‧‧‧輸入裝置
在此說明書的最後部分中,特別地指出,且明顯地主張本揭示內容的標的。本揭示之上述及其他的特性將自下面之結合附圖的說明及後附申請專利範圍中變成更完全顯然可知。要瞭解的是,附圖僅繪示依據本揭示內容的多個實施例,因此,並不視為其範圍的限制。此揭示將經由附圖的使用而以額外的具體性及細節來予以說明,使得可更立即地確定本揭示內容的優點,其中:圖1-13繪示依據本說明的實施例之形成垂直穿隧負微分電阻裝置的程序之側剖面概圖。
圖14繪示依據本說明的實施例之經由垂直穿隧負微分電阻裝置的側剖面概要電流流動。
圖15係依據本說明的實施例之系統的概圖。
【發明內容和實施方式】
在下面的詳細說明中,參考附圖,其顯示(作為例示)所主張的標的可予以實施的特定實施例。這些實施例係以充分的細節來予以說明,以使熟習此項技術者能夠實施此標的。要瞭解的是,各種實施例雖然不同,但是並非必然相互獨立。例如,在不脫離所主張的標的之精神及範圍之下,結合一個實施例的在此所述之特定的特性、結構、或特徵可被實施於其他實施例內。此說明書內之參考「一個實施例」或「實施例」意謂結合此實施例所述之特定的特性、結構或特徵被包括於本發明內所包含的至少一種實施中。因此,「一個實施例」或「在一個實施例中」的詞句之使用不必然參考相同實施例。此外,要瞭解的是,在不脫離所主張的標的之精神及範圍之下,可修改各個所揭示的實施例內之個別元件的位置或配置。因此,下面的詳細說明不是以限制的意義來視之,而是此標的之範圍僅藉由後附申請專利範圍來以界定,伴隨著稱為後附申請專利範圍的等效之完整範圍而適當地予以解讀。在圖式中,相似的標號有關於多個視圖均相同或類似的元件或功能,且其中所繪示的元件不必然彼此按比例繪製,而是個別元件可予以增大或縮小,以便更容易瞭解本說明的本文中之元件。
在本說明的各種實施例中,負微分電阻裝置可利用量子井來予以形成,其中,此類裝置被使用於微電子裝置應用中。負微分電阻為某些電路的特性,其中,進入此電路 的電壓之增加會導致通過相同電路的電流之降低,其中,在此電路之操作範圍的至少某些部分中出現此特性。本說明之負微分電阻裝置的實施例可達成能夠高性能的高峰值驅動電流,以及能夠低的功耗及雜訊容限之高峰谷電流比,如同將由熟習此項技術者所瞭解的。因此,本說明的實施例可被使用於邏輯及/或記憶體積體電路中。
圖1為依據本說明的一個實施例之層狀結構100的剖面概圖。層狀結構100可包括微電子基板102,諸如適當的含矽材料。緩衝層104可被形成於微電子基板102上。在本說明的一個實施例中,緩衝層104係可由砷化鎵(GaAs)來予以形成。
要瞭解的是,在緩衝層104的形成之前,成核(nucleation)層(未顯示出)可被形成於微電子基板102上,且緩衝層104可包含多層。緩衝層104也可被梯度化,以提供滑動差排(gliding dislocation),以及微電子基板102與被形成於緩衝層104之上的底部阻障層間之晶格不匹配的控制。
在緩衝層104的形成之後,底部阻障層106可被形成於緩衝層104上。在一個實施例中,底部阻障層106係可由比量子井(其被形成於底部阻障層106上)的材料更大之帶隙材料來予以形成。在一個實施例中,底部阻障層106可包含砷化鋁銦(InxAl1-xAs)。在另一個實施例中,底部阻障層106可被梯度化。在特定實施例中,底部阻障層106可包含具有自x等於零開始至x等於0.52的梯度之砷化鋁銦 (InxAl1-xAs)。因此,在底部阻障層106與緩衝層104之間的界面處之組合物可以砷化鋁(AlAs)開始,而可在其另一邊界處,以In0.52Al0.48As結束。在另一個實施例中,底部阻障層106可包含砷化鋁銦(InxAl1-xAs),其中,此梯度可藉由以自砷化鋁(AlAs)直至到達砷化鋁銦(諸如,In0.52Al0.48As)為止的組合物之線性增加的方式,來改變形成期間的銦供應而為線性的。在又另一個實施例中,底部阻障層106可包含具有非線性梯度的砷化鋁銦(InxAl1-xAs),其中,此銦供應可以非線性增加的方式來予以提供,使得底部阻障層106可具有比此底部阻障層106的物理中點處之銦的一半濃度更大或更小之濃度。藉由形成底部阻障層106,差排可沿著其中之相當斜的平面滑動,如同將由熟習此項技術者所瞭解的。
在底部阻障層106的形成之後,下量子井108可被形成於其上。在一個實施例中,下量子井108係可由具有比底部阻障層106的帶隙更小之帶隙的材料來予以形成。在一個實施例中,下量子井108係可由砷化鎵銦來予以形成。在特定實施例中,下量子井108可為砷化鎵銦(亦即,InxGa1-xAs,其中,x等於約0.53與0.8之間)。在一個實施例中,下量子井108可被摻雜,以提升效率。在不同的實施例中,下量子井108可以p-摻雜物(諸如,硼),或n-摻雜物(諸如,磷)來予以摻雜。下量子井108的摻雜可藉由此項技術中所已知的任何技術來予以達成。另外,下量子井108可直接被摻雜,或經由後續形成的一層或多層 之高平面(delta)摻雜來予以摻雜,如同將由熟習此項技術者所瞭解的。此外,下量子井108可被調制摻雜,如同將由熟習此項技術者所瞭解的。
阻障層112可被形成於下量子井108之上。在一個實施例中,阻障層112可包含砷化鋁銦(例如,InxAl1-xAs)。
上量子井114可被形成於阻障層112上。在一個實施例中,上量子井114可由砷化鎵銦來予以形成。在特定實施例中,上量子井114可包含砷化鎵銦(亦即,InxGa1-xAs,其中,x等於約0.53與0.8之間)。在一個實施例中,上量子井114可予以摻雜,以提升效率。在不同的實施例中,上量子井114可以p-摻雜物(諸如,硼),或n-摻雜物(諸如,磷)來予以摻雜。上量子井114的摻雜可藉由此項技術中所已知的任何技術來予以達成。另外,上量子井114可直接被摻雜,或經由後續形成的一層或多層之高平面摻雜來予以摻雜,如同將由熟習此項技術者所瞭解的。此外,上量子井114可被調制摻雜,如同將由熟習此項技術者所瞭解的。
在一個實施例中,下量子井108及上量子井114皆可未被摻雜。在另一個實施例中,下量子井108及上量子井114皆可被摻雜。在另外實施例中,下量子井108及上量子井114的其中一個可被摻雜,而另一個未被摻雜。
上阻障層116可選擇性地被形成於上量子井114之上。在一個實施例中,上阻障層116可包含砷化鋁銦(例如,InxAl1-xAs)。
要瞭解的是,圖1中所顯示的層狀結構100僅為範例,且可包括各種的緩衝層、阻障層、調制摻雜的環形層、間隙物層等等,以達成所想要的結果,如同將由熟習此項技術者所瞭解的。再者,在不脫離本說明之下,可使用各種的材料及系統。進一步要瞭解的是,層狀結構100中的各種層可藉由此項技術中之任何已知的技術(其包括,但不受限於,化學氣相沈積(「CVD」)、物理氣相沈積(「PVD」)、原子層沈積(「ALD」)、分子束磊晶(MBE)、有機金屬化學氣相沈積磊晶(MOCVD epi)、超高真空CVD磊晶(UHCVD epi)、及降低溫度的CVD磊晶(RTCVD epi))來予以製造。
如圖2中所顯示,掩罩118可被圖案化於上阻障層116上。掩罩118可藉由此項技術中所已知的任何技術(其包括,但不受限於,微影)來予以形成。圖2的層狀結構100然後可被蝕刻為如圖3中所顯示者,其中,由掩罩118所保護的層(緩衝層104、底部阻障層106、下量子井108、阻障層112、上量子井114、及上阻障層116)殘留,以形成雙量子井堆疊結構120。在本說明的各種實施例中,如圖3中所顯示,此蝕刻可選擇停止於緩衝層104上或中,或可選擇停止於底部阻障層106上或中。
如圖4中所顯示,可移除式掩罩118,且形成介電材料122,以鄰接雙量子井堆疊結構120。在一個實施例中,介電材料122可為沈積於雙量子井堆疊結構120之上的覆蓋物(blanket),然後被平坦化,以具有與上阻障層116的外 表面126實質上為平面之外表面124。介電材料122可包括,但不受限於,二氧化矽(SiO2)、氮氧化矽(SiOxNy)、及氮化矽(Si3N4)。介電材料122可藉由此項技術中所已知的任何技術(其包括,但不受限於,濕式或乾式蝕刻,及化學機械研磨)來予以平坦化。
如圖5中所顯示,閘極電極132可被形成於上阻障層外表面126上。閘極電極132可被使用來調制上量子井114的電子密度,如同將被討論的。在一個實施例中,閘極介電質134可被形成於閘極電極132與上阻障層116之間。閘極介電質134可為任何適當的介電質材料,其包括,但不受限於,高K(高介電常數)材料(諸如,氧化鉿、氧化矽鉿、氧化鑭、氧化鋁鑭、氧化鋯、氧化矽鋯、氧化鉭、氧化鈦、氧化鈦鍶鋇、氧化鈦鋇、氧化鈦鍶、氧化釔、氧化鋁、氧化鉭鈧鉛、及鈮酸鋅鉛)。閘極電極132及/或閘極介電質134可藉由熟知的技術(諸如,化學氣相沈積(「CVD」)、物理氣相沈積(「PVD」)、原子層沈積(「ALD」))來予以製造,然後以熟知的光微影及蝕刻技術來圖案化,如同將由熟習此項技術者所瞭解的。
如圖6中所顯示,閘極介電質間隙物136可被形成為鄰接閘極電極132的側面138。閘極介電質間隙物136可由任何適當的介電質材料(其包括,但不受限於,二氧化矽(SiO2)及氮化矽(Si3N4))來予以形成。閘極介電質間隙物136可藉由任何已知的技術(其包括,但不受限於,緊接在蝕刻之後的同形(conformal)沈積)來予以製造, 如同將由熟習此項技術者所瞭解的。
如圖7中所顯示,層間介電質142可被形成於閘極電極132、閘極介電質間隙物136、上阻障層外表面126、及介電質材料外表面124之上。層間介電質142可為任何適當的介電質材料,其包括,但不受限於,二氧化矽(SiO2)。層間介電質142可藉由任何已知的技術(其包括,但不受限於,緊接在平坦化之後的沈積)來予以製造,如同將由熟習此項技術者所瞭解的。
如圖8中所顯示,第一開口144可被形成穿過層間介電質142及上阻障層116,以使上量子井114的部分曝露出。第一開口144可藉由此項技術中所已知的任何技術(其包括,但不受限於,微影蝕刻、雷射鑽孔、離子鑽孔、濕式蝕刻、乾式蝕刻、或其任何組合)來予以形成。在一個實施例中,可使用微影蝕刻技術,其中,掩罩(未顯示出)被圖案化於層間介電質142上。層間介電質142及上阻障層116然後可以蝕刻劑(其選擇上量子井114的材料)來予以蝕刻穿過此掩罩(未顯示出),使得此蝕刻停止於上量子井114上或中。
如圖9中所顯示,上量子井接點146可被形成於第一開口144(見圖8)中。上量子井接點146可藉由此項技術中所已知的任何技術來予以形成。在一個實施例中,導電材料可諸如藉由化學氣相沈積(「CVD」)、物理氣相沈積(「PVD」)、原子層沈積(「ALD」)等等而被沈積於第一開口144(見圖8)中,及層間介電質142的外表面148 上。此導電材料的部分然後可諸如藉由自層間介電質外表面148化學機械研磨或蝕刻,而自層間介電質外表面148去除,以形成上量子井接點146。此導電材料可包括,但不受限於,銅、鋁、銀、鈦、金、其合金等等。
然後,可形成下量子井接點,如圖10-13中所顯示。如圖10中所顯示,第二開口152可被形成穿過層間介電質142、上阻障層116、及上量子井114。第二開口152可藉由此項技術中所已知的任何技術(其包括,但不受限於,微影蝕刻、雷射鑽孔、離子鑽孔、濕式蝕刻、乾式蝕刻、或其任何組合)來予以形成。在一個實施例中,可使用微影蝕刻技術,其中,掩罩(未顯示出)被圖案化於層間介電質142上。層間介電質142及上阻障層116然後可以第一蝕刻劑(其選擇上量子井114的材料)予以蝕刻穿過此掩罩(未顯示出),使得此蝕刻停止於上量子井114上或中。然後可使用第二蝕刻劑,以蝕刻穿過上量子井114。第二蝕刻劑可選擇阻障層112的材料,使得此蝕刻停止於阻障層112上或中。
為了使上量子井114與此後續形成的下量子井接點隔離,接點介電質間隙物154可被形成於第二開口152的側壁156上,如圖11中所顯示。接點介電質間隙物154可由任何適當的介電質材料(其包括,但不受限於,二氧化矽(SiO2)及氮化矽(Si3N4))來予以形成。接點介電質間隙物154可藉由任何已知的技術(其包括,但不受限於,緊接在蝕刻之後的同形沈積)來予以製造,以使第二開口 152內之阻障層112的部分曝露出,如同將由熟習此項技術者所瞭解的。
然後可使用第三蝕刻劑,以使第二開口152延伸穿過阻障層112。第三蝕刻劑可選擇上量子井114的材料,使得此蝕刻停止於上量子井114上或中。要瞭解的是,第三蝕刻劑可與第一蝕刻劑相同。
如圖13中所顯示,下量子井接點158可被形成於第二開口152(見圖12)中。下量子井接點158可藉由此項技術中所已知的任何技術來予以形成。在一個實施例中,導電材料可諸如藉由化學氣相沈積(「CVD」)、物理氣相沈積(「PVD」)、原子層沈積(「ALD」)等等而被沈積於第二開口152(見圖12)中,及層間介電質外表面142上。此導電材料的部分然後可諸如藉由自層間介電質外表面148化學機械研磨或蝕刻,而自層間介電質外表面148去除,以形成下量子井接點158。此導電材料可包括,但不受限於,銅、鋁、銀、鈦、金、其合金等等。
要瞭解的是,如果合適的話,可同時實施上量子井接點146及下量子井接點158的形成中所使用的各種製造步驟(諸如,蝕刻、沈積、及微影圖案化)。
所產生的微電子裝置160(如圖13中所顯示)為雙量子井系統,其中,上量子井114及下量子井108各自實質上彼此為平面。換言之,上量子井114及下量子井108實質上為二維(2D),且由上量子井114及下量子井108所形成的平面實質上彼此平行。因為上量子井114及下量子井108各 自具有獨立的接點(亦即,分別是上量子井接點146及下量子井接點158),且被阻障層112分離,所以上量子井114及下量子井108不會彼此直接電氣接觸。
微電子裝置160的操作係根據上量子井114與下量子井108之間的直接垂直穿隧。換言之,其係根據實質上平行的二維(2D)量子井之間的穿隧。下層的裝置物理為當上量子井114與下量子井108之間的電子密度匹配時,能量-動量守恆僅允許穿隧。閘極電極132可被使用來調制上量子井114的電子密度,以使電子密度匹配而操作微電子裝置160。因此,藉由使用使上量子井114及下量子井108的電子密度不平衡之汲極偏壓或閘極電壓,可達成在微電子裝置160的IV特徵中之負微分電阻,如將由熟習此項技術者所瞭解的。
在圖14中所顯示的一個範例中,電流(如線162所顯示)可自汲極164流動至上量子井接點146、經由上量子井接點146而流動至上量子井114中、經由阻障層112而穿隧至下量子井108中、及經由下量子井接點158而流動至連接至下量子井接點158的源極166中。
微電子裝置160可達成能夠高性能的高峰值驅動電流,以及能夠低的功耗及雜訊容限之高峰谷電流比。這是由於能量-動量守恆可明確地抑制上量子井114與下量子井108之間的穿隧電流。因此,微電子裝置160可被使用作為振盪器,或用於記憶體及/或邏輯積體電路應用。
雖然本說明的雙量子井結構160係以砷化鎵銦量子井 及砷化鋁銦阻障層(亦即,InGaAs/InAlAs系統)來予以說明,但是熟習此項技術者將瞭解的是,雙量子井結構160可以各種的量子井系統來予以製成。在一個實施例中,這些量子井系統可以種種的三五族量子井系統(其包括,但不受限於,砷化鎵/砷化鎵鋁系統(GaAs/AlGaAs)、砷化鎵/砷化鋁系統(GaAs/AlAs)、銻化銦/銻化鋁銦系統(InSb/InAlSb)、銻化銦/銻化鎵銦系統(InSb/InGaSb)等等)來予以製成。在另一個實施例中,這些量子井系統可以種種的二六族量子井系統(其包括,但不受限於,硒化鋅/硒化鎘鋅系統(ZnSe/ZnCdSe))來予以製成。在又另一個實施例中,這些量子井系統可以矽及鍺(其包括,但不受限於,鍺/鍺化矽系統(Ge/SiGe)、鍺化矽/矽系統(SiGe/Si)等等)來予以實施。在更其他的實施例中,這些量子井系統可由四族量子井系統來予以製成,或可由任何可應用的一般異質結構之雙量子井系統來予以製成,如同將由熟習此項技術者所瞭解的。
圖15為利用本說明的標的之電子系統200的概圖。電子系統200可為任何電子裝置,其包括,但不受限於,可攜式裝置(諸如,可攜式電腦、行動電話、數位相機、數位音樂播放器、上網平板電腦(web tablet)、個人數位助理器、分頁器、即時訊息裝置、或其他裝置)。電子系統200可被適用以諸如經由無線局域網路(WLAN)系統、無線個人區域網路(WPAN)系統、及/或蜂巢式網 路,而無線地發送及/或接收資訊。
在實施例中,電子系統200可包括電氣地耦接電子系統200的各種組件之系統匯流排220。系統匯流排220可為單一匯流排,或依據各種實施例之匯流排的任何組合。電子系統200可包括將電力提供給積體電路210的電壓源230。在某些實施例中,電壓源230可將電流經由系統匯流排220而供應至積體電路210。
積體電路210可被電氣耦接至系統匯流排220,且包括任何電路,或依據實施例之電路的組合。在實施例中,積體電路210可包括可為任何型式的處理器212。如同在此所使用的,處理器212可意謂任何型式的電路,諸如,但不受限於,微處理器、微控制器、圖形處理器、數位訊號處理器、或另一種處理器。可被包括於積體電路210中之其他型式的電路為客製化電路或特定應用積體電路(ASIC),諸如無線裝置(諸如,行動電話、分頁器、可攜式電腦、對講機(two-way radios)等等的電子系統)中使用的通訊電路214。在實施例中,積體電路210可包括晶粒上記憶體216,諸如靜態隨機存取記憶體(SRAM)。在另一個實施例中,積體電路210可包括可被使用作為處理器212的快取記憶體之嵌入式晶粒上記憶體216,諸如嵌入式動態隨機存取記憶體(eDRAM)。
在實施例中,電子系統200還包括外部記憶體240,其依序可包括適用於特定應用的一個或多個記憶體元件(諸如,以RAM的形式之主記憶體242,或非揮發性記憶體 (諸如快閃記憶體))、一個或多個硬碟機244、及/或處理可移除式媒體246(諸如,碟片、光碟(CD)、數位影音碟片(DVD)、快閃記憶體鑰匙、及此項技術中所已知的其他可移除式媒體)的一個或多個碟機。
電子系統200可包括輸入裝置270(諸如,鍵盤、滑鼠、軌跡球、遊戲控制器、麥克風等等),及輸出(I/O)裝置(諸如,顯示裝置250及音訊輸出260)。
如同在此所顯示的,積體電路210及/或主記憶體242可包括本說明的至少一個負微分電阻裝置。積體電路210及/或主記憶體242可以一些不同的實施例(諸如,電子系統、電腦系統等等)來予以實施。本說明的垂直穿隧負微分電阻裝置之各種實施例及其技術承認的等效可包括於製造積體電路的一種或多種方法,及製造電子組件的一種或多種方法中。這些元件、材料、幾何、尺寸、及操作的順序均可予以變化,以符合如同在此所述的垂直穿隧負微分電阻裝置。
因此已詳細說明本說明的實施例,要瞭解的是,在不脫離其的精神或範圍之下,由後附之申請專利範圍所界定的本發明並非被以上說明中所提及的特定細節限制,如其許多顯然可知的變化是可行的。
100‧‧‧層狀結構
102‧‧‧微電子基板
104‧‧‧緩衝層
106‧‧‧底部阻障層
108‧‧‧下量子井
112‧‧‧阻障層
114‧‧‧上量子井
116‧‧‧上阻障層

Claims (18)

  1. 一種微電子裝置,包含:上量子井;下量子井,藉由阻障層而與該上量子井分離;閘極電極,靠近該上量子井;上量子井接點,耦接至該上量子井;以及下量子井接點,耦接至該下量子井,其中該下量子井接點延伸穿過該上量子井且藉由介電材料與其電氣隔離。
  2. 如申請專利範圍第1項之微電子裝置,其中,該上量子井及該下量子井的至少其中一個包含砷化鎵銦。
  3. 如申請專利範圍第1項之微電子裝置,其中,該阻障層包含砷化鋁銦。
  4. 如申請專利範圍第1項之微電子裝置,其中,該上量子井及該下量子井的至少其中一個係n-摻雜的。
  5. 如申請專利範圍第1項之微電子裝置,其中,該上量子井及該下量子井的至少其中一個係p-摻雜的。
  6. 如申請專利範圍第1項之微電子裝置,其中,該閘極電極係適以調制該上量子井中的電流密度。
  7. 一種微電子裝置之製造方法,包含:形成下量子井;形成靠近該下量子井的阻障層;形成靠近該阻障層的上量子井;形成靠近該上量子井的閘極電極; 形成耦接至該上量子井的上量子井接點;以及形成耦接至該下量子井的下量子井接點,包含:形成穿過該上量子井的開口;沈積介電材料於該開口的側壁上;使該開口延伸穿過該阻障層,以使該下量子井的一部分曝露出;以及沈積導電材料以填充該開口。
  8. 如申請專利範圍第7項之方法,其中,形成該下量子井包含形成砷化鎵銦下量子井。
  9. 如申請專利範圍第7項之方法,其中,形成該上量子井包含形成砷化鎵銦上量子井。
  10. 如申請專利範圍第7項之方法,其中,形成該阻障層包含形成砷化鋁銦阻障層。
  11. 如申請專利範圍第7項之方法,更包含摻雜該上量子井及該下量子井的至少其中一個。
  12. 如申請專利範圍第7項之方法,更包含:提供微電子基板;形成緩衝層於該微電子基板上;以及形成底部阻障層於該緩衝層上;其中,形成該下量子井包含形成該下量子井於該底部阻障層上。
  13. 一種微電子系統,包含:積體電路裝置;以及主記憶體; 其中,該積體電路裝置及該主記憶體的至少其中一個包括微電子裝置,該微電子裝置包含:上量子井;藉由阻障層而與該上量子井分離的下量子井;靠近該上量子井的閘極電極;耦接至該上量子井的上量子井接點;以及耦接至該下量子井的下量子井接點,其中該下量子井接點延伸穿過該上量子井且藉由介電材料與其電氣隔離。
  14. 如申請專利範圍第13項之微電子系統,其中,該上量子井及該下量子井的至少一其中個包含砷化鎵銦。
  15. 如申請專利範圍第13項之微電子系統,其中,該阻障層包含砷化鋁銦。
  16. 如申請專利範圍第13項之微電子系統,其中,該上量子井及該下量子井的至少其中一個係n-摻雜的。
  17. 如申請專利範圍第13項之微電子系統,其中,該上量子井及該下量子井的至少其中一個係p-摻雜的。
  18. 如申請專利範圍第13項之微電子系統,其中,該閘極電極係適以調制該上量子井中的電流密度。
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