CN103477428B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN103477428B
CN103477428B CN201280018242.2A CN201280018242A CN103477428B CN 103477428 B CN103477428 B CN 103477428B CN 201280018242 A CN201280018242 A CN 201280018242A CN 103477428 B CN103477428 B CN 103477428B
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conductive pattern
dielectric substrate
heat dissipating
semiconductor device
junction surface
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CN201280018242.2A
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CN103477428A (zh
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长畦文男
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

本发明提供一种半导体器件及其制造方法,能够减小接合部隅角上的应力集中,来抑制或防止在例如温度循环的可靠性测试中焊料层产生裂纹。本发明所涉及的半导体器件具有如下连接结构:在两个表面接合有导体图案(2a、2b)的绝缘衬底(1)上安装半导体芯片(3),并且将绝缘衬底(1)与散热用基底构件(4)接合,使得由半导体芯片(3)产生的热量能够释放到外部。一端与安装有半导体芯片(3)的绝缘衬底的正面上的导体图案(2a)接合的内部连接端子(70)的接合部(71、72)为圆形。此外,绝缘衬底的背面上的与散热基底构件(4)进行接合的导体图案(2b)的接合面为长方形,且在隅角附近具有预定的曲率半径。其结果是,能够将施加在固定层、例如焊料层的隅角上的应力减小至弹性极限以下。

Description

半导体器件及其制造方法
技术领域
本发明涉及用于例如功率半导体模块的半导体器件及其制造方法,特别是涉及具有如下连接结构的半导体器件及其制造方法:在绝缘衬底上安装功率半导体芯片并且将绝缘衬底与散热基底构件接合,使得由功率半导体芯片产生的热量能释放到外部。
背景技术
用于例如功率半导体模块的半导体器件中,随着电流容量及元器件密度增大且模块尺寸减小,流过封装件中布线的电流量会增加,从而需要提高模块的散热性。此外,在很多情况下,为了减小布线电感,使用利用了铜板的引线框,以取代现有技术中的铝引线接合。
图8是表示现有技术所涉及的半导体器件的纵向剖视图及俯视图。
图8(A)是沿图8(B)的线A-A所得到的纵向剖视图。由例如陶瓷构成的绝缘衬底1是在其两个表面接合有导体图案2a和2b的DBC(直接接合铜)衬底。此外,在绝缘衬底1的正面上作为铜电路而形成的导体图案2a上通过焊接安装有半导体芯片3。在绝缘衬底1的背面接合有导体图案2b,该导体图案2b具有与导体图案2a相同的厚度,且与散热基底构件4接合,使得由半导体芯片3产生的热量释放到外部。散热基底构件4形成树脂外壳5的底部,且有大小两个绝缘衬底1与散热基底构件4接合。半导体芯片3、内部连接端子7、和铝引线8被填充在树脂外壳5中的胶状密封构件6保护。
图8(B)是表示密封构件6填充之前的半导体衬底的状态的俯视图。半导体芯片3的金属电极3a和3b通过内部连接端子7和铝引线8而与导体图案2a的预定部分进行内部连接。此外,多个外部引出端子9a和9b从导体图案2a引出到树脂外壳5的上表面。内部连接端子7和外部引出端子9a及9b是通过对铜板进行加工而得到的引线框。
在诸如模块型功率半导体器件、智能功率模块、或分立半导体产品的半导体器件中,半导体芯片3的金属电极3a及3b与内部连接端子7之间、内部连接端子7与固定于绝缘衬底1的导体图案2a之间在器件内部进行布线,且外部引出端子9a及9b引出到器件的外部。在半导体器件中,通常来说,半导体芯片3与导体图案2a之间、导体图案2b与散热基底构件4之间、或者导体图案2a与内部连接端子7或外部引出端子9a及9b之间通过例如焊接、钎焊、超声波接合、或激光焊接来进行连接并布线。此外,通常来说,半导体器件的元器件为圆形或矩形,且通过使具有不同热膨胀系数的金属材料进行接合来形成。
图9是表示沿图8(A)的线IX-IX所得到的现有技术所涉及的半导体器件的剖视图。
在用于例如功率半导体模块的半导体器件中,通常来说,如图9所示,与散热基底构件4接合的导体图案2b为正方形或长方形。此外,一般而言,在半导体芯片与金属端子之间、在金属材料之间、或者在金属端子与固定于绝缘衬底的金属图案之间形成布线时,彼此连接的各个元器件具有与模块的外形相对应的形状,其为正方形或长方形。因此,在通过焊接或钎焊将半导体芯片与金属端子、或者将热膨胀系数不同的金属材料彼此连接时,在例如温度循环可靠性测试中,元器件具有不同的热膨胀系数,沿接合面产生的应力会集中在有棱角的隅角上。因此,焊料层或钎焊填料金属层容易破损或破裂。
图10是表示温度循环测试时在焊料固定层中产生的裂纹的图。图10(A)和10(B)示出在形成于图8所示的大小两个绝缘衬底1的背面上的导体图案2b通过焊接固定于散热基底构件4的状态下进行例如温度循环可靠性测试时元器件重复膨胀及收缩所产生的裂纹。
图10(A)和10(B)中,用箭头表示各个固定层13a和13b中产生的裂纹的扩展方向。在图10(A)所示的俯视时呈正方形的固定层13a的超声波照片中,将与焊料的产生裂纹部分相当的区域表示为较大的白色区域。
如上所述,在将与图10所示的金属构件12相对应的导体图案2b的下表面焊接在与金属构件11相对应的散热基底构件4上的半导体器件中,在固定层13的隅角产生较大的剪切应变,从而导致从隅角开始产生裂纹。当在绝缘衬底1的隅角产生的裂纹到达半导体芯片3的接合面时,从绝缘衬底1向散热基底构件4的热流被裂纹阻挡。因此,用于释放所产生的热量的半导体芯片3的散热性变差。其结果是,元件的结温异常上升,从而导致热损坏。
下述专利文献1披露了具有如下连接结构的半导体器件。当焊料层的厚度较小时,由于使用环境下的热循环,会导致因绝缘衬底与引线框之间的热膨胀差而向焊接部施加热应力,该热应力会导致较早地产生疲劳损坏。因此,在引线框或绝缘衬底的铜电路图案的焊接面上形成突起,以防止焊料层的厚度出现偏差。
此外,专利文献2披露了如下结构:为了减小施加于接合部的应力,在衬底的四个隅角形成倒角部或在导体图案中形成缝隙。在该结构中,因热循环而施加于接合部的热应力减小,增加了直到裂纹产生为止的时间,从而防止裂纹生长。
现有技术文献
专利文献
专利文献1:日本专利第4100685号(参见段落[0008]至[0014])
专利文献2:日本专利第4124040号(参见段落[0024]至[0071])
发明内容
本发明要解决的问题
特别是,剪切应力容易集中于正方形或长方形的金属元器件的隅角上,从而导致从固定层的隅角产生裂纹。接合面中产生的裂纹的生长会降低半导体器件的散热性,从而会导致尤其是从功率半导体模块产生的热量难以释放到外部。最终,会产生半导体器件发生热损环的严重问题。
本发明是鉴于上述问题而完成的,本发明的目的在于提供如下的半导体器件及其制造方法,该半导体器件能够减小接合部隅角上的应力集中,来抑制或防止在例如温度循环可靠性测试中焊料层裂纹扩展。
解决问题的手段
为了解决上述问题,根据本发明,提供一种半导体器件,具有如下连接结构:在正面和背面接合有导体图案的绝缘衬底上安装功率半导体芯片,并且将所述绝缘衬底与散热基底构件接合,使得由所述功率半导体芯片产生的热量能释放到外部。在该半导体器件中,所述绝缘衬底的背面上的与所述散热基底构件进行接合的所述导体图案的接合部为长方形,且在隅角附近具有预定的曲率半径。所述预定的曲率半径在1mm~10mm的范围内。
为了解决上述问题,根据本发明,提供一种半导体器件,具有如下连接结构:在正面和背面接合有导体图案的绝缘衬底上安装功率半导体芯片,并且将所述绝缘衬底与散热基底构件接合,使得由所述功率半导体芯片产生的热量能释放到外部。在该半导体器件中,所述绝缘衬底的背面上的与所述散热基底构件进行接合的所述导体图案包括多个与所对应的散热基底构件接合的接合部。各接合部为长方形,且在隅角的附近具有预定的曲率半径。预定的曲率半径在1mm~10mm的范围内。
为了解决上述问题,根据本发明,提供一种半导体器件,具有如下连接结构:在正面和背面接合有导体图案的绝缘衬底上安装功率半导体芯片,并且将所述绝缘衬底与散热基底构件接合,使得由所述功率半导体芯片产生的热量能释放到外部。在该半导体器件中,所述绝缘衬底的背面上的与所述散热基底构件进行接合的所述导体图案的接合部具有如下形状:其包括一个或多个弯曲部,且在弯曲部及隅角附近具有预定的曲率半径。预定的曲率半径在1mm~10mm的范围内。
为了解决上述问题,根据本发明,提供一种半导体器件,具有如下连接结构:在正面和背面接合有导体图案的绝缘衬底上安装功率半导体芯片,并且将所述绝缘衬底与散热基底构件接合,使得由所述功率半导体芯片产生的热量能释放到外部。在该半导体器件中,所述绝缘衬底的背面上的与所述散热基底构件进行接合的所述导体图案包括多个与所对应的散热基底构件接合的接合部。各接合部为有六条边以上的多边形。
根据本发明,提供一种半导体器件的制造方法,该半导体器件具有如下连接结构:在绝缘衬底上安装功率半导体芯片,并且将所述绝缘衬底与散热基底构件连接,使得由所述功率半导体芯片产生的热量能释放到外部。该方法包括:在所述绝缘衬底的正面和背面接合导体图案,所述绝缘衬底的背面上的导体图案的接合部为长方形且在隅角附近具有预定的曲率半径;在所述散热基底构件与所述导体图案之间设置具有与所述导体图案相同的平面形状且具有预定厚度的片状焊料;以及对所述片状焊料进行固化以形成将所述导体图案与所述散热基底构件连接的焊料固定层。预定的曲率半径在1mm~10mm的范围内。
本发明的效果
根据本发明,施加在固定层隅角上的应力被设定在弹性极限以下。从而,可以抑制和防止固定层中产生裂纹。因此,在严酷的温度条件下使用的半导体器件的散热性得以确保,从而能够延长半导体器件的寿命。
本发明的上述及其他目的、特征、及优点将通过与表示本发明的优选实施方式的附图相关联的下述说明变得更加清楚。
附图说明
图1是表示本发明的第一实施方式的半导体器件的纵向剖视图及俯视图。
图2是沿图1(A)的线II-II所得到的剖视图。
图3是表示通过焊料固定层使两个金属构件彼此接合的状态的剖视图。
图4是示出本发明第二实施方式的半导体器件的散热基底构件与绝缘衬底之间的接合状态的图。
图5是示出本发明第三实施方式的半导体器件的散热基底构件与绝缘衬底之间的接合状态的图。
图6是表示本发明第四实施方式的半导体器件的俯视图及纵向剖视图。
图7是示出本发明第五实施方式的半导体器件的散热基底构件与绝缘衬底之间的接合状态的图。
图8是表示现有技术所涉及的半导体器件的纵向剖视图及俯视图。
图9是表示沿图8(A)的线IX-IX所得到的现有技术所涉及的半导体器件的剖视图。
图10是表示温度循环测试中出现在焊料固定层中的裂纹的图。
具体实施方式
下面,参照附图对本发明的实施方式进行说明。图1是表示本发明第一实施方式所涉及的半导体器件的纵向剖视图及俯视图。图2是沿图1(A)的线II-II得到的剖视图。
在图示的功率半导体器件中,在正面和背面接合有导体图案2a和2b的绝缘衬底1上安装半导体芯片3,且绝缘衬底1与散热基底构件4接合。由此,能够使由半导体芯片3产生的热量释放到外部。此外,在功率半导体器件中,作为铜板引线框的外部引出端子9a和9b与安装有半导体芯片3的绝缘衬底1的正面上的导体图案2a接合。功率半导体器件包括将半导体芯片3的金属电极3a与导体图案2a相连接的内部连接端子70。该连接结构与图8所示的现有技术所涉及的器件的结构相同。
该功率半导体器件的第一个特征在于,内部连接端子70和外部引出端子9a及9b的接合部71、72的外形为例如圆形的弯曲形状。其第二个特征在于,如图2所示,与散热基底构件4接合的导体图案2b的隅角被倒圆,且所述导体图案的外形为弯曲形状,从而能够减小应力集中,防止其与散热基底构件4之间的焊料固定层中产生裂纹。即,如图2所示,绝缘衬底1的背面侧上与散热基底构件4进行接合的导体图案2b的接合部为长方形,且稍稍大于绝缘衬底1。而且,导体图案2b在其隅角附近具有预定的曲率半径。通过实验,该曲率半径可在1mm~10mm的范围内。
一端与安装有半导体芯片3的绝缘衬底的正面上的导体图案2a接合的内部连接端子70的接合部71、72为圆形。此外,从绝缘衬底的正面上的导体图案2a引出的外部引出端子9a和9b的接合部91也为圆形。从而,焊料固定层的隅角被倒圆,施加在被倒圆的隅角上的应力能够被设定在弹性极限以下。因此,能够确保半导体器件的散热性。
接着,对利用焊料层使具有不同热膨胀系数的接合构件之间进行接合时产生的裂纹进行说明。
在将具有不同热膨胀系数的金属构件彼此连接的情况下,当其环境温度重复上升及下降时,由于金属构件以不同的比例伸缩,因此应力会重复地施加在将金属构件接合起来的焊料层或钎焊填料金属层上。其结果是,容易产生裂纹。
图3是表示通过焊料固定层使两个金属构件彼此接合的状态的剖视图。
图3中,X轴表示构件的长度方向,Y轴表示构件的厚度方向。假设金属构件11和12分别具有不同的热膨胀系数α1和α2(α1<α2)及纵向弹性模量E1和E2。此外,假设固定层13是具有剪切弹性模量Gc的焊料层且具有厚度h。
如图3所示,在第二金属构件12通过焊料固定层13与第一金属构件11接合的状态下,在固定层13的外周部形成有角焊缝。一般而言,已知当将长度L和厚度t2的第二金属构件12与厚度t1的第一金属构件11接合,在接合结构中产生T[℃]的温度变化时,固定层13中的焊料的剪切应变率(Δγ)可通过下式(1)来计算出。
[式1]
&Delta;&gamma; &ap; ( L / 2 ) &CenterDot; ( &alpha; 2 - &alpha; 1 ) &CenterDot; T / { ( A ) &CenterDot; h }
(其中,系数A为Gc/h·{1/(E2·t2)+1/(E1·t1)})。
根据式1,第一和第二金属构件11和12的厚度t1和t2以及第二金属构件12的长度L越大,施加在固定层13上的应力的剪切应变率就Δγ越大。其结果是,容易产生裂纹。
即,在内部连接端子70和外部连接导体90的接合部71、72、91与安装有半导体芯片3的绝缘衬底的正面上的导体图案2a接合时,由于接合部为圆形,因此式1中的长度L变小。同样,与绝缘衬底1的背面接合的导体图案2b具有与散热基底构件4相接合的长方形接合面,该长方形接合面的隅角具有预定的曲率半径。因此,式1中的长度L变小。由此,能够减小作用于固定层13的剪切应变率Δγ。
在制造上述功率半导体器件的方法中,首先,将导体图案2a和2b与绝缘衬底1的正面和背面相接合。在接合过程中,与绝缘衬底1的背面相接合的导体图案的接合部为长方形,且该导体图案的隅角被倒圆。
然后,在散热基底构件4与导体图案2b之间设置具有与导体图案2b相同的平面形状且具有预定厚度的片状焊料,并对该片状焊料进行加热。然后,使熔融的片状焊料进行固化以形成将导体图案2b与散热基底构件4连接的焊料固定层。此外,导体图案2b可通过钎焊与散热基底构件4接合。
导体图案2a、2b中与散热基底构件4接合的导体图案2b形成为与绝缘衬底1的接合面的周边部的厚度小于该接合部中心的厚度。从而,能够将施加在焊料固定层上的应力设定在弹性极限以下。由此,作用于图3所示的固定层13的剪切应变率Δγ进一步减小。
图4是示出本发明第二实施方式的半导体器件的散热基底构件与绝缘衬底之间的接合状态的图。
在与散热基底构件4接合的绝缘衬底1a和1b的背面,分别设有包括4个和10个分割导体层2c的导体图案。各导体层2c是具有圆角的长方形的图案形状。由此,能够减小将各导体层2c固定到散热基底构件4上的焊料固定层13的尺寸。
即,图3所示的第二金属构件12的长度L减小,从而由上述式1得到的作用于固定层13的剪切应变率Δγ变小。因此,能够防止产生裂纹,进而防止半导体器件热损坏。分割导体层2c的数量不限于4个或10个,1个绝缘衬底可以分割成2个以上的导体层。在此情况下,能获得如上所述的相同效果。
图5是示出本发明第三实施方式的半导体器件的散热基底构件与绝缘衬底之间的接合状态的图。
功率半导体器件具有接合部20,该接合部20从与散热基底构件4接合的绝缘衬底的背面上的导体图案2b的多个分割区域向散热基底构件4突出。在这种情况下,能够减小将各接合部20固定在散热基底构件4上的焊料固定层13的尺寸。
图6是表示本发明第四实施方式的半导体器件的俯视图及纵向剖视图。
在本实施方式中,在内部连接端子73的接合部73a、73b上分别形成有多个圆形突出部7f。同样,在外部引出端子9a、9b的接合部91上分别形成有2个圆形突出部9f。
圆形突出部7f、9f分别通过独立的焊料固定层13而与金属电极3a和导体图案2a接合。由此,焊料固定层13的尺寸减小,从而能够减小作用于固定层13的剪切应变率Δγ。
图7是示出本发明第五实施方式的半导体器件的散热基底构件与绝缘衬底之间的接合状态的图。
本实施方式中,作为对图2所示的第一实施方式和图4所示的第二实施方式的变形,将绝缘衬底1a、1b与散热基底构件4接合的导体图案2b具有2种不同的形状。2个导体图案2b中,图7(A)所示的导体图案2b包括长方形接合部,其在隅角附近的曲率半径为r,且在接合部的每一侧都形成有多个凹形的弯曲部(bend)b。通过实验,曲率半径r可在1mm~10mm的范围内。
关于弯曲部b的尺寸,当隅角附近的曲率半径为r时,优选使弯曲部b的宽度Bw大于等于r,弯曲部b的深度Bd大于等于r。由此,图7(A)所示的导体图案2b构成为使得图3中所示的第二金属构件12的直线部分的长度L减小。优选使弯曲部内侧底部的隅角具有与上述相同的曲率半径。根据这种结构,能够减小隅角的剪切应变率Δγ。
另一方面,图7(B)所示的导体图案具有多个分割导体层2d,且具有六边形的图案形状、或构成一部分六边形的梯形的图案形状。在这种情况下,当平面上导体图案的横向尺寸为Sd时,优选使导体图案2d之间的间隔Sg大于等于0.1×Sd。由此,当分割导体层2d被固定到散热基底构件4上时,能够减小焊料固定层13的尺寸,从而能够减小作用于固定层13的剪切应变率Δγ。多个分割导体层的形状不限于六边形,也可以是具有6条边以上的多边形。该多边形可以是通常的多边形。当分割导体层的形状是具有6条边以上的多边形时,能够减小隅角上的剪切应变率Δγ。另外,使该多边形的角部具有上述曲率半径也是有效的。
上面仅示出了本发明的原理。可由本领域技术人员对本发明作出各种变形和变更。本发明并不限定于上述的结构和应用例,相对应的所有变形及等同物都落入到添附的权利要求及其等同物所定义的本发明的范围中。
标号说明
1 绝缘衬底
2a、2b 导体图案
2c 导体层
3 半导体芯片
4 散热基底构件
5 树脂外壳
6 密封构件
7、70、73 内部连接端子
7f、9f 圆形突出部
8 铝引线
9a、9b 外部引出端子
11 第一金属构件
12 第二金属构件
13、13a、13b 固定层
20、71、72、73a、73b、91 接合部
90 外部连接导体

Claims (5)

1.一种半导体器件,具有如下连接结构:在正面和背面接合有导体图案的绝缘衬底上安装功率半导体芯片,并且将所述绝缘衬底与散热基底构件连接,使得由所述功率半导体芯片产生的热量能够释放到外部,其特征在于,
所述绝缘衬底的背面上的与所述散热基底构件接合的所述导体图案的接合部为长方形,且在隅角附近具有预定的曲率半径,金属端子的接合部为圆形,该金属端子的一端与安装有所述功率半导体芯片的所述绝缘衬底的正面上的所述导体图案接合,
所述金属端子是从安装有所述功率半导体芯片的所述绝缘衬底引出的外部引出端子,并且
所述外部引出端子的接合部具有多个用于与所述绝缘衬底的正面上的所述导体图案独立地接合的突出部。
2.如权利要求1所述的半导体器件,其特征在于,
在与所述散热基底构件接合的所述绝缘衬底的背面,形成有包括多个分割导体层的导体图案。
3.如权利要求1所述的半导体器件,其特征在于,
所述绝缘衬底的背面上的与所述散热基底构件接合的所述导体图案包括接合部,该接合部设置在多个分割区域中,且向所述散热基底构件突出。
4.如权利要求1所述的半导体器件,其特征在于,
所述绝缘衬底的背面上的与所述散热基底构件接合的所述导体图案形成为使得与所述绝缘衬底接合的接合面的周缘部的导电图案的厚度比所述接合部的中心的厚度要小。
5.一种半导体器件,具有如下连接结构:在正面和背面接合有导体图案的绝缘衬底上安装功率半导体芯片,并且将所述绝缘衬底与散热基底构件连接,使得由所述功率半导体芯片产生的热量能够释放到外部,其特征在于,
所述绝缘衬底的背面上的与所述散热基底构件接合的所述导体图案的接合部为长方形,且在隅角附近具有预定的曲率半径,金属端子的接合部为圆形,该金属端子的一端与安装有所述功率半导体芯片的所述绝缘衬底的正面上的所述导体图案接合,
所述金属端子是将所述功率半导体芯片的正面电极与所述导体图案相连接的内部连接端子,并且
所述内部连接端子的各接合部具有多个用于与所述正面电极或所述导体图案独立地接合的突出部。
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Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2662893B1 (en) * 2011-01-07 2020-09-23 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method thereof
JPWO2012157583A1 (ja) * 2011-05-13 2014-07-31 富士電機株式会社 半導体装置とその製造方法
DE102012105110A1 (de) * 2012-06-13 2013-12-19 Osram Opto Semiconductors Gmbh Montageträger und Verfahren zur Montage eines Montageträgers auf einem Anschlussträger
JP6210818B2 (ja) * 2013-09-30 2017-10-11 三菱電機株式会社 半導体装置およびその製造方法
JP6192561B2 (ja) * 2014-02-17 2017-09-06 三菱電機株式会社 電力用半導体装置
JP6395530B2 (ja) * 2014-09-11 2018-09-26 三菱電機株式会社 半導体装置
JP6305302B2 (ja) * 2014-10-02 2018-04-04 三菱電機株式会社 半導体装置およびその製造方法
CN105990265B (zh) * 2015-02-26 2019-04-05 台达电子工业股份有限公司 功率转换电路的封装模块及其制造方法
JP6500162B2 (ja) * 2015-03-23 2019-04-10 広東美的制冷設備有限公司Gd Midea Air−Conditioning Equipment Co.,Ltd. インテリジェントパワーモジュール及びその製造方法
JP6302142B2 (ja) * 2015-07-07 2018-03-28 日立オートモティブシステムズ株式会社 半導体装置、力学量測定装置および半導体装置の製造方法
US20170084521A1 (en) * 2015-09-18 2017-03-23 Industrial Technology Research Institute Semiconductor package structure
JP6584928B2 (ja) * 2015-11-16 2019-10-02 住友電工デバイス・イノベーション株式会社 電子装置
JP6714831B2 (ja) * 2016-03-17 2020-07-01 富士電機株式会社 半導体用基板
JP6743439B2 (ja) * 2016-03-18 2020-08-19 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6724449B2 (ja) * 2016-03-18 2020-07-15 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6621714B2 (ja) * 2016-07-01 2019-12-18 三菱電機株式会社 半導体装置
JP6515886B2 (ja) * 2016-07-08 2019-05-22 株式会社豊田自動織機 半導体モジュール
WO2018021322A1 (ja) * 2016-07-26 2018-02-01 三菱電機株式会社 半導体装置
DE112017003925B4 (de) 2016-08-05 2022-12-22 Mitsubishi Electric Corporation Leistungs-Halbleiterelement
JP6673100B2 (ja) * 2016-08-24 2020-03-25 トヨタ自動車株式会社 半導体装置
JP6870249B2 (ja) * 2016-09-14 2021-05-12 富士電機株式会社 半導体装置および半導体装置の製造方法
CN109952639B (zh) * 2016-11-11 2023-06-27 三菱电机株式会社 半导体装置、逆变器单元及汽车
JP2018182198A (ja) * 2017-04-19 2018-11-15 株式会社東芝 半導体装置
US11257768B2 (en) * 2017-12-13 2022-02-22 Mitsubishi Electric Corporation Semiconductor device and power conversion device
JP7005373B2 (ja) * 2018-02-09 2022-01-21 三菱電機株式会社 パワーモジュールおよび電力変換装置
CN109530838B (zh) * 2018-12-13 2021-05-04 武汉凌云光电科技有限责任公司 一种激光焊接功率半导体芯片的方法
JP2020141023A (ja) * 2019-02-27 2020-09-03 株式会社 日立パワーデバイス 半導体装置
JP7274954B2 (ja) * 2019-06-20 2023-05-17 新電元工業株式会社 半導体装置
EP3761357A1 (en) * 2019-07-04 2021-01-06 Infineon Technologies Austria AG Semiconductor device
JP7424026B2 (ja) 2019-12-13 2024-01-30 三菱マテリアル株式会社 絶縁回路基板
KR20220036534A (ko) * 2020-09-16 2022-03-23 에스케이하이닉스 주식회사 관통 전극을 포함하는 반도체 칩, 및 이 반도체 칩을 포함하는 반도체 패키지
CN114975128A (zh) * 2021-02-25 2022-08-30 珠海零边界集成电路有限公司 一种智能功率模块及其制备方法
DE102022201187A1 (de) 2022-02-04 2023-08-10 Zf Friedrichshafen Ag Leistungsmodul mit einer thermisch optimierten Verbindungssschicht

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1185231A (zh) * 1995-06-12 1998-06-17 松下电器产业株式会社 半导体单元的封装体、其封装方法及其封装材料
CN101312168A (zh) * 2007-05-25 2008-11-26 株式会社丰田自动织机 半导体器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982844A (ja) * 1995-09-20 1997-03-28 Mitsubishi Electric Corp 半導体モジュール基板及びその製造方法
JP2001308226A (ja) * 2000-04-24 2001-11-02 Nec Corp 半導体装置
JP4969738B2 (ja) * 2001-06-28 2012-07-04 株式会社東芝 セラミックス回路基板およびそれを用いた半導体モジュール
US6844621B2 (en) * 2002-08-13 2005-01-18 Fuji Electric Co., Ltd. Semiconductor device and method of relaxing thermal stress
JP4124040B2 (ja) 2002-08-13 2008-07-23 富士電機デバイステクノロジー株式会社 半導体装置
JP4100685B2 (ja) * 2003-08-20 2008-06-11 富士電機デバイステクノロジー株式会社 半導体装置
JP2006245436A (ja) * 2005-03-04 2006-09-14 Hitachi Metals Ltd 窒化珪素配線基板およびこれを用いた半導体モジュール
DE102006014609B4 (de) * 2006-03-29 2021-03-18 Infineon Technologies Ag Halbleiterbauelementeträger
JP5268786B2 (ja) 2009-06-04 2013-08-21 三菱電機株式会社 半導体モジュール

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1185231A (zh) * 1995-06-12 1998-06-17 松下电器产业株式会社 半导体单元的封装体、其封装方法及其封装材料
CN101312168A (zh) * 2007-05-25 2008-11-26 株式会社丰田自动织机 半导体器件

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