JP6714831B2 - 半導体用基板 - Google Patents
半導体用基板 Download PDFInfo
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- JP6714831B2 JP6714831B2 JP2016054361A JP2016054361A JP6714831B2 JP 6714831 B2 JP6714831 B2 JP 6714831B2 JP 2016054361 A JP2016054361 A JP 2016054361A JP 2016054361 A JP2016054361 A JP 2016054361A JP 6714831 B2 JP6714831 B2 JP 6714831B2
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- 239000000758 substrate Substances 0.000 title claims description 179
- 239000004065 semiconductor Substances 0.000 title claims description 107
- 229910052751 metal Inorganic materials 0.000 claims description 170
- 239000002184 metal Substances 0.000 claims description 170
- 229910000679 solder Inorganic materials 0.000 claims description 87
- 230000017525 heat dissipation Effects 0.000 claims description 21
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 10
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- 230000000052 comparative effect Effects 0.000 description 10
- 230000008646 thermal stress Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Description
特許文献1 国際公開2012/157584号パンフレット
特許文献2 特開2001−177053号公報
図2Aは、実施例1に係る絶縁性基板の平面図の一例を示す。図2Bは、実施例1に係る絶縁性基板のA−A'断面図の一例を示す。図2Cは、実施例1に係る半導体用基板100のB−B'断面図の一例を示す。なお、図2Aでは、第1金属板20の形状を示すために、Z軸の負側から見た場合を示している。
図4は、比較例1に係る半導体装置600の構成の一例を示す。本例の半導体装置600は、半導体用基板500および半導体チップ610を備える。半導体用基板500は、絶縁基板510、第1金属板520、第2金属板530、はんだ540および放熱板550を備える。半導体用基板500の上方には、はんだ545を介して、半導体チップ610が接合される。
図6は、実施例2に係る半導体用基板100の構成の一例を示す。本例では、半導体用基板100について、絶縁基板10a,10b、第1金属板20a,20bおよび放熱板50を図示している。その他の構成については、説明を簡略化するために省略している。
図7は、比較例2に係る半導体用基板500の一例を示す。本例では、半導体用基板500について、絶縁基板510a,510b、第1金属板520a,520bおよび放熱板550を図示している。その他の構成については、説明を簡略化するために省略している。放熱板550には、はんだ止め部560およびはんだ止め部565が形成されている。
図8は、実施例3に係る半導体用基板100の構成の一例を示す。本例の半導体用基板100は、実施例2に係る半導体用基板100と第1金属板20bの形状が異なる。
(沿面距離A)≧(第1金属板20の厚さB)+(はんだ40の厚さC)
言い換えると、沿面距離Aが絶縁基板10の下端から放熱板50の上端までの距離以上となる。これにより、半導体用基板100は、はんだ40がはみ出して盛り上がった場合であっても、絶縁性を十分に確保できる。
Claims (14)
- 絶縁基板と、
複数の辺を有し、前記絶縁基板の第1面に形成された第1金属板と、
前記第1金属板を介して前記絶縁基板が載置される矩形の放熱板と、
前記第1金属板の周囲において、前記放熱板の表面に形成されたはんだ止め部と、
を備え、
前記第1金属板は、
前記第1金属板の第1辺の角側に位置し、前記第1金属板の端部と前記絶縁基板の端部との間の沿面距離が、前記第1辺において最小値となる角部と、
前記角部よりも前記第1辺の中央側に位置し、前記第1金属板の端部と前記絶縁基板の端部との間の沿面距離が前記最小値より大きくなる中央部と、
を有し、
前記中央部の範囲は、前記角部の範囲より広く、
前記はんだ止め部の少なくとも一部は、平面視で、前記絶縁基板の下方に形成され、
前記中央部に対応するはんだ止め部は、前記角部に対応するはんだ止め部と不連続に形成されている
半導体用基板。 - 前記絶縁基板の前記第1面と反対側の第2面に形成された第2金属板を更に備え、
前記第2金属板は、前記第1金属板よりも体積が小さい
請求項1に記載の半導体用基板。 - 前記第2金属板は、前記第1金属板と膜厚が等しい
請求項2に記載の半導体用基板。 - 前記中央部の範囲は、前記角部の範囲の1.3倍以上である
請求項1から3のいずれか一項に記載の半導体用基板。 - 前記角部の範囲は、前記第1金属板の最も短い辺の長さの30%以下である
請求項1から4のいずれか一項に記載の半導体用基板。 - 前記角部の範囲は、前記第1金属板の最も短い辺の長さの10%以上である
請求項1から5のいずれか一項に記載の半導体用基板。 - 前記第1金属板は矩形を有し、
前記第1金属板の長辺における前記中央部は、前記第1金属板の短辺における前記中央部よりも大きい
請求項1から6のいずれか一項に記載の半導体用基板。 - 前記第1金属板の長辺における前記角部の範囲は、前記第1金属板の短辺における前記角部の範囲と等しい
請求項7に記載の半導体用基板。 - 前記中央部の沿面距離は、前記角部の沿面距離の1.5倍以上であって、2.5倍以下である
請求項1から8のいずれか一項に記載の半導体用基板。 - 複数の前記絶縁基板と、
複数の前記絶縁基板に対応して配置された複数の前記第1金属板と、
を備え、
複数の前記第1金属板は、複数の前記第1金属板同士が対向する内側辺と、複数の前記第1金属板同士が対向しない外側辺とを有し、
前記放熱板は、複数の前記第1金属板を介して複数の前記絶縁基板が載置され、
前記外側辺は、前記放熱板の長辺と平行に形成される
請求項1から9のいずれか一項に記載の半導体用基板。 - 前記第1金属板は、前記内側辺に対応する前記角部、および前記内側辺に対応する前記中央部を有する
請求項10に記載の半導体用基板。 - 絶縁基板と、
複数の辺を有し、前記絶縁基板の第1面に形成された第1金属板と、
前記第1金属板を介して前記絶縁基板が載置される矩形の放熱板と、
前記第1金属板の周囲において、前記放熱板の表面に形成されたはんだ止め部と、
を備え、
前記第1金属板は、
前記第1金属板の第1辺の角側に位置し、前記第1金属板の端部と前記絶縁基板の端部との間の沿面距離が、前記第1辺において最小値となる角部と、
前記角部よりも前記第1辺の中央側に位置し、前記第1金属板の端部と前記絶縁基板の端部との間の沿面距離が前記最小値より大きくなる中央部と、
を有し、
前記中央部の範囲は、前記角部の範囲より広く、
前記はんだ止め部の少なくとも一部は、平面視で、前記絶縁基板の下方に形成され、
前記中央部に対応するはんだ止め部は、前記角部に対応するはんだ止め部よりも前記第1金属板の内側に形成されている
半導体用基板。 - 前記はんだ止め部は、前記放熱板の表面に形成されたカーボンケガキまたは有機レジストである
請求項1から12のいずれか一項に記載の半導体用基板。 - 前記中央部に対応するはんだ止め部は、前記放熱板の表面に形成されたカーボンケガキであり、
前記角部に対応するはんだ止め部は、前記放熱板の表面に形成された有機レジストである
請求項1から12のいずれか一項に記載の半導体用基板。
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US8957508B2 (en) * | 2011-05-13 | 2015-02-17 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
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