CN103367264A - 一种可避免胶材溢流的封装载板 - Google Patents

一种可避免胶材溢流的封装载板 Download PDF

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CN103367264A
CN103367264A CN2012100844824A CN201210084482A CN103367264A CN 103367264 A CN103367264 A CN 103367264A CN 2012100844824 A CN2012100844824 A CN 2012100844824A CN 201210084482 A CN201210084482 A CN 201210084482A CN 103367264 A CN103367264 A CN 103367264A
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carrier plate
glue material
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CN103367264B (zh
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陈逸男
徐文吉
叶绍文
刘献文
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Nanya Technology Corp
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

本发明公开了一种可避免胶材溢流的封装载板，其特征在于包含一内核层与一设在所述内核层上的阻焊层。所述阻焊层具有一预定的黏晶区域，用来涂布胶材以黏合芯片、一沟渠，沿着所述预定的黏晶区域的外缘分布、一凸起屏障，沿着所述沟渠的外缘分布、以及多个接合指，设置在所述凸起屏障的外侧并从所述阻焊层中裸露出来。

Description

一种可避免胶材溢流的封装载板
技术领域
本发明涉及一种封装结构，特别是涉及一种封装载板，其防焊层上具有特殊的结构可避免胶材溢流。
背景技术
为了要在有限的面积中达到更高的储存容量，动态随机存取存储器(Dynamic Random Access Memory，DRAM)架构开始朝向立体的堆叠式封装技术(3D stacked package)发展，此封装技术的原理在于将多个互连的存储芯片堆叠在一单一的封装载体上，如此将可在同样的面积范围内达到数倍的储存容量。
在封装工序中，会先进行一黏晶步骤将芯片黏在封装载体上，之后芯片的输出入端(I/O)须与外部的封装体电性互连，其多是透过打线接合(wirebonding)方式将芯片上的接合垫(pad)与封装载体上的接合指(finger)电性连接。在打线接合后，封装结构中尚须进行一模封工艺以填入模封材料，使得内部的芯片与外部隔绝。
现在请参照图1，其绘示出根据背景技术中一封装结构的横断面视图。如图1所示，在黏晶工序中，封装载板100预定的黏晶区域上会预先涂布一层胶材101，以将芯片黏合在载板上。对堆叠式封装技术来说，单一的黏晶区域上可以堆叠方式黏上多个芯片，如芯片102a与102b。封装载板100一般是由一内核层100a和上下两面的阻焊层100b所构成，其内部并有预先形成的导电线路，如裸露出阻焊层中的接合指104部位，以与芯片上的接合垫105打线接合。
对此黏晶工序来说，上述黏晶用的胶材101多以印刷工艺涂布在封装载板100上，故会使用流动性佳的胶材。然而，流动性胶材虽然便于印制，但却容易在工序中溢流到黏晶区域外侧，污染到裸露的接合指104部位，影响后续打线接合工序的进行以及模封材料106与封装载板100的结合。严重者甚至会造成接合线107脱离、模封材料106脱层或剥离等问题，导致电路失效。
对于上述问题，目前业界多采用芯片贴装薄膜(die attached film，DAF)的高阶封装工艺来解决，其透过直接在芯片上黏贴一层尺寸裁切成与芯片相同的黏膜来将芯片黏在载板上，不会有胶材流动的污染问题。然而，此芯片贴装薄膜工艺的成本较高，且易有掉晶问题(die lost)发生。故此，目前业界仍须改善现有的封装结构或方法，以解决习知的溢胶问题。
发明内容
有鉴于上述背景技术易发生的溢胶问题，本发明的主要目的在提供一种新颖的封装载板，其通过在封装载板的助焊层上设计出可阻挡溢胶的结构，避免溢胶流动至外侧裸露出阻焊层的接合指处。
根据本发明的优选实施例，本发明提供了一种可避免胶材溢流的封装载板，其特征在于包含一内核层与一设在所述内核层上的阻焊层。所述阻焊层具有一预定的黏晶区域，用来涂布胶材以黏合芯片、一沟渠，沿着所述预定的黏晶区域的外缘分布、一凸起屏障，沿着所述沟渠的外缘分布、以及多个接合指，设置在所述凸起屏障的外侧并从所述阻焊层中裸露出来。
本发明通过简单的工序在载板上的阻焊层形成特殊地形结构，即可使胶材无法溢流至外侧裸露的输出入端，达成发明功效，而不须使用成本较高的芯片贴装薄膜工艺。
附图说明
图1绘示出背景技术中封装结构中的胶材溢流至外侧接合指处的横断面示意图。
图2为依据本发明优选实施例所绘示的封装载板结构的部分横断面放大图。
图3绘示出依据本发明优选实施例封装载板结构阻挡胶材溢流的横断面示意图。
图4绘示出依据本发明优选实施例整个封装结构的横断面示意图。
其中，附图标记说明如下：
100        封装载板        203        黏晶区域
100a       内核层          204        接合指
100b       阻焊层          205        焊锡凸块
101        胶材            206        沟渠
102a/102b  芯片            207        凸起屏障
104        接合指          208        胶材
105        接合垫          209a/209b  芯片
106        模封材料        210        接合线
107        接合线          211        胶材
200        封装载板        212        接合垫
201        内核层          213        模封材料
202        阻焊层
具体实施方式
下文中将以图示来说明本发明的优选实施例。首先，请参照图2，其绘示出依据本发明优选实施例中一可避免胶材溢流的封装载板结构设计的部分横断面放大图。如图2所示，本发明的封装载板200包含一内核层201以及覆盖在内核层201上下两面的阻焊层202。内核层201的材质可为塑料或陶瓷材料，阻焊层202则可为阻焊绿漆等。阻焊层202上设有一预定的黏晶区域203，如封装载板200的中间区域。黏晶区域203于后续的黏晶工艺中会涂布上一层胶材，以黏上芯片。黏晶区域203外侧的封装载板200上会设置有接合指(bond finger)204，其自阻焊层202的开口裸露出来。黏晶工艺后的打线接合步骤会将接合指204电性连接至所黏上的芯片的输出入端，如一对应的接合垫(pad)。而整个封装结构则可进一步通过封装载板200下侧所布设的焊锡凸块(bump)205来与一外部装置(如主机板)电性连接。如此，芯片即可以通过封装载板200传入或传出信号。
在本发明中，芯片黏合面的阻焊层202具有特别的结构设计，如图2所示，在预定黏晶区域203与接合指204之间的阻焊层202部位会设计成具有凹凸的表面地形。其中，阻焊层202中会形成一沟渠206结构沿着预定的黏晶区域203外缘分布，以及形成一凸起屏障207沿着沟渠206的外缘分布。如此，封装载板200的预定黏晶区域203与接合指204之间会隔有沟渠206与凸起屏障207结构。
上述沟渠206与凸起屏障207结构可通过对阻焊层202进行光刻工艺而形成。举例来说，先形成一厚度较一般厚的上阻焊层202，再连续进行两次的光刻工艺在上述预定位置依序分别形成沟渠206与凸起屏障207结构。
接着请参照图3，其绘示出依据图2中所形成的特殊结构来阻挡胶材溢流的横断面示意图。如图3所示，黏晶工序期间，封装载板200的预定黏晶区域203上会先涂布一层胶材208，以于后续步骤中黏合芯片209a。对此，由于胶材208多会以印刷工艺印制在封装载板200上，故会使用流动性佳的胶材，如环氧树脂胶。此类胶材在未经烘烤或固化工序之前，会因为流动性佳的缘故从中间预定的黏晶区域203向封装载板200外缘扩散。再者，当芯片209a压合到胶材208上时，胶材208也有可能受到挤压而往旁边扩散。最严重的状况，胶材208甚至有可能流动到接合指204位置处而将其遮蔽，影响到后续打线接合工艺的进行。对此，阻焊层202上的沟渠206与凸起屏障207的存在将有助于遏止胶材208的流动或将其阻绝在内侧的区域。沟渠206提供了部分的胶材208容置空间，使得一定量溢流的胶材208可以流入沟渠206中，减少或遏止溢流量。进一步的，若胶材溢流量大到沟渠206空间无法容纳，则设置在沟渠206外缘、高于阻焊层202水平的凸起屏障207将可起到阻绝溢流的功效，如同水坝一般。如此，外侧的接合指204将不会受到溢流的胶材208污染，得以与接合线210顺利地接合。
须注意，对于立体的堆叠式封装技术来说，黏晶区域203上多会层叠上多个芯片，如图3中芯片209a与芯片209b通过一胶材211黏合。此胶材211如同胶材208也可能向外溢流沿着芯片209a的侧壁而下。对此，阻焊层202上的沟渠206与凸起屏障207同样能起到阻隔的功效。
请参照图4，其绘示出依据本发明优选实施例整个封装结构的横断面示意图。如图4所示，封装载板200预定的黏晶区域203上涂布有胶材208来黏合芯片209a，芯片209a则通过胶材211黏合另一芯片209b形成芯片堆叠结构。封装载板200的内核层201上下两面各覆盖有阻焊层202，并于黏晶区域203的外侧裸露出接合指204部位，上述接合指204并与芯片209a及209b上的接合垫212藉由接合线210接合。对本发明来说，介于黏晶区域203与接合指204部位之间阻焊层202的沟渠206与凸起屏障207有效遏止了胶材208的溢流，使打线接合动作得以顺利的进行。于封装工序的最后，整个封装结构，包括芯片209a与209b以及封装载板200，会置入一模套(未示于图中)中，模封材料213会通入模套中固化，进而密封并固定封装结构中裸露的组件，如接合线210。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

1.一种可避免胶材溢流的封装载板，其特征在于，包含：
一内核层；
一阻焊层，设在所述内核层上，所述阻焊层具有：
一预定的黏晶区域，用来涂布胶材以黏合芯片；
一沟渠，沿着所述预定的黏晶区域的外缘分布；
一凸起屏障，沿着所述沟渠的外缘分布；以及
多个接合指，设置在所述凸起屏障的外侧，并从所述阻焊层中裸露出来。
2.如权利要求1所述的可避免胶材溢流的封装载板，其特征在于，所述胶材会向外流动至所述沟渠中。
3.如权利要求2所述的可避免胶材溢流的封装载板，其特征在于，所述凸起屏障阻挡所述胶材向外侧溢流至所述多个接合指处。
4.如权利要求1所述的可避免胶材溢流的封装载板，其特征在于，所述接合指经由打线接合电性连接至所述芯片上的接合垫部位。
5.如权利要求1所述的可避免胶材溢流的封装载板，其特征在于，所述胶材为环氧树脂。
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