CN108231704B - 半导体模块 - Google Patents
半导体模块 Download PDFInfo
- Publication number
- CN108231704B CN108231704B CN201711326343.7A CN201711326343A CN108231704B CN 108231704 B CN108231704 B CN 108231704B CN 201711326343 A CN201711326343 A CN 201711326343A CN 108231704 B CN108231704 B CN 108231704B
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- Prior art keywords
- die
- semiconductor
- conductor
- pad
- conductive
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Abstract
本发明提供一种抑制剥离和动作不合格的半导体模块。半导体模块(2)具备:PCB基材部(16)、设置在PCB基材部(16)上的导体裸片焊盘(11b)、设置在导体裸片焊盘(11b)上的半导体裸片(12a)、将导体裸片焊盘(11b)与半导体裸片(12a)电连接的导电性裸片粘合剂(14a)、设置在PCB基材部(16)上的引线键合焊盘(18)、将引线键合焊盘(18)与半导体裸片(12a)电连接的引线(13)、以及将导体裸片焊盘(11b)、半导体裸片(12a)、导电性裸片粘合剂(14a)、引线键合焊盘(18)和引线(13)密封的密封树脂(17)。而且,俯视时,导体裸片焊盘(11b)的面积在5.0mm2以下。
Description
技术领域
本发明涉及半导体模块。
背景技术
将设置在导体裸片焊盘上的半导体裸片用树脂密封而得到的半导体模块已为公众所知。由于树脂的热传导性较差,因此一般通过增大导体裸片焊盘来散发半导体裸片所产生的热量。
发明内容
发明所要解决的技术问题
然而,当在高温多湿的环境下进行回流来实施压力测试时,确认在连接半导体裸片与导体裸片焊盘的导电性裸片粘和剂与导体裸片焊盘之间发生了剥离。还确认了动作不合格及增益值变动等动作不合格的情况。
本发明是鉴于上述问题而完成的,其目的在于提供一种能够抑制导电性裸片粘和剂与导体裸片焊盘或半导体裸片之间的剥离和动作不合格的半导体模块。
解决技术问题的技术方案
本发明的一方面所涉及的半导体模块具备:基板;设置在该基板上的导体裸片焊盘;设置在该导体裸片焊盘上的半导体裸片;将导体裸片焊盘和半导体裸片电连接的导电性裸片粘合剂;设置在基板上的引线键合焊盘;将该引线键合焊盘和半导体裸片电连接的引线;以及至少对导体裸片焊盘、半导体裸片、导电性裸片粘合剂、引线键合焊盘和引线进行密封的密封树脂。而且,导体裸片焊盘的面积在俯视时为5.0mm2以下。
本发明的一方面所涉及的半导体模块具备:基板;设置在该基板上且表面材质为Cu的导体裸片焊盘;设置在该导体裸片焊盘上的半导体裸片;将导体裸片焊盘和半导体裸片电连接的导电性裸片粘合剂;设置在基板上且表面材质为包含Au在内的金属的引线键合焊盘;以及将该引线键合焊盘与半导体裸片电连接的引线。
本发明的一方面所涉及的半导体模块具备:基板;设置在该基板上的第一导体裸片焊盘;设置在该基板上且与第一导体裸片焊盘相邻并间隔的第二导体裸片焊盘;半导体裸片;以及与第一导体裸片焊盘、第二导体裸片焊盘及所述第一导体裸片焊盘和所述第二导体裸片焊盘之间的间隙中的基板相接触并将第一导体裸片焊盘及第二导体裸片焊盘同半导体裸片电连接的导电性裸片粘合剂。
发明效果
根据本发明,能够提供一种抑制导电性裸片粘合剂与导体裸片焊盘、半导体裸片之间的剥离的半导体模块。
附图说明
图1(a)~图1(d)是比较例及实施方式所涉及的半导体模块的平面简图。
图2(a)、图2(b)是比较例所涉及的半导体模块1’的剖视图。
图3是实施方式1所涉及的半导体模块2的剖视图。
图4(a)、图4(b)是实施方式2所涉及的半导体模块3的剖视图。
图5是实施方式3所涉及的半导体模块4的剖视图。
图6(a)、图6(b)是表示导体裸片焊盘(及导电性裸片粘合剂)的面积与高温多湿压力测试的结果的曲线图。
图7(a)、图7(b)是表示俯视时导体裸片焊盘与半导体裸片之间的距离及高温多湿压力测试的结果的曲线图。
图8是形成为倒梯形的导体裸片焊盘11e的边缘。
图9是表示抑制了浸润扩散的导电性裸片粘合剂14d的俯视图。
图10是在多个散热用过孔19d上设置导体裸片焊盘11b的俯视图。
图11是形成有止流用的槽20的PCB基材部16的剖视图。
图12(a)、图12(b)是在互相间隔地形成的导体裸片焊盘11f上设置半导体裸片12a的俯视图。
图13是实施方式5所涉及的半导体模块5的剖视图。
图14(a)、图14(b)是表示实施方式5所涉及的半导体模块5的制造工序的图。
图15是导体裸片焊盘表面的材质为NiPdAu时与导体裸片焊盘表面的材质为Cu时的高温多湿压力测试后的增益变动值的比较图。
具体实施方式
下面,参照附图,对本发明的实施方式进行详细说明。对于与比较例或其它实施方式功能相同或结构相同的要素,简化说明或省略说明。以下的实施方式是用于说明本发明的例示,本发明并不限定于该实施方式。而且,在不脱离本发明宗旨的范围内,可以进行种种变形。
图1(a)~图1(d)是简要地表示比较例所涉及的半导体模块1和各实施方式所涉及的半导体模块2、3、4的俯视图。
图1(a)是比较例所涉及的半导体模块1,其具备:PCB基材部16(基板)、配置在PCB基材部16上的导体裸片焊盘11a、配置在导体裸片焊盘11a上的2个半导体裸片12a和12b、以及用于将这些半导体裸片12a和12b、导体裸片焊盘11a电连接的导电性裸片粘合剂(导电性粘合剂)(未图示)。还具备将这些半导体裸片12a和12b相互电连接或者与其它金属布线(未图示)电连接的多根引线13。而且,这些要素还被密封树脂(未图示)密封。
图1(b)是实施方式1所涉及的半导体模块2。该半导体模块2的导体裸片焊盘11b形成为在俯视时面积比比较例的导体裸片焊盘11a要小。因此,半导体裸片12a、12b的边界到导体裸片焊盘11b的边界的距离比比较例的情况要小。涂布在导体裸片焊盘11b上的导电性裸片粘合剂(未图示)的面积也变小。关于半导体模块2,还会在后文中进行说明。
图1(c)是实施方式2所涉及的半导体模块3。该半导体模块3的导体裸片焊盘11c同与之相邻的导体裸片焊盘11c’之间隔开间隔地形成。从而在各导体裸片焊盘11c和11c’上分别设置半导体裸片12b和12a。相邻的半导体裸片12a和12b通过至少一根引线13电连接。关于半导体模块3,还会在后文中进行说明。
图1(d)是实施方式3所涉及的半导体模块4。该半导体模块4的相邻的半导体裸片12a和12b中,半导体裸片12b无需确保从底面的电连接。因此,虽然设置了经由导电性裸片粘合剂(未图示)而与半导体裸片12a电连接的导体裸片焊盘11d,但并未设置半导体裸片12b用的导体裸片焊盘。半导体裸片12b通过绝缘性裸片粘合剂与PCB基材部16直接连接,或者经由阻焊剂(未图示)连接。关于半导体模块4,还会在后文中进行说明。
图2(a)是其它比较例所涉及的半导体模块1’的剖视图。如图所示,半导体模块1’具备:PCB基材部16(基板)、配置在PCB基材部16上的导体裸片焊盘11a、配置在导体裸片焊盘11a上的半导体裸片12a、以及将导体裸片焊盘11a与半导体裸片12a电连接的导电性裸片粘合剂14a。PCB基材部16上还形成有与导体裸片焊盘11a相邻且隔开间隔的引线键合焊盘18及与该引线键合焊盘18相连的金属布线。该引线键合焊盘18和半导体裸片12a通过引线13电连接。与该引线键合焊盘18相连的金属布线受阻焊剂15的保护。而且,这些要素还被密封树脂17密封。
对该半导体模块1’在高温多湿(例如气温在80℃以上且湿度在80%以上)的环境下实施进行多次250℃以上的回流的压力测试(以下称为高温多湿压力测试),如图2(b)所示,发现在导电性裸片粘合剂14a与导体裸片焊盘11a之间发生了剥离100。还确认了在导电性裸片粘合剂14a与半导体裸片12a之间发生剥离的情况、在密封树脂17与导体裸片焊盘11a之间发生剥离的情况。此外,还确认了动作不合格、增益值变动等特性方面不合格的情况发生。
发明人使用了不同形状和大小的半导体裸片、导体裸片焊盘实施高温多湿压力测试,并努力探讨其原因,得出如下结果:导电性裸片粘合剂是造成一连串剥离和动作不合格等的主要原因。而且,还发现无论半导体裸片是何种大小和形状,通过减小导体裸片焊盘的面积,都能有效地抑制上述不良情况的发生。
图3~图5是实施方式1~3所涉及的半导体模块2、3、4的剖视图,分别公开了能够减小导体裸片焊盘的面积的方式。各方式可以与其它方式组合使用,也可以独立地使用。下面,在对各半导体模块2、3、4的结构进行了说明之后,说明其效果。
图3是实施方式1所涉及的半导体模块2的剖视图。
如上所述,导体裸片焊盘11b与比较例的导体裸片焊盘11a的不同点在于,导体裸片焊盘11b设计成在俯视时的面积小于比较例的导体裸片焊盘11a。具体而言,比较例的导体裸片焊盘11a的面积约为6.1mm2,而本实施方式的导体裸片焊盘11b的面积约为5.0mm2。调整导电性裸片粘合剂14a的预留量和粘性,以使其不会从导体裸片焊盘11a溢出,因此导电性裸片粘合剂14a俯视时的面积也约为5.0mm2。
随着导体裸片焊盘11b(及导电性裸片粘合剂14a)的面积减小,俯视时导体裸片焊盘11b(及导电性裸片粘合剂14a)的边界到半导体裸片12a的边界的距离X也减小。
这里,俯视时导体裸片焊盘11b的边界到半导体裸片12a的边界的距离X是指构成导体裸片焊盘11b(及导电性裸片粘合剂14a)的边界的各边与相应的半导体裸片12a的各边之间的垂直距离中最小的距离。因此,俯视时导体裸片焊盘11b的上边到半导体裸片12a的上边的距离为0.1mm,导体裸片焊盘11b的其它边到半导体裸片12a的相应的其它边的距离为0.3mm的情况下,距离X为0.1mm。比较例中的半导体模块10的距离X为0.125mm,而半导体模块2的距离X为0.07mm。
这样减小导体裸片焊盘11b(及导电性裸片粘合剂14a)的面积而带来的实施方式效果将在后文叙述。
图4(a)是实施方式2所涉及的半导体模块3的剖视图。从实施方式2开始,对于和实施方式1或比较例通用的事项,将省略其说明,而是对不同之处进行说明。尤其是同样的结构带来的同样的作用效果,每一个实施方式中不再逐个地提及。
该半导体模块3与实施方式1所涉及的半导体模块2相比,不同点在于导体裸片焊盘11c同与之相邻的导体裸片焊盘11c’(第二导体裸片焊盘)隔开间隔地形成。而且在各导体裸片焊盘11c’和11c上分别设置半导体裸片12a和12b(第二半导体裸片)。相邻的半导体裸片12a和12b通过至少一根引线13(第二引线)电连接。
通过这样在由引线13连接的相邻的多个半导体裸片12a和12b上分别设置隔开间隔形成的多个导体裸片焊盘11c和11c’,能够减小导体裸片焊盘的面积。调整导电性裸片粘合剂14a和14c(第二导电性裸片粘合剂)的量及粘性,使其在表面张力的作用下不会从各导体裸片焊盘11c及11c’溢出。因此,随着导体裸片焊盘的面积减小,导电性裸片粘合剂的面积也能够减小。
图4(b)是实施方式2所涉及的半导体模块3的变形例即半导体模块3a的剖视图。
该半导体模块3与半导体模块2相比,在导体裸片焊盘11b中位于相邻的半导体裸片12a与12b(第三半导体裸片)之间的区域上设有阻焊剂15。因此,导电性裸片粘合剂14a和14b(第三导电性裸片粘合剂)被阻焊剂15所遮挡,其结果是能够使导电性裸片粘合剂14a和14b的表面积能够减小到4.9mm2。
另外,由于阻焊剂15靠近半导体裸片12a和12b设置,因此,俯视时导电性裸片粘合剂14a及14b的边界到半导体裸片12a的距离能够进一步减小,例如能够变为X=0.04~0.06mm。
图5是实施方式3所涉及的半导体模块4的剖视图。
该半导体模块4与实施方式1的半导体模块2相比,不同之处在于导体裸片焊盘11d的一部分上设有阻焊剂15’(第二阻焊剂),该阻焊剂15’与半导体裸片12b通过绝缘性裸片粘合剂14b(绝缘性裸片粘合剂)连接。
通过这样将不需要与底面电连接的半导体裸片12b设置在阻焊剂15上,能够抑制导电性裸片粘合剂14a扩散而导致的其表面积变大。由于使用绝缘性裸片粘合剂14b,因此能够抑制导电性裸片粘合剂所占的面积。
图6(a)表示导体裸片焊盘(及导电性裸片粘合剂)的面积与高温多湿压力测试时的剥离发生率的关系。
图6(b)表示导体裸片焊盘(及导电性裸片粘合剂)的面积与高温多湿压力测试时的动作不合格率的关系。
如图6(a)和图6(b)所示,导体裸片焊盘(及导电性裸片粘合剂)的面积为6.1mm2时(比较例),产品总面积的60%以上的部分发生了密封树脂剥离,且40%以上的半导体模块动作不合格。
另一方面,在导体裸片焊盘11b(及导电性裸片粘合剂14a)的面积为5.0mm2时(实施方式1),差不多产品总面积的不到40%发生了密封树脂的剥离且差不多不到10%的半导体模块的动作不合格。
还确认了即使使半导体裸片12a的大小不同,在导体裸片焊盘11b(及导电性裸片粘合剂14a)的面积为5.0mm2时,剥离及动作不合格的情况也减少了。例如,在半导体裸片12a的尺寸为例如1.16mmX1.06mm的情况下,确认了上述效果。
而且,在导体裸片焊盘11c和11c’(及导电性裸片粘合剂14a和14b)的面积之和为4.9mm2时(实施方式2及其变形例),也确认了剥离和动作不合格的情况进一步减少。尤其是动作不合格率变为了0%。
此外,在导体裸片焊盘11c的面积为3.2mm2的情况下(实施方式3),也确认了剥离和动作不合格的情况进一步减少。尤其能使剥离发生率和动作不合格率双方都为0%。
通过将上述结构加以组合,对多种结构实施同样的高温多湿压力测试,其结果是通过减小导体裸片焊盘的面积,能够定性地减少剥离和动作不合格的情况发生。例如,在导电性裸片粘合剂的表面积为5.0mm2以上时,与比较例的结构相比,如实施方式2所示,通过引线电连接的相邻的半导体裸片之间的区域不存在导电性裸片粘合剂,通过采用这样的结构,与存在导电性裸片粘合剂的情况相比,能够发挥减少剥离和动作不合格的效果。同样,在导电性裸片粘合剂的表面积为5.0mm2以上时,与比较例的结构相比,如实施方式3所示,对无需确保从底面的电连接的半导体裸片使用绝缘性裸片粘合剂,从而与使用导电性裸片粘合剂的情况相比,能够发挥减少剥离和动作不合格的效果。其中,高温多湿压力测试下的动作不合格率与半导体裸片的尺寸无关,通过将导体裸片焊盘(及导电性裸片粘合剂)的表面积设为5.0mm2以下,能飞跃性地降低上述动作不合格率。
图7(a)表示距离X与高温多湿压力测试时的剥离发生率之间的关系。
图7(b)表示距离X与高温多湿压力测试时的动作不合格率之间的关系。
这些测试结果可通过进一步减小半导体模块2的导体裸片焊盘11b的尺寸等来导出。
如图7(a)和图7(b)所示,X为0.125mm时(比较例),产品总面积的60%以上的部分发生了密封树脂剥离,且40%以上的半导体模块动作不合格。
另一方面,在X为0.07mm的情况下,差不多产品总面积的不到40%发生了密封树脂的剥离,且不到10%的半导体模块动作不合格。
还确认了在X为0.07mm的情况下,即使改变半导体裸片12a的尺寸,也能够减轻剥离及动作不合格。
通过将X进一步减小为0.06mm,能够使动作不合格率为0%,通过将X进一步减小为0.04mm,能够使剥离发生率也减小至0%。
通过这样减小俯视时半导体裸片的边界到导体裸片焊盘的边界(及从此处溢出的导电性裸片粘合剂的边界)的距离X,能够减少剥离和动作不合格的情况发生。这是因为,导电性裸片粘合剂中位于导体裸片焊盘与半导体裸片之间的间隙的部分与位于半导体裸片外部的导体裸片焊盘与密封树脂之间的间隙的部分相比时,后者的导电性裸片粘合剂更会造成与密封树脂的剥离及动作不合格。将导体裸片焊盘的面积设为5.00mm2以下能够发挥上述效果,但在导体裸片焊盘的面积大于5.00mm2的情况下,通过减小距离X也能发挥上述效果。
如上所述,在导体裸片焊盘与电连接半导体裸片的导电性裸片粘合剂被树脂密封的结构中,通过使导体裸片焊盘及导电性裸片粘合剂的面积为5.00mm2以下,与将其设为5.00mm2以上的情况相比,能够将动作不合格的情况减小30%左右。对半导体模块内的所有或几乎所有半导体裸片焊盘适用上述设定时能够发挥其效果,但并不限于此,也可以仅适用于一部分导体裸片焊盘及导电性裸片粘合剂(例如包含在半导体模块中的设有导电性裸片粘合剂的导体裸片焊盘的至少半数)。另外,导电性裸片粘合剂的一部分也可以从导体裸片焊盘溢出。
若减小导体裸片焊盘的面积,则导电性裸片粘合剂会从导体裸片焊盘流出,与引线键合焊盘18接触,从而导致动作不合格的可能性变高。
因此,也可以如图8所示,将导体裸片焊盘11e的边缘设为倒梯形(离PCB基材部16的表面越远就越宽的形状),在与PCB基材部16的表面垂直的截面中,使其与PCB基材部16的接触角α为钝角,从而增加与导电性裸片粘合剂14a之间的表面张力,抑制导电性裸片粘合剂14a的流出。
这样的导体裸片焊盘11e的制造方法如下所述。首先,在未设置导体裸片焊盘11e的PCB基材部16的表面粘贴掩模(未图示)。掩模与PCB基材部16的表面成锐角的接触角。在粘贴了该掩模的状态下,通过蒸镀等形成导体裸片焊盘11e。由于掩模与PCB基材部16的表面成锐角的接触角,因此导体裸片焊盘11e能够形成为具有钝角的接触角α的倒梯形。
由此,通过将导体裸片焊盘11e的边缘形成为倒梯形,从而能够增大其与导电性裸片粘合剂的接触角,能够抑制导电性裸片粘合剂的流出,因此能够减小导体裸片焊盘11e的面积。其结果是,能够减小露出于密封树脂17并与之相对的导电性裸片粘合剂的面积,能够抑制因该导电性裸片粘合剂造成的剥离。
并不一定要导体裸片焊盘11e的所有边缘都为倒梯形,也可以仅一部分边缘为倒梯形。
另外,也可以将导电性裸片粘合剂的材质变更为热传导率高于以往的材质。在比较例的情况下,为了满足所要求的散热特性,在半导体裸片12a的整个底面上使导电性裸片粘合剂14a浸润扩散。而通过导入热传导率较高的导电性裸片粘合剂、例如2.5[W/m·K]以上的导电性裸片粘合剂14d,从而减小导电性裸片粘合剂的面积也能满足要求。
也可以如图9所示,例如导电性裸片粘合剂14d全部或基本全部集中在俯视时设置于导体裸片焊盘11b上的半导体裸片12a所占据的区域内。换言之,也可以是以下状态:俯视时,导体裸片焊盘11b所占据的区域中从密封树脂露出的外部边缘区域(第四区域)包围被导电性裸片粘合剂14d覆盖的区域(第三区域)。
还可以如图10所示,为了提高散热性,俯视时在导电性裸片粘合剂14e所占据的区域内形成多个散热用的过孔19d。形成于基板的过孔19d内填充有金属,因此散热效果较高。因而,通过设置导体裸片焊盘11b和导电性裸片粘合剂14e,使得导电性裸片粘合剂14e所占据的区域内包含多个过孔19d,从而能够减小导电性裸片粘合剂14e的浸润扩散面积,抑制其从导体裸片焊盘11b流出,同时又维持散热特性。
也可以将热传导率高的导电性裸片粘合剂14d与上述结构组合使用,从而能够进一步减小导电性裸片粘合剂14d的浸润扩散面积。
另外,通过导入粘度更高的导电性裸片粘合剂14e,也能减小浸润扩散的面积。例如,即使在使用通常粘性的导电性裸片粘合剂(第六导电性裸片粘合剂)时该导电性裸片粘合剂从导体裸片焊盘11b溢出并与PCB基材部16接触的情况下,通过使用粘性更高(例如8000[cP]以上)的导电性裸片粘合剂14e,也能够更高地保持接触角并抑制浸润扩散。
还可以在至少剥离发生可能性较高的区域使用导电DAF(Die Attach Film:芯片粘接薄膜)来代替导电性裸片粘合剂,以连接半导体裸片和导体裸片焊盘。从而能够消除浸润扩散。
还可以如图11所示,在PCB基材部16中形成槽20,从而阻止从导体裸片焊盘11b流出的导电性裸片粘合剂14c的浸润扩散。例如,通过在半导体裸片12a与经由引线13连接的引线键合焊盘18之间的PCB基材部16的表面形成槽20,即使有导电性裸片粘合剂14c流出,也会流入槽20内,因此能够抑制动作不合格的情况发生。
上述各种结构既可以单独使用,也可以组合使用。还可以不考虑导体裸片焊盘(及导电性裸片粘合剂)的面积来适用。
下面,对实施方式4进行说明。
从实施方式4开始,对于和实施方式1通用的事项,将省略其说明,而是对不同之处进行说明。尤其是同样的结构带来的同样的作用效果,每一个实施方式中不再逐个地提及。
本实施方式的半导体模块具有半导体裸片和隔开间隔形成的多个半导体裸片焊盘通过导电性裸片粘合剂粘接的结构。导电性裸片粘合剂至少将一个导体裸片焊盘与半导体裸片电连接,且将与该导体裸片焊盘隔开间隔形成的其它导体裸片焊盘与半导体裸片电连接,而且,该导体裸片焊盘之间的位于半导体裸片与基板间的区域也设有导电性裸片粘合剂。
例如图12(a)所示,具备彼此隔开间隔形成的9个导体裸片焊盘11f、以及经由导电性裸片粘合剂14a(未图示)与各导体裸片焊盘11f的至少一部分电连接的半导体裸片12a。因此在俯视时,各导体裸片焊盘11f的至少一部分与半导体裸片12a有重叠的区域。
通过这样设置细分成网格状图案的导体裸片焊盘11f,导电性裸片粘合剂14a不仅将各导体裸片焊盘11f与半导体裸片12a电连接,还与位于两者间隙的高度和材质都不同于导体裸片焊盘11f的PCB基材部16的表面接触,因此利用其高低差产生的锚固效应提高粘接力,从而能够抑制剥离。
也可以如图12(b)所示,将网格状图案的导体裸片焊盘11f设计成与贯穿PCB基材部16的一部分或全部的过孔19d连接的圆环状的导体裸片焊盘11f’,从而形成通孔盘的形状。这种情况下,除了具有锚固效应之外,还可以期待通孔盘的散热效果,因此能够期待随着导电性裸片粘合剂14a的浸润扩散被抑制而防止剥离发生的效果。
下面,对实施方式5进行说明。
如图13所示,该半导体模块5在PCB基材部16(基板)上具备导体裸片焊盘11g和设置在导体裸片焊盘11g上的半导体裸片12a,导体裸片焊盘11g和半导体裸片12a通过导电性裸片粘合剂14a电连接。而且,与导体裸片焊盘11g相邻地形成有引线键合焊盘18和与之相连的金属布线,半导体裸片12a和引线键合焊盘18通过引线13电连接。半导体裸片12a、导体裸片焊盘11g、导电性裸片粘合剂14a、引线13、引线键合焊盘18等被密封树脂17密封。
本实施方式中,引线键合焊盘18由表面电镀了NiPdAu等Au或含Au合金的Cu构成。因此,能够适合与尤其是由金等形成的引线13接合。
另一方面,作为引线13另一端的设有半导体裸片12a的导体裸片焊盘11g没有被电镀含Au的合金,其包括表面在内都由Cu构成。而且,导体裸片焊盘11g的材质Cu与半导体裸片12a通过导电性裸片粘合剂14d电连接。
这样的结构可以由图14(a)、图14(b)所示的方法来制造。
首先,在PCB基材部16上用Cu来形成引线键合焊盘18和与之连接的布线、导体裸片焊盘11g。
然后,在除了引线键合焊盘之外的布线上涂布阻焊剂对其进行保护。
接着,在想要露出Cu的导体裸片焊盘11g上粘贴掩膜21,并在此状态下将其放入Au镀液槽来进行镀Au(图14(a))。
其结果是,粘贴了掩膜21的导体裸片焊盘11g包括其表面材质在内都由Cu构成,引线键合焊盘18的表面电镀了NiPdAu。
之后,利用导电性裸片粘合剂14a将半导体裸片12a接合到导体裸片焊盘11g上,并用密封树脂17密封全体。
通过上述工序,能够得到上述半导体模块5。
也可以如图14(b)所示,不粘贴掩膜21,而是在导体裸片焊盘11g的表面镀了Au之后,使用激光器22来去除镀层以使Cu面露出。
图15是导体裸片焊盘表面的材质为NiPdAu时与导体裸片焊盘表面的材质为Cu时的高温多湿压力测试后的增益变动值的比较曲线图。如该图所示,前者的增益变动值在1.6dB以上,而后者的增益变动值能实现小于1dB。
以上对本发明的示例性的实施方式进行了说明。
这样的半导体模块1具备:PCB基材部16、设置在该基板上的导体裸片焊盘11b、设置在该导体裸片焊盘11b上的半导体裸片12a、将导体裸片焊盘11b与半导体裸片12a电连接的导电性裸片粘合剂14a、设置在PCB基材部16上的引线键合焊盘18、将该引线键合焊盘18与半导体裸片12a电连接的引线13、以及至少对导体裸片焊盘11b、半导体裸片12a、导电性裸片粘合剂14a、引线键合焊盘18及引线13进行密封的密封树脂17,俯视时,导体裸片焊盘11b的面积在5.0mm2以下。
通过采用上述结构,能够提供一种抑制导电性裸片粘合剂与导体裸片焊盘、半导体裸片之间的剥离和动作不合格的半导体模块。
俯视时,导体裸片焊盘11b的边界到半导体裸片12a的距离X的最小值可以在0.07mm以下。
通过采用上述结构,能够减少从半导体裸片12a露出并从密封树脂17露出的导电性裸片粘合剂14a的量,因此能够抑制剥离。
另外,可以在PCB基材部16上设置与导体裸片焊盘11c’相邻且隔开间隔设置的导体裸片焊盘11c、设置在该导体裸片焊盘11c上的半导体裸片12b、将导体裸片焊盘11c与半导体裸片12b电连接的导电性裸片粘合剂14c、以及将半导体裸片12a与半导体裸片12b电连接的引线13。
通过采用上述结构,在相邻的半导体裸片之间也分割了导体裸片焊盘,因此能够抑制导电性裸片粘合剂的浸润扩散。
另外,也可以在导体裸片焊盘11b上设置与半导体裸片12a相邻的半导体裸片12b、将导体裸片焊盘11b与半导体裸片12b电连接的导电性裸片粘合剂14b、以及在导体裸片焊盘11b上具备设置于半导体裸片12a与半导体裸片12b之间的间隙的阻焊剂15。
通过采用上述结构,在半导体裸片之间设置了阻焊剂15,因此能够抑制导电性裸片粘合剂14a浸润扩散到该区域。
另外,也可以在导体裸片焊盘11d上设置与半导体裸片12a相邻设置的第二阻焊剂15’、设置在该第二阻焊剂15’上的第四半导体裸片12b、以及将该第四半导体裸片12b与第二阻焊剂15’连接的绝缘性裸片粘合剂14b。
通过采用上述结构,对于无需从底面进行电连接的半导体裸片设置了绝缘性裸片粘合剂,因此能够抑制因导电性裸片粘合剂引起的剥离等发生。
也可以在与PCB基材部16的表面垂直的至少一个截面中,将导体裸片焊盘11e形成为相对于PCB基材部16具有钝角的接触角α的倒梯形,以使其离PCB基材部16的表面越远而越宽。
通过采用这样的结构,能够抑制导电性裸片粘合剂流出。
导体裸片焊盘11b也可以具备被导电性裸片粘合剂14d覆盖的第三区域和从密封树脂17露出的第四区域,俯视时,第三区域被第四区域包围。
通过采用这样的结构,能够限制导电性裸片粘合剂的表面积,因此能够抑制因导电性裸片粘合剂引起的剥离发生。
还可以设置贯穿PCB基材部16并在内部形成有与导体裸片焊盘11b电连接的金属的多个过孔19d,俯视时,该多个过孔19d设置在第三区域内。
通过采用上述结构,能够通过多个过孔19d进行散热,从而即使导电性裸片粘合剂的量减少,也能够维持所要求的散热特性。
导电性裸片粘合剂也可以使用导电性裸片粘合剂14e,该导电性裸片粘合剂14e的粘性要高于使用同量的导电性裸片粘合剂14a时从导体裸片焊盘11b溢出并与PCB基材16接触的导电性裸片粘合剂14a所具备的粘性,且该导电性裸片粘合剂14e的接触角要大于导电性裸片粘合剂14a与PCB基材部16的接触角。
通过采用这样结构,能够抑制导电性裸片粘合剂14e的浸润扩散。
也可以在PCB基材部16的位于导体裸片焊盘11b与引线键合焊盘18之间的区域中形成槽20,导电性裸片粘合剂14c的一部分流入槽20内部。
通过采用这样结构,能够抑制导电性裸片粘合剂14e的浸润扩散,因此能够抑制由此引起的剥离。
另外,半导体模块5具备:PCB基材部16、设置在该PCB基材部16上且表面材质为Cu的导体裸片焊盘11g、设置在该导体裸片焊盘11g上的半导体裸片12a、将导体裸片焊盘11g与半导体裸片12a电连接的导电性裸片粘合剂14a、设置在PCB基材部16上且表面材质为含Au金属的引线键合焊盘18、以及将该引线键合焊盘18与半导体裸片12a电连接的引线13。
通过采用上述结构,相比于和表面材质为Au的导体裸片焊盘连接的情况,能够提供增益特性得到提高的半导体模块。
也可以进一步设置与引线键合焊盘18连接的金属布线,且导体裸片焊盘11g和金属布线均由含Cu的同一金属材料形成。
通过采用上述结构,通过在同一工序中形成导体裸片焊盘和金属布线。
另外,半导体模块具备:PCB基材部16、设置在该PCB基材部16上的第一导体裸片焊盘11f、在该PCB基材部16上与第一导体裸片焊盘11f相邻且隔开间隔设置的第二导体裸片焊盘11f、半导体裸片12a、以及与第一导体裸片焊盘11f、第二导体裸片焊盘11f及第一导体裸片焊盘11f与第二导体裸片焊盘11f之间的间隙中的PCB基材部16相接触并将第一导体裸片焊盘11f、第二导体裸片焊盘11f和半导体裸片12a电连接的导电性裸片粘合剂14a。
根据上述结构,导电性裸片粘合剂与导体裸片焊盘和基板双方均接触,因此能够利用锚固效应来进一步抑制剥离。
也可以设置贯穿PCB基材部16且在内部形成有与导体裸片焊盘11f’电连接的金属的过孔19d、以及贯穿PCB基材部16且在内部形成有与导体裸片焊盘11f’电连接的金属的过孔19d。
根据上述结构,能够通过过孔进行散热,因此能够减少会导致剥离发生的导电性裸片粘合剂。
另外,第一导体裸片焊盘11f’可以形成为与第一过孔19d相连的圆环状,第二导体裸片焊盘11f’可以形成为与第二过孔19d相连的圆环状。
根据上述结构,能够利用通孔盘来设置导体裸片焊盘。
上述说明的各实施方式用于使本发明容易理解,并不是限定解释本发明。在不脱离本发明的思想的前提下,可以对本发明变更或改良,并且本发明的等同发明也包含在本发明的范围内。即,本领域的技术人员在各实施方式上加以适当的设计变更,只要包含本发明的技术特征,也被包含在本发明的范围内。例如各实施方式具备的各要素及其配置、材料、条件、形状、尺寸等,不限于例示,能进行适当地变更。另外,各实施方式是一种例示,不同实施方式所示的结构可以部分替换或组合,只要具有本发明的特征,也包含在本发明的范围之内。
标号说明
半导体模块……1、2、3、3a、4、5
导体裸片焊盘……11a、11b、11c、11d、11e、11f、11f’、11g
半导体裸片……12a、12b
引线……13
导电性裸片粘合剂……14a
绝缘性裸片粘合剂……14b
阻焊剂……15
PCB基材部……16
密封树脂……17
引线键合焊盘……18
剥离……100。
Claims (10)
1.一种半导体模块,其特征在于,包括:
基板;
设置在该基板上的导体裸片焊盘;
设置在该导体裸片焊盘上的半导体裸片;
将所述导体裸片焊盘和所述半导体裸片电连接的导电性裸片粘合剂;
设置在所述基板上的引线键合焊盘;
将该引线键合焊盘与所述半导体裸片电连接的引线;
至少将所述导体裸片焊盘、所述半导体裸片、所述导电性裸片粘合剂、所述引线键合焊盘和所述引线密封的密封树脂;
在所述导体裸片焊盘上与所述半导体裸片相邻设置的第二半导体裸片;
将所述导体裸片焊盘和所述第二半导体裸片电连接的第二导电性裸片粘合剂;
在所述导体裸片焊盘上设置于所述半导体裸片与所述第二半导体裸片之间的间隙中的阻焊剂;以及
将所述半导体裸片和所述第二半导体裸片直接电连接的一根第二引线。
2.如权利要求1所述的半导体模块,其特征在于,
俯视时,所述导体裸片焊盘的边界到所述半导体裸片的距离的最小值为0.07mm以下。
3.如权利要求1或2所述的半导体模块,其特征在于,
在与所述基板的表面垂直的至少一个截面中,所述导体裸片焊盘形成为相对于所述基板具有钝角的接触角的倒梯形,以使所述导体裸片焊盘离所述基板越远就越宽。
4.如权利要求1或2所述的半导体模块,其特征在于,
所述导体裸片焊盘具有被所述导电性裸片粘合剂覆盖的第一区域和从所述半导体裸片露出的第二区域,
俯视时,所述第一区域被所述第二区域包围。
5.如权利要求4所述的半导体模块,其特征在于,
还具备贯穿所述基板且内部形成有与所述导体裸片焊盘电连接的金属的多个过孔,该多个过孔在俯视时设置于所述第一区域内。
6.如权利要求1或2所述的半导体模块,其特征在于,
所述导电性裸片粘合剂的粘性在8000cP以上。
7.如权利要求1或2所述的半导体模块,其特征在于,
在所述基板的位于所述导体裸片焊盘与所述引线键合焊盘之间的区域中形成有槽,
所述导电性裸片粘合剂的一部分流入所述槽的内部。
8.一种半导体模块,其特征在于,包括:
基板;
设置在该基板上的导体裸片焊盘;
设置在该导体裸片焊盘上的半导体裸片;
将所述导体裸片焊盘和所述半导体裸片电连接的导电性裸片粘合剂;
设置在所述基板上的引线键合焊盘;
将该引线键合焊盘与所述半导体裸片电连接的引线;
至少将所述导体裸片焊盘、所述半导体裸片、所述导电性裸片粘合剂、所述引线键合焊盘和所述引线密封的密封树脂;
在所述导体裸片焊盘上与所述半导体裸片相邻设置的阻焊剂;
设置在该阻焊剂上的第二半导体裸片;
将该第二半导体裸片与所述阻焊剂连接的裸片粘合剂;以及
将所述半导体裸片和所述第二半导体裸片直接电连接的一根第二引线。
9.如权利要求8所述的半导体模块,其特征在于,
所述导体裸片焊盘具有被所述导电性裸片粘合剂覆盖的第一区域和从所述半导体裸片露出的第二区域,
俯视时,所述第一区域被所述第二区域包围。
10.如权利要求9所述的半导体模块,其特征在于,
还具备贯穿所述基板且内部形成有与所述导体裸片焊盘电连接的金属的多个过孔,该多个过孔在俯视时设置于所述第一区域内。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5866953A (en) * | 1996-05-24 | 1999-02-02 | Micron Technology, Inc. | Packaged die on PCB with heat sink encapsulant |
US6635957B2 (en) * | 1998-06-10 | 2003-10-21 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
TW428295B (en) * | 1999-02-24 | 2001-04-01 | Matsushita Electronics Corp | Resin-sealing semiconductor device, the manufacturing method and the lead frame thereof |
US6548328B1 (en) * | 2000-01-31 | 2003-04-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
KR100347706B1 (ko) * | 2000-08-09 | 2002-08-09 | 주식회사 코스타트반도체 | 이식성 도전패턴을 포함하는 반도체 패키지 및 그 제조방법 |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2002299538A (ja) * | 2001-03-30 | 2002-10-11 | Dainippon Printing Co Ltd | リードフレーム及びそれを用いた半導体パッケージ |
TW548810B (en) * | 2002-05-31 | 2003-08-21 | Gigno Technology Co Ltd | Multi-chip package |
EP1542272B1 (en) * | 2003-10-06 | 2016-07-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US7556987B2 (en) * | 2006-06-30 | 2009-07-07 | Stats Chippac Ltd. | Method of fabricating an integrated circuit with etched ring and die paddle |
US20080157327A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Package on package structure for semiconductor devices and method of the same |
JP5220373B2 (ja) * | 2007-09-25 | 2013-06-26 | 三洋電機株式会社 | 発光モジュール |
JP5239309B2 (ja) * | 2007-11-21 | 2013-07-17 | 株式会社村田製作所 | 半導体装置 |
JP5407667B2 (ja) * | 2008-11-05 | 2014-02-05 | 株式会社村田製作所 | 半導体装置 |
JP2010171114A (ja) * | 2009-01-21 | 2010-08-05 | Renesas Technology Corp | 半導体装置 |
US20110133327A1 (en) * | 2009-12-09 | 2011-06-09 | Hung-Hsin Hsu | Semiconductor package of metal post solder-chip connection |
JP2011243897A (ja) * | 2010-05-21 | 2011-12-01 | Fujitsu Ltd | 多層プリント基板及びその製造方法 |
CN103515364A (zh) * | 2012-06-29 | 2014-01-15 | 三星电机株式会社 | 电源模块封装和用于制造电源模块封装的方法 |
JP6076068B2 (ja) * | 2012-12-17 | 2017-02-08 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
TWI559419B (zh) * | 2015-08-21 | 2016-11-21 | 力成科技股份有限公司 | 使用模封互連基板製程之柱頂互連(pti)型態半導體封裝構造及其製造方法 |
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Patent Citations (1)
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---|---|---|---|---|
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