CN103311127A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN103311127A
CN103311127A CN2013100751190A CN201310075119A CN103311127A CN 103311127 A CN103311127 A CN 103311127A CN 2013100751190 A CN2013100751190 A CN 2013100751190A CN 201310075119 A CN201310075119 A CN 201310075119A CN 103311127 A CN103311127 A CN 103311127A
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斋藤直人
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Ablic Inc
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Abstract

提供半导体装置的制造方法。提供一种使用简单并且控制性良好的工序的沟槽MOSFET的制造方法，所述沟槽MOSFET能够与CMOS晶体管形成在同一衬底上，可以缩小元件面积。是如下所述的沟槽MOSFET的制造方法：通过形成三维的体接触区域，即便采用更小的面积，也具有能够确保与以往同样的接触的结构。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体装置和半导体装置的制造方法，涉及例如在与CMOS相同的衬底上形成的沟槽MOSFET的构造和制造方法。
背景技术
MOS晶体管是在电子技术中发挥核心作用的电子元件，MOS晶体管的小型化和高驱动能力化无论在低耐压领域还是在高耐压领域都是重要的课题。
将载流子移动的方向相对于半导体衬底表面设定为上下（铅直方向）的纵型构造的沟槽MOSFET，能够构成小面积且具有较大的沟槽宽度的晶体管，因此被广泛用于需要高驱动能力的用途。目前为止，作为离散的驱动元件被广泛应用，但近年来，提出了将该高驱动能力的沟槽MOSFET与构成控制电路的通常的CMOS晶体管一体化的工艺。
在从上方观察的情况下，沟槽MOSFET的表面形状被划分为沟槽区域和非沟槽区域。此外，非沟槽区域被划分为高浓度杂质区域即源区域和用于固定体（body）区域的电位的高浓度杂质区域即体接触区域。
此外，由于通常以同电位使用作为非沟槽区域的源区域和体接触区域，因此多数情况下两杂质区域邻接，并同时用相同的金属布线连接。在硅化物形成工艺的情况下，两区域被连续的硅化物覆盖，经由最小限度的接触面积/数量与布线金属连接。
为了提高每单位面积的驱动能力，要求消减上述沟槽区域或非沟槽区域的面积。作为非沟槽区域之一的体接触区域，只要能固定电位即可，在这点上，减小面积是有效的，但如果电位不稳定，则晶体管会阶跃恢复（Snapback），妨碍在期望的动作电压下的正常动作。
此外，由于受到构成源区域的杂质的浓度的偏差和扩散的偏差的影响，因此需要将体接触区域配置成具有更大余量的面积。因此不能容易地缩小面积。
以往，控制杂质浓度和热处理，以使得固定电位并能够尽量缩小面积，从而构成源区域和体接触区域。或者，此外，如下述的专利文献1那样提出如下方案，设置配置体接触区域的部位和不配置体接触区域的部位，在整体上缩小面积。
如图5所示，在专利文献1的技术中，将沟槽区域51和非沟槽区域53配置成条带状，将非沟槽区域53的宽度分为两种，在宽度较大的一方配置体接触区域52，在宽度较小的一方不配置体接触区域52。将该配置在邻接的条带中以彼此不同的方式排列，由此将面积效率最优化，以最小限度的面积构成晶体管，降低每单位面积的晶体管的导通（ON）电阻。
现有技术文献
专利文献
专利文献1：日本特开2002-50760号公报
发明内容
然而，根据专利文献1的技术，必须将体接触区域配置成一定面积以上，该区域依然限制晶体管面积的缩小化。此外，“在将沟槽区域配置为格子状的情况下，将限定为条带状的布局的体接触区域到处配置”这一对策在得到晶体管特性的均匀性上未必是好方法。
因此，本发明的目的在于，提供一种能够不增加工序并且使用控制性优良的工序得到均匀的元件面积较小的沟槽MOSFET的制造方法。
本发明为了达成所述目的，在第1方面的发明中，提供一种半导体装置的制造方法，其特征在于，该半导体装置的制造方法包括以下工序：
在第1导电型的半导体衬底上形成第2导电型的埋层；在所述埋层上形成第2导电型的外延层；从所述第2导电型的外延层的表面到一定的深度，形成第1导电型的体区域；除去构成所述体区域的表面的半导体材料，在凸型触点区域的周围形成浅沟槽；形成从所述浅沟槽的表面的一部分到所述第2导电型的外延层内的深沟槽区域；在所述深沟槽区域的内壁形成栅绝缘膜；与所述栅绝缘膜相接地由多晶硅填充所述深沟槽区域内；在所述体区域表面的所述浅沟槽内形成第2导电型的源区域；在所述体区域表面的所述凸型触点区域形成第1导电型的体接触区域；以及形成连接所述源区域和所述体接触区域的硅化物层，
所述凸型触点区域的表面全部是所述体接触区域，与所述源区域的表面一起被所述硅化物层覆盖。
在第2方面的发明中，提供一种半导体装置的制造方法，其特征在于，该半导体装置的制造方法包括以下工序：
在第1导电型的半导体衬底上形成第2导电型的埋层；在所述埋层上形成第2导电型的外延层；在所述外延层的表面的特定的区域形成用于作为凹型触点区域的浅沟槽；以与所述外延层的表面的距离固定的方式，形成第1导电型的体区域，该第1导电型的体区域在没有所述凹型触点区域的平坦的区域下浅，在所述凹型触点区域下深，并朝向所述埋层突出；在所述平坦的区域形成从所述体区域的表面到所述外延层内的深沟槽；在所述深沟槽区域的内壁形成栅绝缘膜；与所述栅绝缘膜相接地由多晶硅填充所述深沟槽区域内；在所述体区域表面的所述平坦的区域形成第2导电型的源区域；沿着所述体区域表面的所述凹型触点区域形成第1导电型的体接触区域；以及形成连接所述源区域和所述体接触区域的硅化物层，
所述凹型触点区域的表面全部是所述体接触区域，与所述源区域的表面一起被所述硅化物层覆盖。
根据本发明，可以制造出最大限度地发挥元件特性并能够对应精细尺寸的半导体装置，其结果是，可以降低成本。
附图说明
图1是用于说明本发明的第一实施方式的半导体装置的制造方法的工序顺序剖视图。
图2是用于说明本发明的第一实施方式的半导体装置的制造方法的、接着图1的工序顺序剖视图。
图3是用于说明本发明的第二实施方式的半导体装置的制造方法的工序顺序剖视图。
图4是用于说明本发明的第二实施方式的半导体装置的制造方法的、接着图3的工序顺序剖视图。
图5是用说明以往的半导体装置的图。
标号说明
1：P型半导体衬底
2：N型埋层
3：N-epi层
4：P型体区域
5：凸型触点
6：深沟槽
7：栅氧化膜
8：栅电极
9：N型源区域
10、30：P型体接触区域
11：硅化物层
12：浅沟槽
15：凹型触点
16：平坦的区域
具体实施方式
图1是用于说明本实施方式的半导体装置的制造方法的图，是本发明中的沟槽MOSFET的工序顺序剖视图。
如图1的（a）所示，在形成于P型半导体衬底1上的N型埋层2上设置有外延层3（在此称作N-epi层3），在整体上掺杂有N型杂质。N型埋层2具有5×1017/cm3～5×1019/cm3的浓度，成为沟槽MOSFET的漏区域。通过掺杂Sb（锑）、As（砷）或P（磷）而形成。此外，N-epi层3成为低浓度的漏区域或者漂移区域，通过在1×1015/cm3～5×1017/cm3的浓度中掺杂磷而实现。N型埋层2的厚度约为2～10μm厚，N-epi层3厚度约为2～10μm厚。
接着，如图1的（b）所示，在N-epi层3内利用用于隔离元件的STI（Shallow TrenchIsolation：浅沟槽隔离）或者LOCOS（Local Oxidation of Silicon：硅的局部氧化）（未图示），残留一部分而除去表面的半导体材料，形成凸型触点区域5。因此，凸型触点区域5的周围成为浅沟槽12，其表面变低。在使用STI来隔离元件的情况下，在凸型触点区域5以外的部位进行用于STI形成的硅蚀刻，由此能够形成图1的（b）那样的形状。关于CMOS形成区域，将绝缘膜埋入STI中的工序等在此处进行。另一方面，在使用LOCOS来隔离元件的情况下，在凸型触点区域5以外形成50nm～150nm的LOCOS氧化膜，通过除去LOCOS氧化膜，形成图1的（b）所示的凸型触点5。
接着，通过离子注入形成P型的体区域4。以成为5×1016/cm3～1×1018/cm3的浓度的方式在P型的体区域4中注入B（硼）或者BF2（二氟化硼）。此时的注入的加速能量根据沟槽MOSFET需要的耐压而改变，但优选在50～250keV的范围内。另外，P型的体区域4的形成工序也可以在形成凸型触点区域5之前。
接着，如图1（c）所示，在浅沟槽内通过蚀刻形成深沟槽6。深沟槽6的深度是约1～3μm，根据晶体管所要求的期望的漏极耐压而适当地进行设定。
接着，在图2的（a）中，在深沟槽6的内壁上通过热氧化形成栅氧化膜7，在沟槽6内隔着栅氧化膜7填充成为栅电极8的多晶硅。栅电极8通过沿着深沟槽6的侧壁和底面延伸的栅氧化膜7而与N-epi层3和P型的体区域4电隔离。考虑期望的晶体管的栅极击穿电压来设定栅氧化膜7的厚度，约为7nm～20nm。此外，栅氧化膜7的形成温度为800℃到1150℃，但更优选在1000℃～1150℃的范围内。
接着，在图2的（b）中，在P型的体区域4的上侧表面区域进行离子注入，以形成N型的高浓度杂质区域即源区域9。为了降低薄膜电阻，优选例如以5×1014～1×1016atoms/cm2的掺杂剂量用As进行离子注入，以形成N型的源区域9。当然，也可以高浓度地注入P（磷），也可以导入As和P这两者。此外，在包含凸型触点区域5的区域中进行用于形成P型的体接触区域10的离子注入。为了降低薄膜电阻，优选例如以5×1014～1×1016atoms/cm2的掺杂剂量用BF2进行离子注入，以形成P型的体接触区域10。当然，也可以高浓度地注入B（硼），也可以导入BF2和B这两者。
然后，如图2的（c）所示，在源区域9和体接触区域10上形成硅化物层11，使用插头布线（未图示）与布线金属层（未图示）连接。
以上对使用了N-epi层3的情况进行了说明，但也可以是，使用P-epi层，与P型的体区域4同时地以N型杂质进行离子注入，将N型埋层2与P型的体区域4之间设定为N型的漏区域。此外，在此处，以N型的晶体管为前提进行了说明，但是，在将埋层、epi层作为P型，体区域作为N型的P型的晶体管的情况下，也能够同样地进行应用。（当然，也可以将epi层设为N型，通过导入杂质将P型埋层与体区域之间设定为P型的漏区域。）
此外，对与沟槽MOSFET在同一衬底上形成的CMOS未作详细说明，但是，上述中示出的工序在CMOS形成时不存在任何成为障碍的工序，能够容易地将沟槽MOSFET与CMOS形成在同一衬底上。
图3是用于对本实施方式的第2半导体装置的制造方法进行说明的图。
在图3的（a）中，在形成于P型半导体衬底1上的N型埋层2上设置epi层3（此处称作N-epi层3），在整体上掺杂有N型杂质。N型埋层2通过掺杂Sb（锑）或者As（砷）或者P（磷）而形成，具有5×1017/cm3～5×1019/cm3的浓度，此外，N-epi层3通过掺杂磷而实现，具有1×1015/cm3～5×1017/cm3的浓度。N型埋层2的厚度约为2～10μm厚，N-epi层3的厚度约为2～10μm。
接着，在N-epi层3内，为了配置用于隔离元件的STI，对硅进行蚀刻，形成浅沟槽，将绝缘膜埋入浅沟槽内，但将埋入位于沟槽MOSFET的形成予定区域的浅沟槽内的绝缘膜除去。（该绝缘膜的除去也可以在后面的P型的体区域离子注入用的抗蚀图案（Resist pattern）形成后进行。）由此，形成利用了浅沟槽的凹型触点区域15。另外，根据所要求的动作电压适当设定浅沟槽的深度，约是200nm～600nm。
也可以不使用STI而是使用LOCOS来隔离元件，制作上述凹型触点区域15那样的形状。此时，仅在凹型触点区域15部分形成50nm～150nm的LOCOS氧化膜，然后，通过蚀刻除去LOCOS氧化膜，由此能够形成与STI相似的形状的凹型触点区域15。
接着，在图3的（b）中，通过离子注入形成P型的体区域4。在P型的体区域4中，以成为5×1016/cm3～1×1018/cm3的浓度的方式注入B（硼）或BF2（二氟化硼）。此时，无论在形成利用了浅沟槽的凹型触点区域15的区域中，还是在未形成凹型触点区域15的平坦的区域16中，杂质能够从表面到达的距离相同，因而形成体区域4的杂质反映N-epi层3的表面的形状而分布，能够在凹型触点区域15正下方使P型的体区域4的底较深，在其他的区域中使P型的体区域4的底较浅。
接着，如图3的（c）所示，从体区域4的表面到N-epi层3，形成深沟槽6。深沟槽6的深度为约1～3um，根据期望的晶体管所要求的漏极耐压适当地进行设定。另外，在此，重要的是将深沟槽6设定在P型的体区域4的底较浅的区域。
接着，如图4的（a）所示，在深沟槽26的内壁上通过热氧化形成栅氧化膜7，在沟槽6内隔着栅氧化膜7填充作为栅电极8的多晶硅。栅电极8通过沿着深沟槽6的侧壁和底面延伸的栅氧化膜7而与N-epi层3和P型的体区域4电隔离。考虑期望的晶体管的栅极击穿电压来设定栅氧化膜7的厚度，约为7nm～20nm。此外，栅氧化膜7的形成温度为800℃到1150℃，但更优选在1000℃～1150℃的范围内。
接着，如图4的（b）所示，在包含与P型的体区域4的上侧表面和深沟槽6的侧壁邻接的凹型触点区域15的区域中形成P型体接触区域30。此外，以与深沟槽6邻接，并与P型体接触区域30邻接的方式，形成N型源区域9。
然后，如图4的（c）所示，在N型的高浓度杂质区域即源区域9和P型的体接触区域30上形成硅化物层11，使用插头布线（未图示）与布线金属层（未图示）连接。
以上对使用了N-epi层3的情况进行了说明，但也可以是，使用P-epi层，与P型的体区域4同时地用N型杂质进行离子注入，将N型埋层2与P型的体区域4之间设定为N型的漏区域。此外，在此处以N型的晶体管为前提进行了说明，但是，在将埋层、epi层作为P型，体区域作为N型的P型的晶体管的情况下，能够同样地进行应用。（当然，也可以将epi层设为N型，通过导入杂质将P型埋层与体区域之间设定为P型的漏区域。）
此外，没有触及与沟槽MOSFET在同一衬底上形成的CMOS，但是，上述中示出的工序在CMOS形成时不存在任何成为障碍的工序，能够容易地将沟槽MOSFET与CMOS在同一衬底上形成。
根据以上说明的本实施方式能够得到如下效果。
（1）可以较大地取得用于得到体（body）的电位的硅高浓度区域和硅化物层的接触面积，如果接触面积相同，则实质上能够缩小体接触区域的面积、即平面的体接触区域的大小，因此，能够以相同面积形成导通（ON）电阻较低的沟槽MOSFET。
（2）通过利用STI或Locos工艺那样的稳定的工序，能够将偏差抑制在最小限度内，能够制造具有高度的特性的设备。
产业上的可利用性
能够应用于在要求比较高的耐压/驱动能力的、面向汽车的半导体装置、或电视、DVD、生活家电等面向家庭的电器制品中有效的半导体装置中。

Claims (8)

1.一种半导体装置的制造方法，其特征在于，该半导体装置的制造方法包括以下工序：
在第1导电型的半导体衬底上形成第2导电型的埋层；
在所述埋层上形成第2导电型的外延层；
从所述第2导电型的外延层的表面到一定的深度，形成第1导电型的体区域；
除去构成所述体区域的表面的半导体材料，在凸型触点区域的周围形成浅沟槽；
形成从所述浅沟槽的表面的一部分到所述第2导电型的外延层内的深沟槽区域；
在所述深沟槽区域的内壁形成栅绝缘膜；
与所述栅绝缘膜相接地由多晶硅填充所述深沟槽区域内；
在所述体区域的表面的所述浅沟槽内形成第2导电型的源区域；
在所述体区域的表面的所述凸型触点区域形成第1导电型的体接触区域；以及
形成连接所述源区域和所述体接触区域的硅化物层，
所述凸型触点区域的表面全部是所述体接触区域，与所述源区域的表面一起被所述硅化物层覆盖。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，
所述浅沟槽的深度在200nm～600nm的范围内。
3.根据权利要求1所述的半导体装置的制造方法，其特征在于，
形成所述浅沟槽的工序由形成LOCOS氧化膜的工序和除去该LOCOS氧化膜的工序构成。
4.根据权利要求3所述的半导体装置的制造方法，其特征在于，
所述LOCOS氧化膜的膜厚在50nm～150nm的范围内。
5.一种半导体装置的制造方法，其特征在于，该半导体装置的制造方法包括以下工序：
在第1导电型的半导体衬底上形成第2导电型的埋层；
在所述埋层上形成第2导电型的外延层；
在所述外延层的表面的特定区域形成用于作为凹型触点区域的浅沟槽；
以与所述外延层的表面的距离固定的方式，形成第1导电型的体区域，该第1导电型的体区域在没有所述凹型触点区域的平坦区域下浅，在所述凹型触点区域下深，并朝向所述埋层突出；
在所述平坦区域形成从所述体区域的表面到所述外延层内的深沟槽；
在所述深沟槽区域的内壁形成栅绝缘膜；
与所述栅绝缘膜相接地由多晶硅填充所述深沟槽区域内；
在所述体区域表面的所述平坦区域形成第2导电型的源区域；
沿着所述体区域的表面的所述凹型触点区域形成第1导电型的体接触区域；以及
形成连接所述源区域和所述体接触区域的硅化物层，
所述凹型触点区域的表面全部是所述体接触区域，与所述源区域的表面一起被所述硅化物层覆盖。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于，
所述浅沟槽的深度在200nm～600nm的范围内。
7.根据权利要求5所述的半导体装置的制造方法，其特征在于，
形成所述浅沟槽的工序由形成LOCOS氧化膜的工序和除去该LOCOS氧化膜的工序构成。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于，
所述LOCOS氧化膜的膜厚在50nm～150nm的范围内。
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