CN103178115A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN103178115A
CN103178115A CN2012105609943A CN201210560994A CN103178115A CN 103178115 A CN103178115 A CN 103178115A CN 2012105609943 A CN2012105609943 A CN 2012105609943A CN 201210560994 A CN201210560994 A CN 201210560994A CN 103178115 A CN103178115 A CN 103178115A
Authority
CN
China
Prior art keywords
groove
gate electrode
diffusion layer
layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012105609943A
Other languages
English (en)
Other versions
CN103178115B (zh
Inventor
桥谷雅幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN103178115A publication Critical patent/CN103178115A/zh
Application granted granted Critical
Publication of CN103178115B publication Critical patent/CN103178115B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Abstract

半导体装置及其制造方法。本发明提供小型的具备沟槽构造的纵型MOS晶体管。在以固定间隔连续的沟槽间的衬底以及随后设置源高浓度扩散层的硅表面区域内生成STI的氧化膜，在形成沟槽之后去除，并形成比周围表面低的区域，由此能够使填埋在具有侧间隔体的具备沟槽构造的纵型MOS晶体管的沟槽的栅电极上的硅化物与设置于衬底以及源高浓度扩散层上的硅化物分离，由此可进行用于面积缩小的沟槽的尺寸缩小以及半导体装置的高驱动性能化。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置，尤其涉及具有沟槽构造的纵型MOS晶体管。
背景技术
存在这样的趋势：以电压调节器、电压检测器为代表的电源IC的芯片尺寸缩小，在电压调节器中，输出电流增加。构成该电源IC的元件中的用于使电流流动的驱动元件占据芯片面积的大部分，所以，一直以来，通过采用具有沟槽构造的MOS晶体管，实现了面积缩小与有效沟道宽度的增大带来的高驱动性能化。
例如，在专利文献1或专利文献2中介绍了现有的具备沟槽构造的半导体装置及其制造方法。
根据图4来说明现有的具备沟槽构造的纵型MOS晶体管的制造方法。图4是示出制造方法的示意性剖视图的工序流程。
首先，如图4(A)所示，具有第2导电型填埋层22，在要设置沟槽构造的区域中形成第1导电型阱扩散层23(称为主体)，在其表面上利用热氧化膜24以及堆积氧化膜25进行层叠。利用抗蚀膜26进行构图从而进行蚀刻，该蚀刻是为了使这些氧化膜作为用于进行沟道蚀刻的硬掩模来使用。接着，如图4(B)所示，在去除抗蚀膜26之后，使用由上述构图后的热氧化膜24以及堆积氧化膜25层叠而得到的硬掩模，利用蚀刻来形成沟槽27。接着，如图4(C)所示，在去除作为硬掩模使用的热氧化膜24以及堆积氧化膜25之后，为了沟槽27的形状改善而利用热氧化来形成牺牲氧化膜28。
然后，如图4(D)所示，去除牺牲氧化膜28，利用热氧化来形成栅绝缘膜29，然后堆积已掺加杂质的掺杂多晶硅膜30。然后，如图4(E)所示，利用抗蚀膜32进行构图，对掺杂多晶硅膜30进行过蚀刻，由此获得栅电极31。然后，如图4(F)所示，对抗蚀膜33进行构图，进行用于形成源区域的第2导电型的杂质添加，接着，如图4(G)所示，另外对抗蚀膜34进行构图，进行用于形成衬底电位区域的第1导电型的杂质添加。
然后，如图4(H)所示，利用热处理来形成第2导电型源高浓度扩散层35以及第1导电型衬底电位高浓度扩散层36。接着，在堆积层间绝缘膜37之后，形成用于实现栅电极31、第2导电型源高浓度扩散层35以及第1导电型衬底电位高浓度扩散层36的电连接的接触孔38，填埋钨等的栓塞（ブラグ），形成源衬底共同电位布线40以及栅电位布线39。
由此，完成具有形成在第1导电型阱扩散层23上的沟槽27的、具备在纵向上工作的沟槽构造的纵型MOS晶体管的元件构造。
专利文献1：日本特开2003-101027号公报
专利文献2：日本特开平8-255901号公报
但是，在具备沟槽构造的纵型MOS晶体管中，存在这样的问题：当为了降低用于实现填埋在沟槽中的栅电极的电连接的接触电阻而实施自对准硅化时，填埋在沟槽中的栅电极和与沟槽邻接的衬底以及源高浓度扩散层的硅化物导通。因此，存在这样的问题：难以进行栅电极上的硅化，当为了缩小芯片面积而谋求沟槽宽度的尺寸缩小时，栅电极的电阻会增大。
发明内容
本发明的课题是提供一种半导体装置及其制造方法，能够将填埋到沟槽中的栅电极上的硅化物与衬底以及源高浓度扩散层的硅化物分离，可进行用于面积缩小的沟道尺寸缩小，能够实现高驱动性能化。
为了解决上述课题，本发明采用如下的手段。
首先，提供一种半导体装置，其特征是具备：第1导电型半导体衬底；第1导电型外延生长层，其隔着第2导电型填埋层设置在第1导电型半导体衬底上；第1导电型阱扩散层，其形成在第2导电型填埋层上的第1导电型外延生长层的一部分上；沟槽，其格状或者条纹状地相互连结，以从第1导电型阱扩散层到第2导电型填埋层的深度形成；栅绝缘膜，其形成在沟槽表面；作为栅电极的多晶硅膜，其隔着栅绝缘膜填充沟槽，并且比第1导电型阱扩散层表面更高地突出；侧间隔体，其形成在栅电极的侧面；第2导电型源高浓度扩散层以及第1导电型衬底电位扩散层，它们形成在第1导电型阱扩散层的沟槽以外的岛状区域的表面的上部；形成在栅电极表面上的硅化物层；以及形成在第2导电型源高浓度扩散层以及第1导电型衬底电位扩散层的表面上的硅化物层，形成在栅电极表面上的硅化物层与形成在第2导电型源高浓度扩散层以及第1导电型衬底电位扩散层的表面上的硅化物层通过侧间隔体而分离。
另外，上述半导体装置的特征是，第2导电型源高浓度扩散层形成在沟槽以外的岛状区域的表面的盘型形状的底部以及周围隆起区域内。
然后，在上述半导体装置的制造方法中，通过对基于STI(Shallow Trench Isolation，浅沟槽隔离)的填埋氧化膜即厚氧化膜进行蚀刻去除来形成沟槽以外的岛状区域的表面的盘型形状。
如上所述，在具备沟槽构造的纵型MOS晶体管中，在以固定间隔连续的沟槽之间的、衬底以及源高浓度扩散层电连接而设置的沟槽以外的区域内，生成厚氧化膜，然后进行去除，由此形成周围高、内部低的区域。通过利用在周围形成的高区域来形成具有侧间隔体的具备沟槽构造的纵型MOS晶体管，能够使填埋在沟槽中的栅电极上与衬底以及源高浓度扩散层的硅化物分离。通过采用此构造，可获得如下的半导体装置，该半导体装置能够进行用于面积缩小的沟道尺寸缩小，并能够实现高驱动性能化。
附图说明
图1是示出本发明的半导体装置的制造方法的实施例的示意性剖视图。
图2是示出接在图1之后的本发明的半导体装置的制造方法的实施例的示意性剖视图。
图3是示出本发明的半导体装置的实施例的示意性俯视图。
图4是示出现有的半导体装置的制造方法的示意性剖视图。
标号说明
1、22第2导电型填埋层；2、23第1导电型阱扩散层；3厚氧化膜；4硬掩模；5、27沟槽；6、28牺牲氧化膜；7、29栅绝缘膜；8、13、14、26、33、34抗蚀膜；9、31栅电极；10、12、25堆积氧化膜；11侧间隔体；15、35第2导电型源高浓度扩散层；16、36第1导电型衬底电位高浓度扩散层；17金属膜；18硅化物；19、37层间绝缘膜；20、38接触孔；21、39源衬底共同电位布线；22、40栅电位布线；24热氧化膜；30掺杂多晶硅膜。
具体实施方式
以下，根据附图来说明本发明的方式。图1以及图2是用于示出本发明的半导体装置的制造方法的实施例的示意性剖视图的工序流程。这些示意性剖视图是在与图3(A)的俯视图所示的本发明的半导体装置的实施例中的B-B截面相当的位置处截断的图。
如图1(A)所示，在第1导电型半导体衬底上使具有第2导电型填埋层1的第1导电型外延生长层以生长层厚度成为几μm至几十μm的方式生长，得到衬底，其中，第1导电型半导体衬底是以使电阻率成为20Ωcm～30Ωcm的方式添加作为杂质的硼而得到的P型半导体衬底，第2导电型填埋层1是使砷、磷、锑等N型杂质以1×1016atom/cm3～1×1018atom/cm3左右的浓度扩散而得到的。
此后，在具有沟槽构造的区域中，使用硼或二氟化硼等杂质以1×1012atom/cm2至1×1013atom/cm2的剂量进行离子注入而形成被称为主体的第1导电型阱扩散层2。如果上述第2导电型填埋层1例如为P型填埋层，则进行杂质添加，使硼等杂质成为上述浓度。适当选择第1导电型半导体衬底、第2导电型填埋层1以及第1导电型外延生长层各自的导电型。
此后，在具有沟槽结构的区域中，将作为本发明特征之一的厚氧化膜3例如以元件分离用的STI（浅沟槽隔离：Shallow Trench Isolation）为代表的填埋氧化膜的膜厚成为几十nm，设置在第1导电型阱扩散层2的沟槽以外的岛状区域。这里，厚氧化膜3在岛状区域的周围变薄，在内部变厚，且具有一定的膜厚。厚氧化膜3的周边形状为钵状或者盘的边缘状。即，在岛状区域内，在接近于沟槽的周围是第1导电型阱扩散层2隆起的隆起区域，包围其内部而构成底部。此外，在第1导电型阱扩散层2的表面以及厚氧化膜3的表面上对用于沟道蚀刻的硬掩模4进行构图并进行配置。此时的硬掩模4如果在之后的沟槽蚀刻中具有足够的耐受性，则也可以是热氧化膜或者堆积氧化膜之一的单层结构，即使是抗蚀膜或者氮化膜也没有问题。
接着，采用硬掩模4利用蚀刻来形成沟槽5。沟槽5的深度优选形成为沟道底部到达第2导电型填埋层1。图1(A)表示此状态。此外，沟槽5的平面形状如图3(A)以及图3(B)所示既可以是格状也可以是条纹状。这里，元件俯视图的图3(A)以及(B)都示出具备沟槽构造的纵型MOS晶体管的基本单元。在实际的半导体装置中，这样的基本单元以至少几百个～几千个的量级集成在芯片内。
进而，如图1(B)所示，在去除硬掩模4之后，为了改善沟槽5的形状而利用热氧化来形成例如具有几nm～几十nm膜厚的牺牲氧化膜6。
然后，如图1(C)所示，与去除牺牲氧化膜6同样地去除厚氧化膜3，由此，去除厚氧化膜3后的区域形成为比周围平面低。这是本实施例的特征之一。即，作为岛状区域的非沟槽区域的第1导电型阱扩散层2的表面成为周围隆起、内部低凹且平坦的盘型形状。接着，在沟槽5以及第1导电型阱扩散层2表面上例如利用膜厚为几百
Figure BDA00002629588100051
几千
Figure BDA00002629588100052
的热氧化膜来形成栅绝缘膜7。并且，在优选以100nm～500nm的膜厚堆积掺杂多晶硅膜之后，利用抗蚀膜8进行构图并进行过蚀刻，得到在沟槽5内填埋掺杂多晶硅膜而成的栅电极9。因为以覆盖沟槽5的上方的方式对抗蚀膜8进行构图，所以栅电极9表面比第1导电型阱扩散层2表面突出，成为比盘型形状的最高的周围部分的隆起区域更高的形状。
然后，如图1(D)所示，去除抗蚀膜8，例如以几百nm的膜厚对堆积氧化膜10进行层叠。接着，如图1(E)所示，通过对堆积氧化膜10进行凹蚀(エツチバツク)，在栅电极9侧面上形成侧间隔体11。然后，例如以几十nm的膜厚对堆积氧化膜12进行堆积，该堆积氧化膜12用于对源高浓度扩散层以及衬底电位高浓度扩散层进行离子注入。
然后，如图2(A)所示，利用抗蚀膜13进行构图，通过离子注入法进行用于形成源区域的第2导电型的杂质添加。杂质注入的区域是栅电极9侧方的第1导电型阱扩散层2的表面附近。
然后，如图2(B)所示，在去除抗蚀膜13之后，以覆盖栅电极9以及侧间隔体11的方式重新对抗蚀膜14进行构图，通过离子注入法来进行用于形成衬底电位区域的第1导电型的杂质添加。关于图2(A)以及图2(B)的离子注入，如果导电型是N型，则优选以1×1018atom/cm2～1×1016atom/cm2的剂量对例如砷或磷进行离子注入。另一方面，如果导电型是P型，则优选以1×1015atom/cm2～1×1016atom/cm2的剂量对硼或者二氟化硼进行离子注入。此外，此处的源区域以及衬底电位区域的杂质添加也可以与不具备沟槽5的同一芯片内的MOS晶体管源区域的杂质添加同时进行。
然后，如图2(C)所示，通过在800℃～1000℃下进行几小时热处理，在栅电极9侧方的第1导电型阱扩散层2表面上形成第2导电型源高浓度扩散层15，在多个第2导电型源高浓度扩散层15之间等形成第1导电型衬底电位高浓度扩散层16。此时，第1导电型阱扩散层2表面成为周围隆起的盘型形状，所以不仅在盘型的底部区域，在周围的隆起区域也形成第2导电型源高浓度扩散层15。
由此，完成具备形成在第1导电型阱扩散层2上的沟槽5、并具有在纵向上工作的沟槽结构的纵向MOS晶体管的基本结构。接着，在去除堆积氧化膜12之后，将用于自对准硅化的金属膜17例如钴或钨等堆积成几十nm。
接着，如图2(D)所示，利用RTA等，例如在800℃～1000℃下进行几十秒～几分钟的热处理，由此在栅电极9以及第2导电型源高浓度扩散层15以及第1导电型衬底电位高浓度扩散层16的共同部分形成硅化物18。此时，在侧间隔体11表面未形成硅化物，从而自匹配地形成硅化物(自对准硅化物构造)。另外，在第2导电型源高浓度扩散层15上的盘型底部区域内形成硅化物，但在周围的隆起区域没有形成硅化物。由此，栅电极9上的硅化物18与第2导电型源高浓度扩散层15上的硅化物18保持充分的距离而分离。
然后，如图2(E)所示，在例如以几百nm～1μm的膜厚对层间绝缘膜19进行层叠后，形成用于实现栅电极9、第2导电型源高浓度扩散层15以及第1导电型衬底电位高浓度扩散层16的共同部分的电连接的接触孔20，填埋钨等的栓塞，形成源衬底共同电位布线21以及栅电位布线22。
如上所述，可利用侧间隔体自匹配地分离并形成作为本发明特征的填埋在沟槽中的栅电极上的硅化物与源高浓度扩散层上以及衬底电位高浓度扩散层上的硅化物，因此即使进行用于面积缩小的栅电极尺寸缩小，也能够实现足够低的接触电阻。

Claims (3)

1.一种半导体装置，其具有半导体衬底上设置的沟槽构造的纵型MOS晶体管，其特征在于，
在沟槽内填埋了栅电极，
在围着所述沟槽的所述半导体衬底表面上设置有源电极，
所述源电极在与所述栅电极的邻接部具有向上方隆起的隆起部，
所述栅电极具有比所述源电极的隆起部更向上方突出的突出部，
在所述栅电极的突出部设置有侧间隔体，
在所述源电极以及所述栅电极的上表面具有硅化物层。
2.一种半导体装置，其特征在于，其具备：
第1导电型半导体衬底；
第1导电型外延生长层，其隔着第2导电型填埋层设置在所述第1导电型半导体衬底上；
第1导电型阱扩散层，其形成在所述第2导电型填埋层上的所述第1导电型外延生长层的一部分上；
沟槽，其配置成格状或者条纹状，并以从所述第1导电型阱扩散层的表面到所述第2导电型填埋层的深度形成；
栅绝缘膜，其形成在所述沟槽的表面上；
栅电极，其隔着所述栅绝缘膜填充所述沟槽，并且比所述第1导电型阱扩散层的表面更高地突出；
侧间隔体，其形成在所述栅电极的侧面；
第2导电型源高浓度扩散层和第1导电型衬底电位扩散层，它们形成在第1导电型阱扩散层的所述沟槽之外的岛状区域的表面上；
第1硅化物层，其形成在所述栅电极的表面上；以及
第2硅化物层，其形成在所述第2导电型源高浓度扩散层和所述第1导电型衬底电位扩散层的表面上，
在所述岛状区域的表面上形成有盘型形状的底部以及周围的隆起区域，所述侧间隔体配置在所述隆起区域上，所述第2导电型源高浓度扩散层形成在所述隆起区域，
所述第1硅化物层与所述第2硅化物层通过所述侧间隔体分离。
3.一种半导体装置的制造方法，该半导体装置具有沟槽构造的纵型MOS晶体管，该制造方法的特征在于，包括以下工序：
在半导体衬底上的作为填埋栅电极的沟槽的部分的周边，与作为所述沟槽的部分离开预定量而设置基于浅沟槽隔离STI的填埋氧化膜；
在作为所述沟槽的部分设置沟槽；
在所述沟槽内设置栅氧化膜后，层叠多晶硅，填埋所述沟槽，进而层叠得高于所述半导体衬底；
去除所述沟槽内以及所述沟槽上方以外的所述多晶硅，形成比所述半导体衬底突出的栅电极；
去除基于所述STI的填埋氧化膜；
在堆积氧化膜之后，进行凹蚀，在所述栅电极的周围形成侧间隔体；
在围着所述栅电极的所述半导体衬底上进行离子注入，形成源区域；
附着硅化用金属膜；以及
实施热处理，在所述栅电极上和所述源区域上形成硅化物层。
CN201210560994.3A 2011-12-22 2012-12-21 半导体装置及其制造方法 Expired - Fee Related CN103178115B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011281632A JP5881100B2 (ja) 2011-12-22 2011-12-22 半導体装置の製造方法
JP2011-281632 2011-12-22

Publications (2)

Publication Number Publication Date
CN103178115A true CN103178115A (zh) 2013-06-26
CN103178115B CN103178115B (zh) 2017-10-03

Family

ID=48637858

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210560994.3A Expired - Fee Related CN103178115B (zh) 2011-12-22 2012-12-21 半导体装置及其制造方法

Country Status (5)

Country Link
US (1) US8847308B2 (zh)
JP (1) JP5881100B2 (zh)
KR (1) KR101960547B1 (zh)
CN (1) CN103178115B (zh)
TW (1) TWI545766B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170021967A (ko) 2015-08-18 2017-03-02 삼성전자주식회사 반도체 장치 제조 방법
JP6740982B2 (ja) * 2017-08-21 2020-08-19 株式会社デンソー 半導体装置
JP6740983B2 (ja) * 2017-08-21 2020-08-19 株式会社デンソー 半導体装置
CN111052323B (zh) * 2017-08-21 2023-06-20 株式会社电装 半导体装置及其制造方法
US11469319B2 (en) * 2020-04-10 2022-10-11 Nanya Technology Corporation Semiconductor device with recessed access transistor and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1722436A (zh) * 2004-07-12 2006-01-18 台湾积体电路制造股份有限公司 半导体装置
US20070007571A1 (en) * 2005-07-06 2007-01-11 Richard Lindsay Semiconductor device with a buried gate and method of forming the same
US20080035990A1 (en) * 2006-08-09 2008-02-14 Hitoshi Matsuura Semiconductor device and method of manufacturing the same
CN101355105A (zh) * 2007-07-27 2009-01-28 精工电子有限公司 半导体装置及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03241865A (ja) * 1990-02-20 1991-10-29 Texas Instr Japan Ltd 半導体装置
JPH08255901A (ja) 1995-03-16 1996-10-01 Nissan Motor Co Ltd 縦型ｍｏｓｆｅｔの製造方法
JP2003101027A (ja) 2001-09-27 2003-04-04 Toshiba Corp 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1722436A (zh) * 2004-07-12 2006-01-18 台湾积体电路制造股份有限公司 半导体装置
US20070007571A1 (en) * 2005-07-06 2007-01-11 Richard Lindsay Semiconductor device with a buried gate and method of forming the same
US20080035990A1 (en) * 2006-08-09 2008-02-14 Hitoshi Matsuura Semiconductor device and method of manufacturing the same
CN101355105A (zh) * 2007-07-27 2009-01-28 精工电子有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
US20130168763A1 (en) 2013-07-04
CN103178115B (zh) 2017-10-03
US8847308B2 (en) 2014-09-30
JP5881100B2 (ja) 2016-03-09
JP2013131695A (ja) 2013-07-04
TW201342609A (zh) 2013-10-16
TWI545766B (zh) 2016-08-11
KR20130079180A (ko) 2013-07-10
KR101960547B1 (ko) 2019-03-20

Similar Documents

Publication Publication Date Title
US6670673B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP4204389B2 (ja) 高電圧縦型ｄｍｏｓトランジスタ及びその製造方法
TWI446537B (zh) 包括一埋入式絕緣層及一貫穿其延伸之垂直導電結構之電子裝置及其形成方法
US7250668B2 (en) Integrated circuit including power diode
JP6092749B2 (ja) 半導体装置及び半導体装置の製造方法
TWI451526B (zh) 半導體元件及其製造方法
CN103137697A (zh) 功率mosfet及其形成方法
CN106024894B (zh) 沟槽栅功率mosfet结构及其制造方法
JP2004342660A (ja) 半導体装置及びその製造方法
JP2008270806A (ja) 半導体素子及びその製造方法
CN103456788A (zh) 垂直功率mosfet及其形成方法
TWI437709B (zh) 包括一配置在通道區下方及具有高於通道區之摻雜物濃度之摻雜區的電子裝置及其形成方法
CN103178115A (zh) 半导体装置及其制造方法
CN102386233B (zh) 半导体器件
TWI503983B (zh) 半導體裝置及其製造方法
JP2014127547A (ja) 半導体装置の製造方法
KR101469343B1 (ko) 수직 파워 ｍｏｓｆｅｔ 및 그 제조 방법
KR20150118764A (ko) 반도체 소자 및 그 제조 방법
CN101901751B (zh) 半导体元件及其制造方法
JP2013251467A (ja) 半導体装置および半導体装置の製造方法
CN104425344A (zh) 半导体结构及其形成方法
CN206210805U (zh) 半导体组件及屏蔽栅极半导体组件
CN110875396A (zh) 沟槽式栅极金氧半场效晶体管及其制造方法
CN113555357A (zh) 电荷耦合场效应晶体管嵌入的单片电荷耦合场效应整流器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160330

Address after: Chiba County, Japan

Applicant after: SEIKO INSTR INC

Address before: Chiba County, Japan

Applicant before: Seiko Instruments Inc.

GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: EPPs Lingke Co. Ltd.

Address before: Chiba County, Japan

Patentee before: SEIKO INSTR INC

CP01 Change in the name or title of a patent holder
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171003

Termination date: 20201221

CF01 Termination of patent right due to non-payment of annual fee