CN113555357A - 电荷耦合场效应晶体管嵌入的单片电荷耦合场效应整流器 - Google Patents

电荷耦合场效应晶体管嵌入的单片电荷耦合场效应整流器 Download PDF

Info

Publication number
CN113555357A
CN113555357A CN202110441871.7A CN202110441871A CN113555357A CN 113555357 A CN113555357 A CN 113555357A CN 202110441871 A CN202110441871 A CN 202110441871A CN 113555357 A CN113555357 A CN 113555357A
Authority
CN
China
Prior art keywords
region
gate
integrated circuit
semiconductor layer
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110441871.7A
Other languages
English (en)
Inventor
李欣蓓
阮文征
M·G·卡斯托里纳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
STMicroelectronics SRL
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of CN113555357A publication Critical patent/CN113555357A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本公开的实施例涉及电荷耦合场效应晶体管嵌入的单片电荷耦合场效应整流器。集成电路包括MOSFET器件和单片二极管器件，其中单片二极管器件与MOSFET器件的本体二极管并联电连接。单片二极管器件被配置，使得单片二极管器件的正向压降VfD2小于MOSFET器件的本体二极管的正向压降VfD1。通过控制栅极氧化物厚度、沟道长度和本体掺杂浓度水平，正向压降VfD2是工艺可调谐的。正向压降VfD2的可调谐性有利地允许根据开关速度和效率的要求的集成电路的设计以适合广泛的应用。

Description

电荷耦合场效应晶体管嵌入的单片电荷耦合场效应整流器
相关申请的交叉应用
本申请要求2020年4月24日提交的美国临时专利申请No.63/014,973的优先权，该申请的公开内容通过引用合并于此。
技术领域
本发明总体上涉及单片集成电路器件，并且特别地涉及单片集成电路场效应晶体管器件。更特别地，本发明考虑了嵌入在电荷耦合场效应晶体管中的单片电荷耦合场效应整流器器件(例如，二极管)的集成。电荷耦合场效应整流器器件的正向压降根据开关速度和效率的要求是工艺可调谐的，以满足广泛的应用。
背景技术
参考图1，示出了功率金属氧化物半导体场效应晶体管(MOSFET)器件10的电路图。功率MOSFET 10包括栅极G、源极S和漏极D。在该实施例中，功率MOSFET 10是n沟道器件，并且因此源极S和漏极D由n型掺杂的半导体区域来形成，以及沟道(和本体B)由p型掺杂的半导体区域来形成。本体B被电系接到源极S。MOSFET10的本体二极管D1由pn结来形成，pn结具有由本体B的p型掺杂区域形成的阳极和由漏极D的n型区域形成的阴极。
在开关电路应用中，当功率MOSFET 10被栅极控制为导通时，本体二极管D1处于反向模式。当功率MOSFET 10随后关断时，本体二极管D1在其反并联电路配置中将以正向模式接通。本体二极管D1可以例如具有大约0.7V的正向压降(Vf)。然而，该正向压降太高而无法支持针对更快的开关速度和更高效率的工业需求。
因此，在本领域中需要解决前述问题。
发明内容
在实施例中，一种集成电路包括：掺杂有第一类型的掺杂剂的半导体层，具有MOSFET器件和单片集成在半导体层中的二极管器件，其中二极管器件与MOSFET器件的本体二极管并联电连接。MOSFET器件包括：第一沟槽，在所述半导体层中；半导体层的第一区域，在半导体层的顶表面处掺杂有第一类型的掺杂剂；半导体层的第三区域，掺杂有与第一类型相对的第二类型的掺杂剂，并且被放置在第一区域与由半导体层形成的第一漂移区域之间；以及第一栅极电极，位于第一沟槽内，并且通过具有第一厚度的第一栅极氧化物层与第一区域和第三区域分离。二极管器件包括：第二沟槽，在所述半导体层中；半导体层的第二区域，在半导体层的顶表面处掺杂有第一类型的掺杂剂，其中第一区域和第二区域彼此分离；第四区域，掺杂有第二类型的掺杂剂，并且被放置在第二区域与由半导体层形成的第二漂移区域之间；以及第二栅极电极，位于第二沟槽内，并且通过具有比第一厚度小的第二厚度的第二栅极氧化物层与第二区域和第四区域分离。
在实施例中，一种集成电路包括：掺杂有第一类型的掺杂剂的半导体层，具有MOSFET器件和单片集成在半导体层中的二极管器件。MOSFET器件包括：漏极区域，由半导体层形成；本体区域，在半导体层内；源极区域，在半导体层内；以及第一绝缘沟槽，延伸穿过源极区域和本体区域，并且包括第一栅极。二极管器件包括：阴极区域，由半导体层形成；阳极区域，在半导体层内；以及第二绝缘沟槽，延伸穿过阳极区域，并且包括第二栅极。第一金属层与半导体层电接触以形成用于MOSFET器件的漏极电极和用于二极管器件的阴极电极。第二金属层与第一栅极电接触，以形成用于MOSFET器件的栅极电极。第三金属层与源极区域电接触以形成用于MOSFET器件的源极电极。第四金属层与阳极区域和第二栅极电接触以形成用于阳极器件的阳极电极。
附图说明
为了更好地理解实施例，现在将仅作为示例的方式来参考附图，其中：
图1是功率金属氧化物半导体场效应晶体管(MOSFET)器件的电路图；
图2是具有嵌入式整流二极管的功率MOSFET器件的电路图；
图3A、图3B和图3C示出了被制造为垂直传导晶体管的功率MOSFET的平行横截面；
图4A、图4B和图4C示出了嵌入图3A至图3C的功率MOSFET的整流二极管的平行横截面；
图5示出了具有嵌入式整流二极管的功率MOSFET器件的单片集成电路的布局的俯视图(平面图)；
图6示出了具有嵌入式整流二极管的功率MOSFET器件的单片集成电路的布局的俯视图(平面图)；
图7A示出了图3A横截面的TEM图像；
图7B示出了图4A横截面的TEM图像；以及
图8A至图8H示出了用于单片半导体集成电路器件的制造的工艺步骤。
具体实施方式
参考图2，示出了具有嵌入式整流二极管D2的功率金属氧化物半导体场效应晶体管(MOSFET)器件12的电路图。功率MOSFET 12包括栅极G、源极S和漏极D。在该示例中，功率MOSFET 12是n沟道器件，并且因此源极S和漏极D由n型掺杂半导体区域来形成，以及沟道(和本体B)由p型掺杂半导体区域来形成。本体B被电系接到源极S。MOSFET12的本体二极管D1由pn结来形成，具有由本体B的p型掺杂区域形成的阳极和由漏极D的n型区域形成的阴极。附加的整流二极管D2与本体二极管D1被并联电耦合在本体B(源极S)和漏极D之间。整流二极管D2具有小于本体二极管D1的正向压降VfD1的正向压降VfD2。结果，相对于图1的MOSFET 10，开关速度和效率得到改善。在本文所描述的方式中，正向压降VfD2的值可以是工艺可调谐的。
在优选的实施方式中，功率MOSFET 12被制造为具有整流二极管D2的单片集成电路器件，该整流二极管D2被嵌入在具有本体二极管D1的场效应晶体管的结构中。换言之，MOSFET 12和二极管D2共享共同的半导体衬底。另外，如将在本文中更详细地描述的，晶体管和整流二极管器件可以共享某些共同的结构。
图3A示出了被制造为垂直传导晶体管的功率MOSFET 12的第一横截面。被n型掺杂的半导体衬底20(例如，硅)包括背表面。在衬底20的背表面处的第一金属层22提供用于晶体管12的漏电极。从衬底20的上表面形成例如由硅制成的n型掺杂的外延层24。外延层24比半导体衬底20更轻掺杂，并且形成用于晶体管的漏极的n型漂移区域30。在外延层24的正表面处的更重n型掺杂区域26提供晶体管12的源极区域。n型掺杂区域26的底部从外延层24的正表面间隔开至深度t4(其中深度t4约为0.2μm，例如在0.15μm至0.25μm的范围中)。掩埋在外延层24中的p型掺杂区域28在用于源极的掺杂区域与n型漂移区域30之间提供晶体管12的本体区域。p型掺杂区域28的底部从外延层24的正表面间隔开至深度t2(其中深度t2约为1μm，例如在0.9μm至1.1μm的范围中)。沟槽32在n型漂移区域30的任一侧上的外延层24中形成。沟槽32从外延层24的正表面延伸完全穿过区域26和28，到达比掩埋的p型掺杂区域28的底部更深的深度，但未到达n型掺杂衬底20的顶部。沟槽被填充有绝缘材料34(诸如氧化物形式的介电材料)。场板电极36位于每个沟槽32内。场板电极36可以例如由多晶硅材料制成，该多晶硅材料被沉积在子沟槽38内(形成在绝缘材料34中(或由绝缘材料34形成))并且通过绝缘材料34与外延层24绝缘。栅极点击40也位于在场板电极36的相对侧上的每个沟槽32内。每个栅极点击40可以例如由沉积在子沟槽内的多晶硅材料制成。栅极点击40通过插入的(即，多晶间)氧化物层42a与场板电极36绝缘。栅极点击40通过栅极氧化物层42b还与(外延层24的)半导体区域26、28和30绝缘，该栅极氧化物层42b具有厚度t1(其中厚度t1约为
Figure BDA0003035399570000051
例如在
Figure BDA0003035399570000052
至
Figure BDA0003035399570000053
的范围中)。多晶间氧化物层42a和栅极氧化物层42b的厚度将典型地不同，其中厚度t1更薄。栅极点击40从外延层24的正表面延伸至深度t3(其中深度t3大于深度t2；其中深度t3约为1.3μm，例如在1.2μm至1.4μm的范围中)，并且在横截面的平面中具有宽度w(其中宽度w约为0.45μm，例如在0.4μm至0.5μm的范围中)。在两个相邻沟槽32之间的位置处，更重p型掺杂区域44被掩埋在掩埋的p型掺杂区域28内，以提供到p型掺杂区域28的接触。绝缘层46在外延层24的顶部表面之上延伸(将注意，层46可以是绝缘层的堆叠制造的)。第一开口48在与更重p型掺杂区域44对准的位置处延伸穿过绝缘层46。第一开口48还在外延层的正表面处延伸穿过更重n型掺杂区域26(并且取决于重p型掺杂区域44的定位，还可以部分地延伸穿过用于晶体管的本体的p型掺杂区域28)。第一开口48被填充有金属材料，该金属材料形成晶体管的源极S电极的部分50。将注意，部分50的金属材料与更重n型掺杂区域26和重p型掺杂区域44二者均直接物理接触和电接触，该更重n型掺杂区域26形成源极区域，该重p型掺杂区域44形成到用于晶体管的本体的p型掺杂区域28的接触。在绝缘层46的顶部表面处的第二金属层52提供用于晶体管源极S电极的另一部分。
图3A横截面的TEM图像在图7A中示出。
图3B示出了功率MOSFET 12的第二横截面。图3B的第二横截面在与图3A的第一横截面的平面平行但偏移的平面中制成。相似的附图标记指代相同的组成部分。在图3A和图3B的横截面之间的偏移在正交于那些横截面的平行平面的方向上(即，在进入/离开附图的页面的方向上)。第二开口54在与每个栅极点击40对准的位置处延伸穿过绝缘层46。第二开口54被填充有形成晶体管的栅极点击的部分56的金属材料。将注意，部分56的金属与栅极点击40的多晶硅材料电接触。在绝缘层46的顶部表面处的第三金属层58提供用于晶体管栅极G电极的另一部分。
图3C示出了功率MOSFET 12的第三横截面。图3C的第三横截面在与图3A的第一横截面和第二横截面的平面平行但偏离的平面中制成。相似的附图标记指代相同的组成部分。在图3A、图3B和图3C的横截面之间的偏移在正交于那些横截面的平行平面的方向上(即，在进入/离开附图的页面的方向上)。第三开口60在与每个场板电极36对准的位置处延伸穿过绝缘层46。第三开口60被填充有形成晶体管的源极S电极的另一部分62的金属材料。将注意，部分62的金属与场板电极36的多晶硅材料电接触。在绝缘层46的顶部表面处的第二金属层52为晶体管提供源极S电极的另一部分。
图4A示出了被嵌入图3A至图3C的功率MOSFET 12的单片整流二极管的第一横截面。相似的附图标记指代相同的组成部分。整流二极管的结构可以与功率MOSFET 12的结构共享公共的以下部分：衬底20(这里形成二极管D2的阴极区域)、第一金属层22(这里提供阴极电极)、具有n型漂移区域30的轻掺杂外延层24、沟槽32、绝缘材料34、场板电极36、子沟槽38和绝缘层46。在外延层24的正表面处的更重n型掺杂区域26’提供源极区域。n型掺杂区域26’的底部与外延层24的正表面间隔开至深度t4’(其中深度t4’约为0.15μm，例如在0.1μm至0.2μm的范围中)。掩埋在外延层24中的p型掺杂区域28’在针对源极的掺杂区域和n型漂移区域30之间提供本体区域。结合调谐二极管D2的正向压降VfD2，针对区域28’的p型掺杂剂的掺杂浓度水平被选择。p型掺杂区域28’的底部与外延层24的正表面间隔开至深度t2’(其中深度t2’小于深度t2；其中深度t2’约为0.6μm，例如在0.5μm至0.7μm的范围中)。结合调谐二极管D2的正向压降VfD2，限定沟道长度的p型掺杂区域28’的深度t2’被选择。沟槽32完全延伸穿过区域26’和28’并且终止在外延层24内。栅极电极40’也位于场板电极36的相对侧上的每个沟槽32内。每个栅极电极40’可以例如由多晶硅材料制成。栅极电极40’通过插入的(即，多晶间)氧化物层42a’与场板电极36绝缘。栅极电极还通过栅极氧化物层42b’与(外延层24的)半导体区域26’、28’和30绝缘，该栅极氧化物层42b’具有厚度t1’(其中厚度t1’小于厚度t1；其中厚度t1’约为
Figure BDA0003035399570000071
例如在
Figure BDA0003035399570000072
至
Figure BDA0003035399570000073
的范围中)。结合调谐二极管D2的正向压降VfD2，栅极氧化物层42b’的厚度t1’被选择。栅极电极40’从外延层24的正表面延伸至深度t3’(其中深度t3’大于深度t2’，并且其中深度t3’小于深度t3；其中深度t3’约为0.9μm，例如在0.8μm至1.0μm的范围中)，并且在横截面的平面中具有宽度w’(其中宽度w小于宽度w’；其中宽度w’约为0.6μm，例如在0.55μm至0.65μm的范围中)。在两个相邻沟槽32之间的位置处，更重p型掺杂区域44’被掩埋在掩埋的p型掺杂区域28’内，以提供用于本体区域的接触。第四开口70在与更重p型掺杂区域44’对准的位置处延伸穿过绝缘层46。第四开口70还在外延层的正表面处延伸穿过更重n型掺杂区域26’(并且可以取决于重p型掺杂区域44’的定位，还部分地延伸穿过用于晶体管的本体的p型掺杂区域28’)。第四开口70被填充有金属材料，该金属材料形成整流二极管D2的阳极A电极的部分72。将注意，部分72的金属材料与更重n型掺杂区域26’和重p型掺杂区域44’二者直接物理接触和电接触，该更重n型掺杂区域26’形成源极区域，该重p型掺杂区域44’形成到用于本体的p型掺杂区域28’的接触。在绝缘层46的顶部表面处的第四金属层74提供阳极A电极的另一部分。第四金属层74电连接(短路)到第二金属层52(并且在实施例中，层52和74可以包括相同的金属层)。将注意，金属层22也呈现并且形成阴极C电极的部分。
图4A横截面的TEM图像被示出在图7B中。
在实施例中，图4A的第一横截面在与针对功率MOSFET12的图3A、图3B和图3C的第一横截面、第二横截面和第三横截面的平面平行但偏移的平面中制成。在图3A、图3B、图3C和图4A的横截面之间的偏移在正交于那些横截面的平行平面的方向上(即，在进入/离开附图的页面的方向上)。
图4B示出了整流二极管的第二横截面。图4B的第二横截面在与图4A的第一横截面的平面平行但偏移的平面中制成。相似的附图标记指代相同的组成部分。在图4A与图4B的横截面之间的偏移在正交于那些横截面的平行平面的方向上(即，在进入/离开附图的页面的方向上)。在与每个栅极电极40’对准的位置处，第五开口76延伸穿过绝缘层46。第五开口76被填充有形成阳极电极的部分78的金属材料。将注意，部分78的金属与栅极电极40’的多晶硅材料电接触。在绝缘层46的顶部表面处的第四金属层74提供阳极A电极的另一部分。
图4C示出了整流二极管的第三横截面。图4C的第三横截面分别在与图4A和图4B的第一横截面和第二横截面的平面平行但偏移的平面中制成。相似的附图标记指代相同的组成部分。图4A、图4B和图4C的横截面之间的偏移在正交于那些横截面的平行平面的方向上(即，在进入/离开附图的页面的方向上)。在与每个场板电极36对准的位置处，第六开口80延伸穿过绝缘层46。第六开口80被填充有形成阳极A电极的部分82的金属材料。将注意，部分82的金属与场板电极36的多晶硅材料电接触。在绝缘层46的顶部表面处的第四金属层74提供阳极A电极的另一部分。
现在参考图5，示出了针对具有嵌入式整流二极管D2的功率金属氧化物半导体场效应晶体管(MOSFET)器件12的单片集成电路的布局的俯视图(平面图)。平面图在对应于区域26和26’的外延层24的上表面的水平处被图示。区域44和44’的相对位置由虚线示出，因为这些区域被掩埋在区域26和26’下方。区域28和28’未示出，但通常具有与区域26和26’相同的平面布局。电极部分50、56、62、72、78和82被示出，应理解，所包括的部分的数目及它们的位置仅作为示例来示出，并且在实施例中，所提供的每个部分很可能将存在多个。另外，仅一对沟槽的图示仅作为示例，并且在优选的实施方式中，其布局将包括彼此平行布置的多个沟槽对(例如，平行于在图示中所示的一对沟槽的左边和右边)。在该示例中，沟槽32及它的场板电极36是在顶部处的MOSFET 12与底部处的二极管D2之间的共享结构。在备选实施方式中，MOSFET 12和二极管D2可以备选地具有分离的沟槽32和场板电极36结构。
现在参考图6，示出了针对具有嵌入式整流二极管的功率金属氧化物半导体场效应晶体管(MOSFET)器件12的单片集成电路的布局的俯视图(平面图)。平面图在对应于区域26和26’的外延层24的上表面的水平处被图示。在该布局中，针对具有嵌入式整流二极管D2的MOSFET器件12的结构被并排布置(与如图5中所示的对准的布局相对)。将理解，如针对在图6中的MOSFET器件12的布局的左边所示的嵌入式整流二极管D2的布局可以被复制在针对MOSFET器件12的布局的右边。此外，如上面结合图5的布局所注意的，仅一对沟槽的图示仅作为示例，并且在优选的实施方式中，MOSFET器件12和嵌入式整流二极管D2中的每个的布局将包括多个沟槽对。
图5至图6的平面图仅是布局配置的示例。图示未按比例绘制。另外，图示未示出针对完整的单片器件的布局。如本领域技术人员所公知的，所图示的布局结构可以被重复多次并且以平铺或单元的方式来布置。
图8A至图8H示出了用于具有嵌入式整流二极管D2的MOSFET器件12的栅极40、40’和栅极氧化物层42、42’的制造的工艺步骤。将注意，图8A至图8H中的每个附图的左侧示出了MOSFET器件12(具有D1)正在被制造的定位，并且图8A至图8H中的每个附图的右侧示出了嵌入式整流二极管D2正在被制造的定位。图8A至图8H的步骤仅是说明性的，并且未示出所有结构或所有单独的工艺步骤。附图未按比例呈现。
在图8A中，本领域技术人员已公知的标准制造工艺已被执行以产生沟槽32、绝缘材料34、子沟槽38和场板电极36。作为工艺的示例：沟槽32通过蚀刻工艺在外延层24中被产生。保形的绝缘材料层被沉积以排列每个沟槽并且限定子沟槽38；然后多晶硅材料被沉积以填充每个子沟槽；抛光操作被执行以去除过量的多晶硅材料并且限定场板电极36。
在图8B中，掩模100在MOSFET器件12正被制造的定位上被提供。然后蚀刻被执行以去除在沟槽的上部分处的绝缘材料34的部分，该沟槽在嵌入式整流二极管D2正被制造的定位中。这里蚀刻被执行至深度t3’。
在图8C中，热氧化被执行以在由于图8B中的蚀刻而暴露的外延层24(在区域26’、28’和30处)的表面上生长具有厚度t1’的栅极氧化物42b’，通过控制热氧化的参数，结合调谐二极管D2的正向压降VfD2，厚度t1’可以被选择。将注意，该热氧化步骤还将产生多晶间氧化物层42a’。
在图8D中，多晶硅材料被沉积以填充开口并且形成栅极40’。
在图8E中，掩模102在嵌入式整流二极管D2正被制造的定位上被提供。然后蚀刻被执行以去除在沟槽的上部分处的绝缘材料34的部分，该沟槽在MOSFET器件12正被制造的定位中。这里蚀刻被执行至深度t3。
在图8F中，热氧化被执行以在由于图8E中的蚀刻而暴露的外延层24(在区域26’、28’和30处)的表面上生长具有厚度t1的栅极氧化42b。将注意，该热氧化步骤还将产生多晶间氧化物层42a。
在图8G中，多晶硅材料被沉积以填充开口并且形成栅极40。
制造工艺继续公知的掩模和掺杂剂注入步骤的使用，以形成针对晶体管12(左侧)的区域26和28和针对整流二极管D2(右侧)的区域26’和28’。结果在图8H中被示出。通过控制注入工艺的参数，结合调谐二极管D2的正向压降VfD2，区域28’中的厚度t2’和掺杂剂浓度可以被选择。
尽管已经在附图和前面的描述中详细地图示和描述了本发明，但该图示和描述被认为是说明性或示例性的，而不是限制性的；本发明不限于所公开的实施例。通过附图的研究、公开和所附权利要求，本领域技术人员在实践所要求保护的发明时可以理解和影响所公开的实施例的其他变型。

Claims (26)

1.一种集成电路，包括：
半导体层，掺杂有第一类型的掺杂剂；
MOSFET器件，包括：
第一沟槽，在所述半导体层中；
所述半导体层的第一区域，在所述半导体层的顶部表面处掺杂有所述第一类型的掺杂剂；
所述半导体层的第三区域，掺杂有与所述第一类型相对的第二类型的掺杂剂，并且被定位在所述第一区域与由所述半导体层形成的第一漂移区域之间；以及
第一栅极，位于所述第一沟槽内，并且通过具有第一厚度的第一栅极氧化物层与所述第一区域以及所述第三区域分离；
二极管器件，包括：
第二沟槽，在所述半导体层中；
所述半导体层的第二区域，在所述半导体层的顶部表面处掺杂有所述第一类型的掺杂剂，其中所述第一区域和所述第二区域彼此分离；
第四区域，掺杂有所述第二类型的掺杂剂，并且被定位在所述第二区域与由所述半导体层形成的第二漂移区域之间；以及
第二栅极，位于所述第二沟槽内，并且通过具有比所述第一厚度小的第二厚度的第二栅极氧化物层与所述第二区域以及所述第四区域分离；
其中所述二极管器件与所述MOSFET器件的本体二极管并联电连接。
2.根据权利要求1所述的集成电路，其中所述第一沟槽和所述第二沟槽是相同的沟槽。
3.根据权利要求1所述的集成电路，其中所述第一沟槽和所述第二沟槽是不同的沟槽。
4.根据权利要求1所述的集成电路，其中所述半导体层是由半导体衬底支撑的外延层。
5.根据权利要求1所述的集成电路：
其中所述MOSFET器件还包括第一场板，所述第一场板位于所述第一沟槽内，并且通过第一插入的氧化物层与所述第一栅极分离；以及
其中所述二极管器件还包括第二场板，所述第二场板位于所述第二沟槽内，并且通过第二插入的氧化物层与所述第二栅极分离。
6.根据权利要求5所述的集成电路：
其中所述MOSFET器件还包括源极电极，所述源极电极电连接到所述第一区域和所述第一场板；
其中所述二极管器件还包括阳极电极，所述阳极电极电连接到所述第二区域和所述第二场板；以及
其中所述源极电极和阳极电极彼此电连接。
7.根据权利要求6所述的集成电路，还包括：
用于所述MOSFET器件的栅极电极，电连接到所述第一栅极；以及
其中所述阳极电极还电连接到第二栅极。
8.根据权利要求1所述的集成电路，其中所述MOSFET器件还包括：
第五区域，在所述第三区域内，所述第五区域比所述第三区域更重地掺杂有所述第二类型的掺杂剂；
源极电极，电连接到所述第一区域和所述第五区域。
9.根据权利要求1所述的集成电路，其中所述二极管器件包括：
第六区域，在所述第四区域内，所述第六区域比所述第四区域更重地掺杂有所述第二类型的掺杂剂；以及
阳极电极，电连接到所述第二区域和所述第六掺杂区域。
10.根据权利要求9所述的集成电路，其中所述阳极电极还电连接到所述第二栅极。
11.根据权利要求1所述的集成电路，其中所述二极管器件的正向压降小于所述MOSFET器件的所述本体二极管的正向压降。
12.根据权利要求1所述的集成电路，还包括：
所述MOSFET器件的漏极电极，电连接到所述半导体层；以及
所述二极管器件的阴极电极，电连接到所述半导体层。
13.根据权利要求12所述的集成电路，其中所述半导体层是由半导体衬底支撑的外延层，并且其中所述漏极电极和所述阴极电极位于所述半导体衬底的背表面处。
14.根据权利要求1所述的集成电路，其中所述第一区域的厚度大于所述第二区域的厚度。
15.根据权利要求1所述的集成电路，其中所述第三区域的底部的深度大于所述第四区域的底部的深度。
16.根据权利要求1所述的集成电路，其中所述第一栅极的宽度小于所述第二栅极的宽度。
17.根据权利要求1所述的集成电路，其中所述第一栅极的深度大于所述第二栅极的深度。
18.根据权利要求1所述的集成电路，其中所述第二厚度以及所述第四区域的深度和掺杂水平被工艺调谐，以将所述二极管器件的正向压降设置为小于所述MOSFET器件的所述本体二极管的正向压降。
19.一种集成电路，包括：
半导体层，掺杂有第一类型的掺杂剂；
MOSFET器件，包括：
漏极区域，由所述半导体层形成；
本体区域，在所述半导体层内；
源极区域，在所述半导体层内；以及
第一绝缘沟槽，延伸穿过所述源极区域和所述本体区域，并且包括第一栅极；
二极管器件，包括：
阴极区域，由所述半导体层形成；
阳极区域，在所述半导体层内；以及
第二绝缘沟槽，延伸穿过所述阳极区域，并且包括第二栅极；第一金属层，与所述半导体层电接触，以形成用于所述MOSFET器件的漏极电极和用于所述二极管器件的阴极电极；
第二金属层，与所述第一栅极电接触，以形成用于所述MOSFET器件的栅极电极；
第三金属层，与所述源极区域电接触，以形成用于所述MOSFET器件的源极电极；以及
第四金属层，与所述阳极区域以及所述第二栅极电接触，以形成用于所述阳极器件的阳极电极。
20.根据权利要求19所述的集成电路，其中所述第三金属层与所述第四金属层电连接，使得所述二极管器件与所述MOSFET器件的本体二极管并联电连接。
21.根据权利要求20所述的集成电路，其中所述二极管器件的正向压降小于所述MOSFET器件的所述本体二极管的正向压降。
22.根据权利要求19所述的集成电路，其中所述第一绝缘沟槽和所述第二绝缘沟槽是相同的绝缘沟槽。
23.根据权利要求19所述的集成电路，其中所述第一绝缘沟槽和所述第二绝缘沟槽是不同的绝缘沟槽。
24.根据权利要求19所述的集成电路，其中所述第一绝缘沟槽的所述第一栅极通过具有第一厚度的第一栅极氧化物层与所述源极区域以及所述本体区域分离，并且其中所述第二绝缘沟槽的所述第二栅极通过具有小于所述第一厚度的第二厚度的第二栅极氧化物层与所述阳极区域分离。
25.根据权利要求24所述的集成电路：
其中所述MOSFET器件还包括第一场板，所述第一场板位于所述第一绝缘沟槽内，并且通过第一插入的氧化物层与所述第一栅极分离；以及
其中所述二极管器件还包括第二场板，所述第二场板位于所述第二绝缘沟槽内，并且通过第二插入的氧化物层与所述第二栅极分离。
26.根据权利要求25所述的集成电路：
其中所述第三金属层还与所述第一场板电接触；以及
其中所述第四金属层还与所述第二场板电接触。
CN202110441871.7A 2020-04-24 2021-04-23 电荷耦合场效应晶体管嵌入的单片电荷耦合场效应整流器 Pending CN113555357A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063014973P 2020-04-24 2020-04-24
US63/014,973 2020-04-24
US17/217,689 2021-03-30
US17/217,689 US11502192B2 (en) 2020-04-24 2021-03-30 Monolithic charge coupled field effect rectifier embedded in a charge coupled field effect transistor

Publications (1)

Publication Number Publication Date
CN113555357A true CN113555357A (zh) 2021-10-26

Family

ID=75625436

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202110441871.7A Pending CN113555357A (zh) 2020-04-24 2021-04-23 电荷耦合场效应晶体管嵌入的单片电荷耦合场效应整流器
CN202120848694.XU Active CN215731715U (zh) 2020-04-24 2021-04-23 集成电路

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202120848694.XU Active CN215731715U (zh) 2020-04-24 2021-04-23 集成电路

Country Status (3)

Country Link
US (1) US11502192B2 (zh)
EP (1) EP3902015A1 (zh)
CN (2) CN113555357A (zh)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0746042B1 (en) 1995-06-02 2004-03-31 SILICONIX Incorporated Bidirectional blocking trench power MOSFET
DE102010063314B4 (de) 2010-12-17 2022-10-13 Robert Bosch Gmbh Halbleiteranordnung mit verbesserter Avalanchefestigkeit
DE102015103067B3 (de) * 2015-03-03 2016-09-01 Infineon Technologies Ag Halbleitervorrichtung mit trenchgatestrukturen in einem halbleiterkörper mit hexagonalem kristallgitter
JP7057044B2 (ja) * 2018-02-22 2022-04-19 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
EP3902015A1 (en) 2021-10-27
CN215731715U (zh) 2022-02-01
US20210336047A1 (en) 2021-10-28
US11502192B2 (en) 2022-11-15

Similar Documents

Publication Publication Date Title
US6670673B2 (en) Semiconductor device and method for manufacturing semiconductor device
US20230246107A1 (en) Vertical trench gate mosfet with integrated schottky diode
CN100485961C (zh) 具有增强的屏蔽结构的金属氧化物半导体器件
US8222115B2 (en) Method of forming a high capacitance diode
US10861965B2 (en) Power MOSFET with an integrated pseudo-Schottky diode in source contact trench
US10468402B1 (en) Trench diode and method of forming the same
CN101083284A (zh) 具有槽电荷补偿区的半导体器件及方法
JP2013258327A (ja) 半導体装置及びその製造方法
US10164087B2 (en) Semiconductor device and method of manufacturing same
JP2008529279A (ja) パワーダイオードを包含する集積回路
US9929259B2 (en) Semiconductor device and manufacturing method for semiconductor device
US20210242342A1 (en) Semiconductor device and method for manufacturing same
US20130093066A1 (en) Semiconductor device
US20020060339A1 (en) Semiconductor device having field effect transistor with buried gate electrode surely overlapped with source region and process for fabrication thereof
JP2012049466A (ja) 半導体装置およびその製造方法
US10651277B2 (en) Semiconductor device and method of manufacturing the same
US20080111197A1 (en) Semiconductor device including a misfet having divided source/drain regions
US20210296161A1 (en) Semiconductor Device and Method for Manufacturing Same
CN215731715U (zh) 集成电路
KR20160030030A (ko) 반도체 장치
US20090250750A1 (en) Trench gate power mosfet
CN109980010B (zh) 一种半导体器件的制造方法和集成半导体器件
RU2810689C1 (ru) Полупроводниковая структура и способ ее изготовления
WO2023127253A1 (ja) 半導体装置
CN116033741A (zh) 半导体结构及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination