TW201342609A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201342609A
TW201342609A TW101147456A TW101147456A TW201342609A TW 201342609 A TW201342609 A TW 201342609A TW 101147456 A TW101147456 A TW 101147456A TW 101147456 A TW101147456 A TW 101147456A TW 201342609 A TW201342609 A TW 201342609A
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trench
diffusion layer
gate electrode
layer
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Masayuki Hashitani
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Seiko Instr Inc
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Abstract

[課題]提供具備有小型之溝槽構造的縱型MOS電晶體。[解決手段]在以一定間隔連續的溝槽間之基板及之後設置有源極高濃度擴散層之矽表面區域製作STI之氧化膜，於溝槽形成後除去，形成較周圍表面低之區域，依此被填埋在具備有溝槽構造的縱型MOS電晶體之溝槽道之閘極電極上和基板及源極高濃度擴散層上之矽化物可分離，且該溝槽構造具有側間隔物，依此因面積縮小故可縮小溝槽的尺寸，和成為半導體裝置之高驅動能力化。

Description

半導體裝置及其製造方法
本發明係關於半導體裝置，尤其關於具備有溝槽構造之縱型MOS電晶體。
以電壓調節器、電壓檢測器為代表之電源IC之晶片尺寸縮小，在電壓調節器中，有輸出電流增加之傾向。因在構成其電源IC之元件中，用以流通電流之驅動元件佔據晶片面積之大部分，故至今藉由採用具備有溝槽構造之MOS電晶體，謀求面積縮小和藉由增大有效的通道寬度而取得高驅動能力化。
關於具備有以往之溝槽構造之半導體裝置及其製造方法，在例如專利文獻1或專利文獻2中被介紹。
針對具備有以往之溝槽構造之縱型MOS電晶體之製造方法，以第4圖為根據而與以說明。第4圖為藉由表示製造方法之模式剖面圖的工程順序程序。
首先，如第4圖(A)所示般，具有第2導電型填埋層22，在具備溝槽構造之區域，形成有第1導電型井擴散層23(被稱為主體)，在其表面以熱氧化膜24及堆積氧化膜25疊層。以抗蝕膜26圖案製作該些氧化膜而進行用以當作溝槽蝕刻用之硬遮罩的蝕刻。接著，如第4圖(B)所示般，於除去抗蝕膜26之後，使用以被圖案製作之熱氧化膜24及堆積氧化膜25所疊層之硬遮罩而藉由蝕刻 形成溝槽道27。接著，如第4圖(C)所示般，除去當作硬遮罩使用之熱氧化膜24及堆積氧化膜25之後，以熱氧化形成用以改善溝槽道27之形狀的犧牲氧化膜28。
之後，如第4圖(D)所示般，除去犧牲氧化膜28，而以熱氧化形成閘極絕緣膜29，並且堆積被摻雜雜質之摻雜多晶矽膜30。然後，如第4圖(E)所示般，以抗蝕膜32圖案製作而對摻雜多晶矽膜30進行過蝕刻而取得閘極電極31。並且，如第4圖(F)所示般，對抗蝕膜33進行圖案製作而進行用以形成源極區域之第2導電型之雜質添加，接著，如第4圖(G)所示般，重新圖案製作抗蝕膜34而進行用以形成基板電位區域的第1導電型之雜質添加。
之後，如第4圖(H)所示般，以熱處理形成第2導電型源極高濃度擴散層35及第1導電型基板電位高濃度擴散層36。接著，於堆積層間絕緣膜37之後，形成用以取得閘極電極31、第2導電型源極高濃度擴散層35及第1導電型基板電位高濃度擴散層36之電性連接的觸孔38，填埋鎢等之插塞，形成源極基板共通電位配線40及閘極電位配線39。
依此，具備有被形成在第1導電型井擴散層23之溝槽道27，具備有在縱方向動作之溝槽構造之縱型MOS電晶體之元件構造完整。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2003-101027號公報
[專利文獻2]日本特開平8-255901號公報
但是，在具備有溝槽構造之縱型MOS電晶體中，當為了降低用以取得被填埋至溝槽道之閘極電極之電性連接的接觸電阻，實施自動對準矽化時，有被填埋在溝槽道之閘極電極上和與溝槽道鄰接之基板及源極高濃度擴散層之矽化物導通之問題。因此，閘極電極上之矽化困難，當為了縮小晶片面積而縮小溝槽道之寬度之尺寸時，有增大閘極電極之電阻之問題。
本發明係以提供被填埋至溝槽道之閘極電極上和基板及源極高濃度擴散層之矽化可分離，用以縮小面積之溝槽之尺寸，並可高驅動能力化之半導體裝置及其製造方法為課題。
為了解決上述課題，本發明使用下述手段。
首先，為一種半導體裝置，其特徵為具有：第1導電型半導體基板；夾著第2導電型填埋層而被設置在第1導電型半導體基板上的第1導電型磊晶成長層；被形成在第2導電型填埋層之上的第1導電型磊晶成長層之一部分上 的第1導電型井擴散層；被配置成格子狀或帶狀的互相連結之溝槽道，其係以從第1導電型井擴散層到達至第2導電型填埋層之深度所形成；被形成在溝槽道之表面的閘極絕緣膜和隔著閘極絕緣膜而填充溝槽道，突出較第1導電型井擴散層表面高之閘極電極的多晶矽膜；被形成在閘極電極之側面的側間隔物；被形成在第1導電型井擴散層之非溝槽道的島狀區域之表面上的第2導電型源極高濃度擴散層及第1導電型基板電位擴散層；被形成在閘極電極表面的矽化物層；和被形成在第2導電型源極高濃度擴散層及第1導電型基板電位擴散層之表面的矽化物層，被形成在閘極電極表面的矽化物層和第2導電型源極高濃度擴散層及第1導電型基板電位擴散層之表面的矽化物層係藉由側間隔物而分離。
再者，第2導電型源極高濃度擴散層係被形成在非溝槽道之島狀區域之表面的碟形狀之底部及周圍隆起區域。
然後，就以上述記載之半導體裝置之製造方法而言，藉由蝕刻除去以STI(Shallow Trench Isolation：淺溝槽隔離)產生的填埋氧化膜之厚膜氧化膜而形成非溝槽道之島狀區域之表面的碟形狀。
如上述般，在具備有溝槽構造之縱型MOS電晶體中，藉由在以一定間隔連續的溝槽道間，為了使基板及源極高濃度擴散層電性連接而設置的不成為溝槽道之區域作成 厚膜氧化膜之後予以除去，形成周圍高且內部低之區域。藉由利用被形成在周圍的區域，形成具備有溝槽構造之縱型MOS電晶體，且其具有側間隔物，被填埋至溝槽道之閘極電極上和基板及源極高濃度擴散層之矽化物成為可分離。藉由使用該構造，可以取得能夠因縮小面積而縮小溝槽之尺寸，並可高驅動能力化之半導體裝置。
以下，針對本發明之型態，參考圖面而予以說明。第1圖及第2圖為用以表示本發明之半導體裝置之製造方法之實施例的模式性剖面圖之工程順序流程。該些模式性剖面圖係在相當於在第3圖(A)之俯視圖中表示的本發明之半導體裝置之實施例中的B-B剖面之位置中切斷的圖示。
如第1圖(A)所示般，將使具有砷、磷、銻等之N型雜質從1×1016atom/cm3擴散至1×1018atom/cm3左右之濃度之第2導電型填埋層1的第1導電型磊晶成長層，以成長層厚從數μm成為數十μm之方式，在以電阻率從20 Ω cm成為30 Ω cm之方式添加成為雜質之硼的P型半導體基板之第1導電型半導體基板上成長者當作基板。
並且，之後在具備溝槽構造之區域，使用硼或二氟化硼等之雜質而以從1012atom/cm2到1013atom/cm2之摻雜量進行離子注入而形成也被稱為主體之第1導電型井擴散層2。若上述第2導電型填埋層1為例如P型填埋層時， 則以硼等之雜質成為上述濃度之方式進行雜質添加。適當選擇第1導電型半導體基板、第2導電型填埋層1及第1導電型磊晶成長層之各個的導電型。
然後，之後將在具備有溝槽構造之領域中為本發明之特徵之一的厚膜氧化膜3，例如以元件分離用之STI(Shallow Trench Isolation)為代表之填埋氧化膜設為膜厚數十nm，具備在第1導電型井擴散層2之不成為溝槽道之島狀區域。在此，厚膜氧化膜3在島狀區域之周圍變薄，在內部變厚，具有一定膜厚。厚膜氧化膜3之周邊形狀成為研缽狀或碟之邊緣狀。即是，在島狀區域中接近於溝槽道之周圍，第1導電型井擴散層2成為隆起的隆起區域，以包圍其內部而構成底部。並且，在第1導電型井擴散層2之表面及厚膜氧化膜3之表面，圖案製作並配置用以溝槽蝕刻用之硬遮罩4。此時之硬遮罩4若在之後的溝槽蝕刻中取得足夠之耐性時，亦可成為熱氧化膜或堆積氧化膜中之單層構造，即使在抗蝕膜或氮化膜也不會造成問題。
接著，使用硬遮罩4而藉由蝕刻形成溝槽道5。溝槽道5之深度係以形成溝槽底部到達至第2導電填埋層1為佳。第1圖(A)表示該狀態。並且，溝槽道5之俯視形狀如第3圖(A)及第3圖(B)所示般，即使為格子狀或帶狀亦可。在此，即使在元件俯視圖之第3圖(A)及(B)中之任一者皆表示具備有溝槽構造之縱型MOS電晶體之基本單元。在實際之半導體裝置中，於晶片內以至少 數百至數千個之層級來積體如此的基本單元。
然後，如第1圖(B)所示般，除去硬遮罩4之後，以例如膜厚從數nm至數十nm之熱氧化形成用以改善溝槽道5之形狀的犧牲氧化膜6。
之後，如第1圖(C)所示般，當除去犧牲氧化膜6之時，同樣也除去厚膜氧化膜3，依此除去的厚膜氧化膜3之區域被形成低於周圍平面。在此，成為本實施例之特徵之一。即是，島狀區域之非溝槽道區域之第1導電型井擴散層2之表面係周圍隆起，內部低且平的碟形狀。接著，在溝槽道5及第1導電型井擴散層2表面以例如膜厚從數百Å至數千Å之熱氧化膜形成閘極絕緣膜7。並且，理想上以膜厚100nm至500nm堆積摻雜多晶矽膜之後，以抗蝕膜8圖案製作進行過蝕刻而取得在溝槽道5填埋摻雜多晶矽膜之閘極電極9。抗蝕膜8因以覆蓋溝槽道5之上方之方式，被圖案製作，故閘極電極9表面較第1導電型井擴散層2表面突出，成為比碟形狀之最高周圍部分之隆起區域更高之形狀。
之後，如第1圖(D)所示般，除去抗蝕膜8而以例如膜厚數百nm疊層堆積氧化膜10。接著，如第1圖(E)所示般，藉由回蝕堆積氧化膜10，在閘極電極9側面形成側間隔物11。接著，以例如膜厚數十nm堆積用以對源極高濃度擴散層及基板電位高濃度擴散層進行離子注入的堆積氧化膜12。
並且，如第2圖(A)所示般，以抗蝕膜13圖案製 作而利用離子注入法進行用以形成源極區域之第2導電型之雜質添加。被雜質注入之區域為閘極電極9側方之第1導電型井擴散層2之表面附近。
並且，如第2圖(B)所示般，除去抗蝕膜13之後，以覆蓋閘極電極9及側間隔物11之方式重新圖案製作抗蝕膜14，而利用離子注入法進行用以形成基板電位區域之第1導電型之雜質添加。關於第2圖(A)及第2圖(B)之離子注入，導電型若為N型，理想以1×1018 atom/cm2至1×1016atom/cm2之摻雜量對例如砷、磷進行離子注入。另外，若導電型為P型，理想以1×1015 atom/cm2至1×1016atom/cm2之摻雜量對砷或二氟化砷進行離子注入。並且，在此對源極區域及基板電位區域進行的雜質添加，即使與對不具備溝槽道5之相同晶片內之MOS電晶體源極區域添加雜質同時進行亦可。
之後，如第2圖(C)所示般，藉由以800℃~1000℃在數小時進行熱處理，在閘極電極9側方之第1導電型井擴散層2表面形成第2導電型源極高濃度擴散層15，然後在複數之第2導電型源極高濃度擴散層15之間等形成第1導電型基板電位高濃度擴散層16。此時，因第1導電型井擴散層2表面成為周圍隆起之碟形狀，故第2導電型源極高濃度擴散層15係不僅在碟形狀之底部區域，也形成在周圍之隆起區域。
依此，具備有被形成在第1導電型井擴散層2之溝槽道5，具備有在縱方向動作之溝槽構造之縱型MOS電晶 體之基本構造完整。接著，於除去堆積氧化膜12之後，以數十nm堆積自動對準矽化之金屬膜17，例如鈷或鎢等。
接著，如第2圖(D)所示般，藉由以RTA等在數十秒到數分間進行例如從800℃到1000℃的熱處理，在閘極電極9及第2導電型源極高濃度擴散層15及第1導電型基板電位高濃度擴散層16之共通部分形成矽化物18。此時，在側間隔物11表面不形成矽化物，自行整合地形成矽化物(鎢矽化物構造)。再者，雖然在第2導電型源極高濃度擴散層15上之碟形狀之底部區域，形成矽化物，但在周圍的隆起區域不形成矽化物。依此，閘極電極9上之矽化物18和第2導電型源極高濃度擴散層15上之矽化物18持有充分之距離而分離。
之後，如第2圖(E)所示般，以例如膜厚數百nm至1μm疊層層間絕緣膜19之後，形成用以取得閘極電極9、第2導電型源極高濃度擴散層15及第1導電型基板電位濃度擴散層16之共通部分之電性連接之接觸孔20，填埋鎢等之插塞，形成源極基板共通電位配線21及閘極電位配線22。
以上，由於可利用側間隔物自行整合地分離形成本發明之特徵的填埋至溝槽道之閘極電極上之矽化物，和源極高濃度擴散層上及基板電位高濃度擴散層上之矽化物，故即使為了縮小面積而縮小閘極電極之尺寸，亦可以實現相當低的接觸阻抗。
1、22‧‧‧第2導電型填埋層
2、23‧‧‧第1導電型井擴散層
3‧‧‧膜厚氧化膜
4‧‧‧硬遮罩
5、27‧‧‧溝槽道
6、28‧‧‧犧牲氧化膜
7、29‧‧‧閘極絕緣膜
8、13、14、26、33、34‧‧‧抗蝕膜
9、31‧‧‧閘極電極
10、12、25‧‧‧堆積氧化膜
11‧‧‧側間隔物
15、35‧‧‧第2導電型源極高濃度擴散層
16、36‧‧‧第1導電型基板電位高濃度擴散層
17‧‧‧金屬膜
18‧‧‧矽化物
19、37‧‧‧層間絕緣膜
20、38‧‧‧接觸孔
21、39‧‧‧源極基板共通電位配線
22、40‧‧‧閘極電位配線
24‧‧‧熱氧化膜
30‧‧‧摻雜多晶矽膜
第1圖為本發明之半導體裝置之製造方法之實施例的模式性剖面圖。
第2圖為接續第1圖，表示本發明之半導體裝置之製造方法之實施例的模式性剖面圖。
第3圖為本發明之半導體裝置之實施例之模式性俯視圖。
第4圖為以往之半導體裝置之製造方法的模式性剖面圖。
1、22‧‧‧第2導電型填埋層
2‧‧‧第1導電型井擴散層
5‧‧‧溝槽道
7‧‧‧閘極絕緣膜
9‧‧‧閘極電極
11‧‧‧側間隔物
12‧‧‧堆積氧化膜
13、14‧‧‧抗蝕膜
15‧‧‧第2導電型源極高濃度擴散層
16‧‧‧第1導電型基板電位高濃度擴散層
17‧‧‧金屬膜
18‧‧‧矽化物
19‧‧‧層間絕緣膜
20‧‧‧接觸孔
21‧‧‧源極基板共通電位配線

Claims (3)

  1. 一種半導體裝置，屬於具有被設置在半導體基板之溝槽構造之縱型MOS電晶體的半導體裝置，其特徵為：在溝槽內填埋閘極電極，在包圍上述溝槽之上述半導體基板表面設置源極電極，上述源極電極在與上述閘極電極之鄰接部具有朝上方隆起之隆起部；上述閘極電極具有較上述源極電極之隆起部更朝上方突出的突出部，在上述閘極電極之突出部設置側間隔物，在上述源極電極及上述閘極電極之上面具有矽化物層。
  2. 一種半導體裝置，其特徵為具有：第1導電型半導體基板；夾著第2導電型填埋層而被設置在上述第1導電型半導體基板上的第1導電型磊晶成長層；被形成在上述第2導電型填埋層之上的上述第1導電型磊晶成長層之一部分上的第1導電型井擴散層；被配置成格子狀或帶狀的溝槽道，其係以從上述第1導電型井擴散層的表面到達至上述第2導電型填埋層之深度所形成；被形成在上述溝槽道之表面的閘極絕緣膜，和隔著上述閘極絕緣膜而填充上述溝槽道，突出較上述第1導電型 井擴散層之表面高的閘極電極；被形成在上述閘極電極之側面的側間隔物；被形成在第1導電型井擴散層之非上述溝槽道的島狀區域之表面上的第2導電型源極高濃度擴散層及第1導電型基板電位擴散層；被形成在上述閘極電極表面的第1矽化物層；及被形成在上述第2導電型源極高濃度擴散層及上述第1導電型基板電位擴散層之表面的第2矽化物層，在上述島狀區域之表面形成碟形狀之底部及周圍隆起區域，上述側間隔物被配置在上述隆起區域上，上述第2導電型源極高濃度擴散層被形成在上述隆起區域，上述第1矽化物層和上述第2矽化物層係藉由上述側間隔物而分離。
  3. 一種半導體裝置之製造方法，屬於具有溝槽構造之縱型MOS電晶體的半導體裝置之製造方法，其特徵為包含：在成為填埋半導體基板上之閘極電極之溝槽之部分的周邊，從成為上述溝槽之部分間隔開特定量而藉由STI(Shallow Trench Isolation：淺溝槽隔離)設置填埋氧化膜之工程；在成為上述溝槽之部分設置溝槽之工程；在上述溝槽內設置閘極氧化膜之後，疊層多晶矽，填埋上述溝槽，並且疊層較上述半導體基板高之工程；除去上述溝槽內及上述溝槽上方以外之上述多晶矽， 形成較上述半導體基板突出之閘極電極之工程；上述藉由STI除去填埋氧化膜之工程；堆積氧化膜之後，進行回蝕，且在上述閘極電極之周圍形成側間隔物之工程；在包圍上述閘極電極之上述半導體基板上離子注入，且形成源極區域之工程；使附著矽化用金屬膜之工程；及除了熱處理之外，在上述閘極電極上及上述源極區域上形成矽化層之工程。
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US20130168763A1 (en) 2013-07-04
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