JP5881100B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims description 32
- 229910021332 silicide Inorganic materials 0.000 claims description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 68
- 238000009792 diffusion process Methods 0.000 description 50
- 239000012535 impurity Substances 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004570 mortar (masonry) Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Description
従来のトレンチ構造を備えた縦型MOSトランジスタの製造方法について、図4を基に説明する。図4は製造方法を示す模式的断面図による工程順フローである。
これにより、第1導電型ウェル拡散層23に形成されたトレンチ溝27を備えた、縦方向に動作するトレンチ構造を備えた縦型MOSトランジスタの素子構造が整う。
まず、第1導電型半導体基板と、第1導電型半導体基板上に第2導電型埋め込み層を挟んで設けられた第1導電型エピタキシャル成長層と、第2導電型埋め込み層の上の第1導電型エピタキシャル成長層の一部に形成された第1導電型ウェル拡散層と、第1導電型ウェル拡散層から第2導電型埋め込み層に達する深さで形成された格子状あるいはストライプ状の互いに連結したトレンチ溝と、トレンチ溝の表面に形成されたゲート絶縁膜とゲート絶縁膜を介してトレンチ溝を充填し、第1導電型ウェル拡散層表面より高く突出したゲート電極である多結晶シリコン膜と、ゲート電極の側面に形成されたサイドスペーサーと、第1導電型ウェル拡散層のトレンチ溝でない島状領域の表面の上部に形成された第2導電型ソース高濃度拡散層および第1導電型基板電位拡散層と、ゲート電極表面に形成されたシリサイド層と、第2導電型ソース高濃度拡散層および第1導電型基板電位拡散層の表面に形成されたシリサイド層とを有し、ゲート電極表面に形成されたシリサイド層と第2導電型ソース高濃度拡散層および第1導電型基板電位拡散層の表面に形成されたシリサイド層はサイドスペーサーによって分離されていることを特徴とする半導体装置とした。
そして、上記記載の半導体装置の製造方法として、トレンチ溝でない島状領域の表面の皿型形状をSTI(Shallow Trench Isolation)による埋め込み酸化膜である厚膜酸化膜をエッチング除去することにより形成する半導体装置の製造方法とした。
引き続き、図1(B)に示すように、ハードマスク4を除去した後、トレンチ溝5の形状改善のため犠牲酸化膜6を例えば膜厚は数nmから数十nmの熱酸化にて形成する。
2、23 第1導電型ウェル拡散層
3 厚膜酸化膜
4 ハードマスク
5、27 トレンチ溝
6、28 犠牲酸化膜
7、29 ゲート絶縁膜
8、13、14、26、33、34 レジスト膜
9、31 ゲート電極
10、12、25 堆積酸化膜
11 サイドスペーサー
15、35 第2導電型ソース高濃度拡散層
16、36 第1導電型基板電位高濃度拡散層
17 金属膜
18 シリサイド
19、37 層間絶縁膜
20、38 コンタクト孔
21、39 ソース基板共通電位配線
22、40 ゲート電位配線
24 熱酸化膜
30 ドープト多結晶シリコン膜
Claims (1)
- トレンチ構造の縦型MOSトランジスタを有する半導体装置の製造方法において、
半導体基板上のゲート電極を埋め込むトレンチとなる部分の周辺に前記トレンチとなる部分から所定量離間してSTI(Shallow Trench Isolation)による埋め込み酸化膜を設ける工程、
前記トレンチとなる部分にトレンチを設ける工程、
前記トレンチ内にゲート酸化膜を設けた後、多結晶シリコンを積層し、前記トレンチを埋め込み、さらに前記半導体基板よりも高く積層する工程、
前記トレンチ内および前記トレンチ上方以外の前記多結晶シリコンを除去し、前記半導体基板より突出したゲート電極を形成する工程、
前記STIによる埋め込み酸化膜を除去する工程、
酸化膜を堆積した後、エッチバックをし、前記ゲート電極の周囲にサイドスペーサーを形成する工程、
前記ゲート電極を囲む前記半導体基板上にイオン注入し、ソース領域を形成する工程、
シリサイデーション用金属膜を付着する工程、
熱処理を加え、前記ゲート電極上および、前記ソース領域上にシリサイド層を形成する工程、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011281632A JP5881100B2 (ja) | 2011-12-22 | 2011-12-22 | 半導体装置の製造方法 |
TW101147456A TWI545766B (zh) | 2011-12-22 | 2012-12-14 | Semiconductor device and manufacturing method thereof |
US13/719,323 US8847308B2 (en) | 2011-12-22 | 2012-12-19 | Semiconductor device having a trench structure |
KR1020120149467A KR101960547B1 (ko) | 2011-12-22 | 2012-12-20 | 반도체 장치 및 그 제조 방법 |
CN201210560994.3A CN103178115B (zh) | 2011-12-22 | 2012-12-21 | 半导体装置及其制造方法 |
Applications Claiming Priority (1)
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JP6740982B2 (ja) * | 2017-08-21 | 2020-08-19 | 株式会社デンソー | 半導体装置 |
JP6740983B2 (ja) * | 2017-08-21 | 2020-08-19 | 株式会社デンソー | 半導体装置 |
WO2019039304A1 (ja) * | 2017-08-21 | 2019-02-28 | 株式会社デンソー | 半導体装置およびその製造方法 |
US11469319B2 (en) * | 2020-04-10 | 2022-10-11 | Nanya Technology Corporation | Semiconductor device with recessed access transistor and method of manufacturing the same |
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JPH03241865A (ja) * | 1990-02-20 | 1991-10-29 | Texas Instr Japan Ltd | 半導体装置 |
JPH08255901A (ja) | 1995-03-16 | 1996-10-01 | Nissan Motor Co Ltd | 縦型mosfetの製造方法 |
JP2003101027A (ja) | 2001-09-27 | 2003-04-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US7205630B2 (en) * | 2004-07-12 | 2007-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for a semiconductor device having low and high voltage transistors |
US8338887B2 (en) * | 2005-07-06 | 2012-12-25 | Infineon Technologies Ag | Buried gate transistor |
JP5222466B2 (ja) * | 2006-08-09 | 2013-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5165954B2 (ja) * | 2007-07-27 | 2013-03-21 | セイコーインスツル株式会社 | 半導体装置 |
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CN103178115B (zh) | 2017-10-03 |
US8847308B2 (en) | 2014-09-30 |
KR20130079180A (ko) | 2013-07-10 |
CN103178115A (zh) | 2013-06-26 |
TW201342609A (zh) | 2013-10-16 |
US20130168763A1 (en) | 2013-07-04 |
TWI545766B (zh) | 2016-08-11 |
KR101960547B1 (ko) | 2019-03-20 |
JP2013131695A (ja) | 2013-07-04 |
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