TW201347047A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TW201347047A
TW201347047A TW102107490A TW102107490A TW201347047A TW 201347047 A TW201347047 A TW 201347047A TW 102107490 A TW102107490 A TW 102107490A TW 102107490 A TW102107490 A TW 102107490A TW 201347047 A TW201347047 A TW 201347047A
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Naoto Saitoh
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Abstract

本發明的課題是在於提供一種溝槽MOSFET的製造方法，其係使用簡單且控制性佳的工程，可與CMOS電晶體形成於同一基板上，可縮小元件面積。其解決手段是溝槽MOSFET的製造方法，其係具有：藉由形成3次元的軀體接觸區域，即使為更小的面積，還是可確保和以往同樣的接觸之構造。

Description

半導體裝置之製造方法
本發明是有關半導體裝置及半導體裝置的製造方法，例如有關與CMOS形成於同一基板上的溝槽MOSFET的構造及製造方法。
MOS電晶體是在電子技術中擔負核心的電子元件，MOS電晶體的小型化及高驅動能力化是不論低耐壓區域及高耐壓區域皆成重要的課題。
將載體移動的方向設定成對半導體基板表面呈上下(鉛直方向)的縱型構造的溝槽MOSFET是可構成小面積持大的通道寬度之電晶體，因此大多用在需要高驅動能力的用途。至今廣泛作為離散的驅動器元件使用，但近年來提案使此高驅動能力的溝槽MOSFET與構成控制電路的通常的CMOS電晶體一體化的製程。
溝槽MOSFET的表面形狀由上來看時是分成溝槽區域及非溝槽區域。而且非溝槽區域是分成高濃度雜質區域的源極區域，及用以固定軀體區域的電位之高濃度雜質區域的軀體接觸區域。
而且非溝槽區域的源極區域及軀體接觸區域通常是以同電位使用，因此兩雜質區域是鄰接，大多的情況是以同金屬配線來同時連接。在矽化物形成製程時，兩區域是以連續的矽化物所覆蓋，經由最小限度的接觸面積．數量來連接至配線金屬。
為了使每單位面積的驅動能力提升，被要求削減上述溝槽區域或非溝槽區域的面積。非溝槽區域之一的軀體接觸區域是只要連電位都可固定即可，該點是面積縮小較為有效，但若電位不安定，則電晶體會急變返回，妨礙在所望的動作電壓的正常動作。
並且，軀體接觸區域會受到構成源極區域的雜質濃度的偏差及擴散的偏差影響，因此必須具有持更餘裕的面積來配置。因此無法容易縮小面積。
以往是以能夠一面固定電位一面極力縮小面積的方式控制雜質濃度及熱處理，而來構成源極區域及軀體接觸區域。或，如下記的專利文獻1那樣，設置配置軀體接觸區域之處及不配置之處，全體欲縮小面積者也被提案。
專利文獻1的技術是如圖5所示般，將溝槽區域51及非溝槽區域53配置成條紋狀，且將非溝槽區域53的寬度分成2種類，在寬度寬處配置軀體接觸區域52，在寬度窄處不予以配置。藉由以鄰接的條紋來彼此不同地排列此配置，使面積效率最適化，以最小限度的面積來構成電晶體，降低每單位面積的電晶體的ON電阻。
[先行技術文獻] [專利文獻]
[專利文獻1]特開2002-50760號公報
然而，即使根據專利文獻1的技術，還是必須將軀體接觸區域配置一定的面積以上，此區域依然對於電晶體面積的縮小化有限。並且，將溝槽區域配置成格子狀時，處處配置被限定成條紋狀的佈局之軀體接觸區域的措施在取得電晶體特性的均一性上未必是好方法。
於是，本發明的目的是在於實現一種可使用工程不增加且控制性佳的工程來取得均一的元件面積小的溝槽MOSFET之製造方法。
本發明為了達成前述目的，請求項1記載的發明為一種半導體裝置的製造方法，其特徵係由下列工程所構成：在第1導電型的半導體基板形成第2導電型的埋入層之工程；在前述埋入層上形成第2導電型的磊晶層之工程；從前述第2導電型的磊晶層的表面到一定的深度，形成第1導電型的軀體區域之工程；除去構成前述軀體區域的表面的半導體材料，而在凸 型接觸區域的周圍形成淺溝槽之工程；從前述淺溝槽的表面的一部分到前述第2導電型的磊晶層內，形成深的溝槽區域之工程；在前述深的溝槽區域的內壁形成閘極絕緣膜之工程；將接於前述閘極絕緣膜之前述深的溝槽區域內予以藉由多結晶矽來充填之工程；在前述軀體區域表面的前述淺溝槽內形成第2導電型的源極區域之工程；在前述軀體區域表面的前述凸型接觸區域形成第1導電型的軀體接觸區域之工程；形成連接前述源極區域及前述軀體接觸區域的矽化物層之工程，又，前述凸型接觸區域的表面全部為前述軀體接觸區域，與前述源極區域的表面一同以前述矽化物層所覆蓋。
請求項2記載的發明為一種半導體裝置的製造方法，其特徵係由下列工程所構成：在第1導電型的半導體基板形成第2導電型的埋入層之工程；在前述埋入層上形成第2導電型的磊晶層之工程；在前述磊晶層的表面的特定的區域形成作為凹型接觸區域用的淺溝槽之工程；以來自前述磊晶層的表面的距離成為一定的方式，在無前述凹型接觸區域的平坦的區域之下為淺，在前述凹型接觸區域之下為深，形成朝前述埋入層突出的第1導電型 的軀體區域之工程；將從前述軀體區域的表面到前述磊晶層內的深的溝槽形成前述平坦的區域之工程；在前述深的溝槽區域的內壁形成閘極絕緣膜之工程；將接於前述閘極絕緣膜之前述深的溝槽區域內予以藉由多結晶矽來充填之工程；在前述軀體區域表面的前述平坦的區域形成第2導電型的源極區域之工程；沿著前述軀體區域表面的前述凹型接觸區域來形成第1導電型的軀體接觸區域之工程；及形成連接前述源極區域與前述軀體接觸區域的矽化物層之工程；又，前述凹型接觸區域的表面全部為前述軀體接觸區域，與前述源極區域的表面一同以前述矽化物層所覆蓋。
若根據本發明，則可將元件特性拉到最大限度，可製造微細尺寸也可對應的半導體裝置，其結果也可降低成本。
1‧‧‧P型半導體基板
2‧‧‧N型型埋入層
3‧‧‧N-epi層
4‧‧‧P型軀體區域
5‧‧‧凸型接觸
6‧‧‧深的溝槽
7‧‧‧閘極氧化膜
8‧‧‧閘極電極
9‧‧‧N型源極區域
10、30‧‧‧P型軀體接觸區域
11‧‧‧矽化物層
12‧‧‧淺溝槽
15‧‧‧凹型接觸
16‧‧‧平坦的區域
圖1是用以說明本發明的第一實施形態的半導體裝置的製造方法之工程順序剖面圖。
圖2是用以說明本發明的第一實施形態的半導體裝置 的製造方法之接續於圖1的工程順序剖面圖。
圖3是用以說明本發明的第二實施形態的半導體裝置的製造方法之工程順序剖面圖。
圖4是用以說明本發明的第二實施形態的半導體裝置的製造方法之接續於圖3的工程順序剖面圖。
圖5是用以說明以往的半導體裝置的圖。
圖1是用以說明本實施形態的半導體裝置的製造方法的圖，本發明的溝槽MOSFET的工程順序剖面圖。
如圖1(a)所示般，在形成於P型半導體基板1上的N型型埋入層2上設置有磊晶層3(在此是稱為N-epi層3)，全體被摻雜N型雜質。N型埋入層2是具有5×1017/cm3~5×1019/cm3的濃度，成為溝槽MOSFET的汲極區域。藉由摻雜Sb(銻)、As(砷)、或P(磷)來形成。並且，N-epi層3是成為低濃度的汲極區域或飄移區域，藉由將磷摻雜到1×1015/cm3~5×1017/cm3的濃度來實現。N型埋入層2的厚度是約2~10μm厚，N-epi層3是2~10μm。
其次，如圖1(b)所示般，在N-epi層3內利用元件分離用的STI(Shallow Trench Isolation)或LOCOS(Local Oxidation of Silicon)(未圖示)，留下一部分來除去表面的半導體材料，形成凸型接觸區域5。因此，凸型接觸區域5的周圍是成為淺溝槽12，其表面變低。 使用STI作為元件分離時，在凸型接觸區域5以外的場所進行STI形成用的矽蝕刻，藉此可形成圖1(b)那樣的形狀。有關CMOS形成區域，在STI埋入絕緣膜的工程等是在此進行。另一方面，使用LOCOS作為元件分離時，在凸型接觸區域5以外形成50nm~150nm的LOCOS氧化膜，除去LOCOS氧化膜，藉此形成圖1(b)所示的凸型接觸5。
其次，藉由離子注入來形成P型的軀體區域4。P型的軀體區域4是將B(硼)或BF2(二氟化硼)注入成5×1016/cm3~1×1018/cm3的濃度。此時的注入的加速能量是依溝槽MOSFET所必要的耐壓而改變，較理想是50~250keV的範圍內。另外，P型的軀體區域4的形成工程是亦可在形成凸型接觸區域5之前。
其次，如圖1(c)所示般，藉由蝕刻在淺溝槽內形成深的溝槽6。深的溝槽6的深度是1~3μm程度，依電晶體所要求之所望的汲極耐壓來適當設定。
其次，在圖2(a)中，在深的溝槽6的內壁藉由熱氧化來形成閘極氧化膜7，在溝槽6內隔著閘極氧化膜7來充填成為閘極電極8的多結晶矽。閘極電極8是藉由沿著深的溝槽6的側壁及底面延伸的閘極氧化膜7來與N-epi層3及P型的軀體區域4電性隔離。閘極氧化膜7的厚度是考慮所望的電晶體的閘極破壞耐壓來設定，大約是7nm~20nm。並且，閘極氧化膜7的形成溫度是成為800℃~1150℃，較理想是1000℃~1150℃的範圍。
其次，在圖2(b)中，於P型的軀體區域4的上側表面區域，進行用以形成N型的高濃度雜質區域的源極區域9之離子注入。為了形成N型的源極區域9，為了降低片電阻(sheet resistance)較理想是以5×1014~1×1016atoms/cm2的劑量來離子注入例如As。當然，亦可高濃度注入P(磷)，或導入As及P的雙方。並且，進行用以在包含凸型接觸區域5的區域形成P型的軀體接觸區域10之離子注入。為了形成P型的軀體接觸區域10，為了降低片電阻，較理想是以5×1014~1×1016atoms/cm2的劑量來離子注入例如BF2。當然，亦可高濃度注入B(硼)，或導入BF2及B的雙方。
然後，如圖2(c)般，將矽化物層11形成於源極區域9及軀體接觸區域10上，使用插銷配線(未圖示)來連接至配線金屬層(未圖示)。
以上的說明是在使用N-epi層3時說明，但亦可使用P-epi層，與P型的軀體區域4同時離子注入N型的雜質，將N型型埋入層2與P型的軀體區域4之間設定為N型的汲極區域。並且，在此是以N型的電晶體為前提進行說明，但在將埋入層、epi層設為P型，將軀體區域設為N型之P型的電晶體時也同樣地適用。(當然亦可將epi層設為N型，藉由雜質導入來將P型埋入層與軀體區域之間設定為P型的汲極區域)。
並且，有關與溝槽MOSFET形成於同一基板上的CMOS方面雖未詳細說明，但實際上述所揭示的工程是在 CMOS形成時，不存在任何成為障礙的工程，容易在同一基板上形成溝槽MOSFET及CMOS。
圖3是用以說明本實施形態的第2半導體裝置的製造方法的圖。
在圖3(a)中，在形成於P型半導體基板1上的N型型埋入層2上設置有epi層3(在此是稱為N-epi層3)，全體被摻雜N型雜質。N型埋入層2是藉由摻雜Sb(銻)或As(砷)或P(磷)來形成，具有5×1017/cm3~5×1019/cm3的濃度，且N-epi層3是藉由摻雜磷來實現，具有1×1015/cm3~5×1017/cm3的濃度。N型埋入層2的厚度是約2~10μm厚，N-epi層3的厚度是2~10μm。
其次，在N-epi層3內，為了配置作為元件分離的STI而蝕刻矽，形成淺溝槽，將絕緣膜埋入淺溝槽內，但在位於溝槽MOSFET的形成預定區域的淺溝槽內所被埋入的絕緣膜是除去。(此絕緣膜的除去是亦可在之後的P型的軀體區域離子注入用的阻劑圖案形成後進行)。藉此，形成利用淺溝槽的凹型接觸區域15。另外，淺溝槽的深度是依所被要求的動作電壓來適當設定，大約是200nm~600nm。
元件分離亦可不是STI而是利用LOCOS來製作上述凹型接觸區域15那樣的形狀。此時，只在凹型接觸區域15部分形成50nm~150nm的LOCOS氧化膜，之後藉由蝕刻來除去LOCOS氧化膜，藉此可形成相似於STI的形狀的凹型接觸區域15。
其次，在圖3(b)中，藉由離子注入來形成P型的軀體區域4。P型的軀體區域4是將B(硼)或BF2(二氟化硼)注入成5×1016/cm3~1×1018/cm3的濃度。此時，在形成有利用淺溝槽的凹型接觸區域15的區域及未形成有凹型接觸區域15的平坦的區域16中，雜質可自表面到達的距離皆相同，因此形成軀體區域4的雜質是反映N-epi層3的表面的形狀來分布，在凹型接觸區域15正下方是可使P型的軀體區域4的底形成深，在其他的區域是可使P型的軀體區域4的底形成淺。
其次，如圖3(c)所示般，從軀體區域4的表面到N-epi層3來形成深的溝槽6。深的溝槽6的深度是1~3um程度，依所望的電晶體要求的汲極耐壓來適當設定。另外，在此重要的是深的溝槽6被設定在P型的軀體區域4的底變淺的區域。
其次，如圖4(a)所示般，在深的溝槽26的內壁藉由熱氧化來形成閘極氧化膜7，在溝槽6內隔著閘極氧化膜7來充填成為閘極電極8的多結晶矽。閘極電極8是藉由沿著深的溝槽6的側壁及底面延伸的閘極氧化膜7來與N-epi層3及P型的軀體區域4電性隔離。閘極氧化膜7的厚度是考慮所望的電晶體的閘極破壞耐壓來設定，大約7nm~20nm。並且，閘極氧化膜7的形成溫度是800℃~1150℃，較理想是1000℃~1150℃的範圍。
其次，如圖4(b)所示般，在包含與P型的軀體區域4的上側表面及深的溝槽6的側壁鄰接的凹型接觸區域 15之區域形成P型軀體接觸區域30。而且，以和深的溝槽6鄰接且與P型軀體接觸區域30也鄰接的方式形成N型源極區域9。
然後，如圖4(c)般，將矽化物層11形成於N型的高濃度雜質區域的源極區域9及P型的軀體接觸區域30上，使用插銷配線(未圖示)來連接至配線金屬層(未圖示)。
以上的說明是在使用N-epi層3時說明，但亦可使用P-epi層，與P型的軀體區域4同時離子注入N型的雜質，將N型型埋入層2與P型的軀體區域4之間設定為N型的汲極區域。並且，在此是以N型的電晶體為前提進行說明，但在將埋入層、epi層設為P型，將軀體區域設為N型之P型的電晶體時也同樣地適用。(當然亦可將epi層設為N型，藉由雜質導入來將P型埋入層與軀體區域之間設定為P型的汲極區域)。
並且，有關與溝槽MOSFET形成於同一基板上的CMOS方面雖一切未觸及，但實際上述所揭示的工程是在CMOS形成時，不存在任何成為障礙的工程，容易在同一基板上形成溝槽MOSFET及CMOS。
藉由至此說明的本實施形態，可取得其次那樣的效果。
(1)可大取用以取得軀體的電位的矽高濃度區域與矽化物層的接觸面積，若接觸面積為相同，則可縮小實質的軀體接觸區域的面積之平面的軀體接觸區域的大小，因 此可以同一面積形成ON電阻低的溝槽MOSFET。
(2)藉由利用STI或Locos製程那樣安定的工程，可一面將偏差抑制在最小限度，一面製造持高度的特性之裝置。
[產業上的利用可能性]
可利用在被要求比較高耐壓．高驅動能力之汽車用半導體裝置或TV，DVD，白色家電等家庭用電器製品中有效的半導體裝置。
1‧‧‧P型半導體基板
3‧‧‧N-epi層
4‧‧‧P型軀體區域
6‧‧‧深的溝槽
7‧‧‧閘極氧化膜
8‧‧‧閘極電極
9‧‧‧N型源極區域
10‧‧‧P型軀體接觸區域

Claims (8)

  1. 一種半導體裝置的製造方法，其特徵係由下列工程所構成：在第1導電型的半導體基板形成第2導電型的埋入層之工程；在前述埋入層上形成第2導電型的磊晶層之工程；從前述第2導電型的磊晶層的表面到一定的深度，形成第1導電型的軀體區域之工程；除去構成前述軀體區域的表面的半導體材料，而在凸型接觸區域的周圍形成淺溝槽之工程；從前述淺溝槽的表面的一部分到前述第2導電型的磊晶層內，形成深的溝槽區域之工程；在前述深的溝槽區域的內壁形成閘極絕緣膜之工程；將接於前述閘極絕緣膜之前述深的溝槽區域內予以藉由多結晶矽來充填之工程；在前述軀體區域表面的前述淺溝槽內形成第2導電型的源極區域之工程；在前述軀體區域表面的前述凸型接觸區域形成第1導電型的軀體接觸區域之工程；形成連接前述源極區域及前述軀體接觸區域的矽化物層之工程，又，前述凸型接觸區域的表面全部為前述軀體接觸區域，與前述源極區域的表面一同以前述矽化物層所覆蓋。
  2. 如申請專利範圍第1項之半導體裝置的製造方 法，其中，前述淺溝槽的深度為200nm~600nm的範圍內。
  3. 如申請專利範圍第1項之半導體裝置的製造方法，其中，形成前述淺溝槽的工程係由形成LOCOS氧化膜的工程及除去該LOCOS氧化膜的工程所構成。
  4. 如申請專利範圍第3項之半導體裝置的製造方法，其中，前述LOCOS氧化膜的膜厚為50nm~150nm的範圍內。
  5. 一種半導體裝置的製造方法，其特徵係由下列工程所構成：在第1導電型的半導體基板形成第2導電型的埋入層之工程；在前述埋入層上形成第2導電型的磊晶層之工程；在前述磊晶層的表面的特定的區域形成作為凹型接觸區域用的淺溝槽之工程；以來自前述磊晶層的表面的距離成為一定的方式，在無前述凹型接觸區域的平坦的區域之下為淺，在前述凹型接觸區域之下為深，形成朝前述埋入層突出的第1導電型的軀體區域之工程；將從前述軀體區域的表面到前述磊晶層內的深的溝槽形成前述平坦的區域之工程；在前述深的溝槽區域的內壁形成閘極絕緣膜之工程；將接於前述閘極絕緣膜之前述深的溝槽區域內予以藉由多結晶矽來充填之工程； 在前述軀體區域表面的前述平坦的區域形成第2導電型的源極區域之工程；沿著前述軀體區域表面的前述凹型接觸區域來形成第1導電型的軀體接觸區域之工程；及形成連接前述源極區域與前述軀體接觸區域的矽化物層之工程；又，前述凹型接觸區域的表面全部為前述軀體接觸區域，與前述源極區域的表面一同以前述矽化物層所覆蓋。
  6. 如申請專利範圍第5項之半導體裝置的製造方法，其中，前述淺溝槽的深度為200nm~600nm的範圍內。
  7. 如申請專利範圍第5項之半導體裝置的製造方法，其中，形成前述淺溝槽的工程係由形成LOCOS氧化膜的工程及除去該LOCOS氧化膜的工程所構成。
  8. 如申請專利範圍第7項之半導體裝置的製造方法，其中，前述LOCOS氧化膜的膜厚為50nm~150nm的範圍內。
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