CN100552975C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN100552975C
CN100552975C CNB2007101496432A CN200710149643A CN100552975C CN 100552975 C CN100552975 C CN 100552975C CN B2007101496432 A CNB2007101496432 A CN B2007101496432A CN 200710149643 A CN200710149643 A CN 200710149643A CN 100552975 C CN100552975 C CN 100552975C
Authority
CN
China
Prior art keywords
drain electrode
layer
electrode layer
high concentration
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2007101496432A
Other languages
English (en)
Other versions
CN101145580A (zh
Inventor
八柳俊佑
上原正文
安齐胜义
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
System Solutions Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101145580A publication Critical patent/CN101145580A/zh
Application granted granted Critical
Publication of CN100552975C publication Critical patent/CN100552975C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体装置及其制造方法，其目的在于提供ESD耐量被提高的晶体管构造。在中浓度的漏极层(10)的表面上从栅极电极(7)的漏极侧的端部离间形成高浓度的漏极层(12)，而且在栅极电极(7)和高浓度的漏极层(12)之间的衬底表面上包围高浓度漏极层(12)形成P型杂质层(13)，通过异常电涌开启寄生双极晶体管(30)期间，电子从源极电极(15)向漏极电极(16)移动，在此，电子避开形成P型杂质层(13)的衬底表面附近(X)，如图4箭头(25)所示，从更深的位置向漏极电极(16)侧以蔓延方式分散移动。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别涉及高耐压MOS晶体管。
背景技术
高耐压MOS晶体管具有高的源极漏极耐压(BVDS)、或者高的栅极耐压，广泛用于LCD驱动器、EL驱动器等各种驱动器或电源电路等。
图6是表示有关现有例的N沟道型的高耐压MOS晶体管的结构的剖面图。在P型半导体衬底100的表面上形成有栅极绝缘膜101、厚的场绝缘膜102。在邻接的场绝缘膜102的一部分上自栅极绝缘膜101起形成栅极电极103。在半导体衬底100的表面区域形成有与栅极电极103的一侧端邻接的高浓度(N++型)的源极层104及低浓度的源极层105。
另外，在从栅极电极103的另一侧端离开的半导体衬底100的表面上形成高浓度(N++型)的漏极层106。并且，在从栅极电极103的下方至场绝缘膜102及高浓度的漏极层106的下方区域，形成比高浓度的漏极层106浓度更低、扩散到更深的低浓度(N-型)的漏极层107。高浓度的漏极层106在低浓度的漏极层107内形成。这样，源极区域及漏极区域成为由高浓度部分和低浓度部分构成的所谓LDD(Lightly Doped Drain)结构。另外，在栅极电极103的侧壁上形成氮化硅膜等侧壁隔膜108。
上述的现有高耐压MOS晶体管在对高浓度的漏极层106施加高电压时，通过在低浓度的漏极层107中扩展耗尽层，漏电场被缓和，因此能够得到高的源极·漏极耐压。另外，由于栅极电极103从栅极绝缘膜101延展到邻接的场绝缘膜102的一部份上，因此栅极绝缘膜101破坏也具有较强的结构。
另外，与本发明相关的技术记载在以下的特许文献中。
特许文献1：特开2002-134738号公报
发明内容
但是，在上述的现有晶体管结构中存在静电破坏耐量(以下称为ESD耐量)不够充分的问题。例如，根据本发明者进行的基于人体模型(HBM)的通常的静电破坏试验为不满200伏特(V)的ESD耐量，基于机器模型(MM)的静电破坏试验为不满50伏特(V)的ESD耐量，这些都不够充分。因此，本发明的目的为提供一种提高ESD耐量的晶体管结构。
本发明的主要特征如下。即本发明的半导体装置，其特征在于：具有形成于第一导电型的半导体层表面的栅极绝缘膜、形成于所述栅极绝缘膜上的栅极电极、形成于所述半导体层表面的第二导电型的源极层、所述栅极电极的漏极侧的端部离间且形成于所述半导体层表面的第二导电型的高浓度的漏极层、在所述栅极电极和所述高浓度的漏极层之间的所述半导体层表面上邻接于所述高浓度的漏极层的第一导电型的杂质层。
另外，本发明的半导体装置的制造方法，其特征在于，具有以下工序：在第一导电型的半导体层的表面上形成栅极绝缘膜的工序；在所述栅极绝缘膜上形成栅极电极的工序；在从所述栅极电极离间的所述半导体层的表面上形成第二导电型的高浓度的漏极层的工序；使第一导电型的杂质层与所述高浓度的漏极层邻接、且在所述半导体层的表面上形成的工序。
在本发明中，在栅极电极和高浓度的漏极层之间的半导体层的表面上，形成有与高浓度的漏极层邻接的、和该漏极层逆导电型的杂质层。通过如这样构成，发生异常电涌时的电子避开形成有所述杂质层的附近而移动，从更深位置向漏极电极蔓延。即半导体层的表面附近的电子的移动被抑制。因此能提高ESD耐量。
附图说明
图1是说明本发明实施方式的半导体装置及其制造方法的剖面图；
图2是说明本发明实施方式的半导体装置及其制造方法的剖面图；
图3(a)、(b)是说明本发明实施方式的半导体装置及其制造方法的剖面图及平面图；
图4是说明本发明实施方式的半导体装置及其制造方法的剖面图；
图5(a)、(b)是说明本发明实施方式的半导体装置的变更例的剖面图；
图6是说明现有的半导体装置的剖面图。
符号的说明：
1、半导体衬底；2、阱层；3、阱层；4a、4b、低浓度的漏极层；5a、5b、5c、场绝缘膜；6、栅极绝缘膜；7、栅极电极；8、低浓度源极层；9a、9b，侧壁隔膜；10、中浓度的漏极层；11、高浓度的源极层；12、高浓度的漏极层；13、P型杂质层；14、层间绝缘膜；15源极电极；16、漏极电极；20、半导体装置；25、电子流；30、寄生双极晶体管；100、半导体衬底；101、栅极绝缘膜；102、场绝缘膜；103、栅极电极；104、源极层；105、低浓度的源极层；106、高浓度的漏极层；107、低浓度的漏极层；108、侧壁隔膜。
具体实施方式
下面，参照附图说明关于本发明实施方式的半导体装置。图1至图4是按制造工序顺序表示本发明实施方式的半导体装置的剖面图。
首先，如图1所示，在P型半导体衬底1的表面上注入N型杂质，且进行热扩散，由此形成N型的阱层2(NW)。该离子注入，例如使磷离子(31P+)在加速电压为80KeV、注入量为1.0×1013/cm2的条件下进行。另外，本发明中也可以省略所述N型的阱层2(NW)的形成。
其次，在阱层2的表面注入P型杂质，通过热扩散形成P型阱层3(PW)。当该离子注入，例如，使硼离子(11B+)在加速电压为80KeV、注入量为2.3×1013/cm2的条件下进行。
下面，通过在阱层3的表面选择性地注入N型杂质形成低浓度(N-型)的漏极层4a、4b。低浓度的漏极层4a、4b之间离开。即在漏极层4a、4b之间以不进行离子注入的方式使用规定的掩膜进行该离子注入。该离子注入，例如，使磷离子(31P+)在加速电压为100KeV、注入量为1.5×1013/cm2的条件下进行。
接着，如图2所示，使用LOCOS(Local Oxidation Of Silicon)法，在阱层3的规定区域上形成厚的场绝缘膜5a、5b、5c。其中场绝缘膜5a、5b分别形成在与低浓度的漏极层4a、4b重叠的区域。场绝缘膜通常形成为元件分离用，而该半导体装置中的场绝缘膜5a、5b用来提高晶体管的耐压。场绝缘膜5a、5b、5c的膜厚根据目标耐压而不同，例如，为300nm～600nm范围。另外，场绝缘膜的形成不限定于LOCOS法，例如，也可以使用包含STI(Shall owTrench Isolation)法的其他的元件分离法。
接着，例如，通过热氧化法形成栅极绝缘膜6。栅极绝缘膜6的膜厚根据目标耐压而不同，例如为15～200nm范围。另外，场绝缘膜5a、5b、5c为比栅极绝缘膜6更厚的绝缘膜。
接着，在半导体衬底1上的表面作为导电材料，通过例如CVD(ChemicalVapor Deposition)法形成多晶硅层。其后，通过选择性地去除该多晶硅层及栅极绝缘层6时，形成栅极电极7。栅极电极7以从栅极绝缘膜6邻接延展到场绝缘膜5a的一部分上的方式制作布线图案。由此提高耐压。其膜厚为例如300nm。另外，通过根据需要注入磷离子等杂质并使其扩散，使栅极电极7低电阻化。
接着，将栅极电极7作为掩膜的一部分，在栅极电极7左侧的阱层3的表面区域上注入N型杂质，形成低浓度的源极层8(LN)。该离子注入例如使磷离子(31p+)在加速电压为20KeV、注入量为4.2×1013/cm2的条件下进行。另外，低浓度的源极层8的形成也可以是在后送的侧壁隔膜9a、9b的形成之后。
接着，如图3(a)所示，在半导体衬底1上的整个面上，例如通过CVD法形成氧化硅膜或氮化硅膜，其次，通过将该氮化硅膜进行反复腐蚀，形成环绕栅极电极7的周围的侧壁隔膜9a、9b。另外，在该侧壁隔膜9a、9b由多晶硅等导电材料形成的情况下，栅极电极7和侧壁隔膜9a、9b的整体成为栅极它极。
接着，将没有图示的光致抗蚀剂层以及场绝缘膜5a、5b作为掩膜，在由场绝缘膜5a、5b包围的阱层3的表面区域注入N型杂质，形成比低浓度的漏极层4a、4b更高的杂质浓度，并且杂质被注入到深处的中浓度的漏极层10(N)。中浓度的漏极层10和低浓度的漏极层4a、4b邻接。该离子注入，例如，使磷离子(31P+)在加速电压为1000KeV、注入量为8.0×1013/cm2的条件下进行。另外，中浓度的漏极层10和低浓度的漏极层4a、4b分开也可以，一部分重叠也可以。
接着，将没有图示的光致抗蚀剂层及侧壁隔膜9a作为掩膜注入N型杂质，在和低浓度的源极层8重叠的区域形成高浓度的源极层11(N+)，同时，在和中浓度的漏极层10重叠的区域形成高浓度的漏极层12(N+)。该离子注入，例如使砷离子(75As+)在加速电压为100KeV、注入量为5.0×1013/cm2的条件下进行。高浓度的漏极层12不是在中浓度的漏极层10的表面的整个面上形成的层，而是如图3(a)、(b)所示和场绝缘膜5a、5b分离，在形成有后述的漏极电极16的区域近旁形成。另外，图3(b)是表示图3(a)的场绝缘膜5a、5b及高浓度的漏极层12的形成区域的部分平面图。
接着，将没有图示的光致抗蚀剂层作为掩膜，将P型杂质注入中浓度的漏极层10，形成高浓度的P型杂质层13。P型杂质层13为有助于提高ESD耐量的层。关于这一点在后面叙述。该离子注入，例如将二氟化硼(49BF2+)离子在加速电压为40KeV、注入量为2.0×1015/cm2的条件下进行。本实施方式的P型杂质层13，如图3(b)所示，以环状包围高浓度的漏极层12的周围，同时和高浓度的漏极层12邻接。另外，从提高ESD耐量的观点上考虑，优选P型杂质层13至少比高浓度的漏极层12更深地形成。另外，从提高ESD耐量的观点上考虑，如图3(a)、(b)所示，优选P型杂质层13和高浓度的漏极层12相接，但分离也可以。另外，在本实施方式中，P型杂质层13和场绝缘膜5a、5b邻接。接着进行退火处理。
另外，将用于高浓度的漏极层12的形成的离子注入注入中浓度的漏极层10的表面区域的整个面上，其后，在该区域使用于P型杂质层13的形成的离子注入一部分进行重叠，由此，形成高浓度的漏极层12和P型杂质层13也可以。
如图4所示，在半导体衬底1的整个面上形成层间绝缘膜14(例如，通过CVD法形成的BPSG膜及氮化硅膜)。接着，形成至高浓度的源极层11及高浓度的漏极层12的接触孔，在各接触孔上分别形成源极电极15和漏极电极16。
从以上制造工序能够得到有关本实施方式的半导体装置20。在以这种方式完成的半导体装置20的漏极电极16上生成过大的正的电涌电压时，如图4所示寄生NPN双极晶体管30开启，电流从漏极电极16侧向源极电极15侧流动。该寄生双向动作为以下现象，即，漏极层4a和阱层3的接合被击穿而电流在阱层3中流动时，阱层3的电压上升，而且基极电流从阱层3向源极层(8，11)侧流动，由此，寄生双极晶体管30开启。
在寄生双向动作进行期间，电子从源极电极15侧向漏极电极16侧移动。在此，考虑在不形成P型杂质层13的现有结构(参照图6)中，电子在衬底表面附近集中地流动、发热，由此达到破坏。与此相对，在本实施方式的结构中形成有P型杂质层13。因此，电子避开形成有P型杂质层13的衬底表面附近X，如图4箭头25所示，电子分散流动，从更深位置向漏极电极16侧以蔓延方式移动。即，考虑由于P型杂质层13的作用，电子(等于电流)在比衬底表面更深的位置分散流动，热不会集中，作为产生难以引起静电破坏的结果。
根据本发明者进行的静电破坏试验，可确认ESD耐量的提高。具体地说，在现有结构(参照图6)不满200伏特的人体模型的ESD耐量提高到3000～3500伏特程度，在现有结构不满50伏特的机器模型的ESD耐量提高到大约400伏特。而且，除了不形成P型杂质层13这一点以外，对和本实施方式具有同样结构的半导体装置进行了静电破坏试验，其情况为人体模型的ESD耐量为2000～2250伏特，机器模型的ESD耐量为200～220伏特。从这些试验可判定：本实施方式的结构与现有结构相比为ESD耐量飞跃式提高的结构、及P型杂质层13大大有助于ESD耐量的提高。
另外，本发明不限定于上述实施方式，在不偏移其主旨的范围内可进行设计变更。例如，在上述结构中，低浓度的漏极层4a、4b存在分离的部分，但也可以不分离而同样地形成低浓度的漏极区域。另外，通过在场绝缘膜5a的下部配置另外的P型杂质层而进一步提高ESD耐量也被考虑。另外，在本实施方式中，在栅极电极7的一部分下方形成有场绝缘膜5a，但是，如图5(a)所示，设计变更为不形成场绝缘膜5a的结构也可以。
进一步地，如图5(b)所示，以中浓度的漏极层10的源极侧的端部位于栅极电极7或者侧壁隔膜9b的下方的方式设计变更为不形成低浓度的漏极层4a的结构也可以。
另外，当然也可以变更制造工序的顺序及条件。例如，上述中是在形成侧壁隔膜9a、9b之后形成中浓度的漏极层10，但在此以前形成也可以。具体而言，也可以是：在场绝缘膜5a～5c形成后，使用所规定的掩膜进行用于形成中浓度的漏极层10的离子注入，其后使注入的离子进行热扩散，由此形成中浓度的漏极层10。而且，其后能够形成栅极绝缘膜6及栅极电极7。另外，从通过进行热扩散而使中浓度的漏极层10较深地形成的观点来看，有关该情况的形成中浓度的漏极层10的的离子注入，通过比较性地增多注入量，能够在非高加速的条件下进行。这时的注入条件，例如，在使用砷离子(75As+)的情况下，条件为：加速电压为90～150KeV，注入量为1.0×1015～6.0×1015cm2；另外，在使用磷离子(31P+)的情况下，条件为：加速电压为40～80KeV，注入量为1.0×1015～6.0×1015cm2。
另外，有关P沟道型的MOS晶体管的说明省略，众所周知其只是导电型不同而其余为相同结构。

Claims (9)

1、一种半导体装置，其特征在于：
具有形成于第一导电型的半导体层表面的栅极绝缘膜；
形成于所述栅极绝缘膜上的栅极电极；
形成于所述半导体层表面的第二导电型的源极层；
从所述栅极电极的漏极侧的端部分离且形成于所述半导体层表面的第二导电型的高浓度的漏极层；
在所述栅极电极和所述高浓度的漏极层之间的所述半导体层表面上，邻接于所述高浓度的漏极层的第一导电型的杂质层。
2、如权利要求1所述的半导体装置，其特征在于：
具有第二导电型的低浓度的漏极层，所述第二导电型的低浓度的漏极层比所述高浓度的漏极层浓度低、并且扩散得更深，形成于从所述栅极电极的下侧到所述高浓度的漏极层之间的所述半导体层的表面。
3、如权利要求1或2所述的半导体装置，其特征在于：
具有和所述高浓度的漏极层及所述杂质层重叠、比所述高浓度的漏极层浓度低、并且扩散得更深的中浓度的漏极层。
4、如权利要求1或2所述的半导体装置，其特征在于：
在所述半导体层上形成比所述栅极绝缘膜更厚的绝缘膜，所述栅极电极延展到所述厚绝缘膜的一部分上。
5、如权利要求4所述的半导体装置，其特征在于：
所述杂质层和所述厚绝缘膜的漏极侧的一端邻接。
6、一种半导体装置的制造方法，其特征在于，具有以下工序：
在第一导电型的半导体层的表面上形成栅极绝缘膜的工序；
在所述栅极绝缘膜上形成栅极电极的工序；
在离开所述栅极电极的所述半导体层的表面上形成第二导电型的高浓度的漏极层的工序；
使第一导电型的杂质层与所述高浓度的漏极层邻接、且在所述半导体层的表面上形成的形成所述杂质层的工序。
7、如权利要求6所述的半导体装置的制造方法，其特征在于：
具有形成低浓度的漏极层的工序，所述漏极层比所述高浓度的漏极层浓度低、并且扩散得更深，形成于从所述栅极电极的下侧到所述高浓度的漏极层之间的所述半导体层的表面。
8、如权利要求7所述的半导体装置的制造方法，其特征在于：
具有以下工序，即在和所述高浓度的漏极层及所述杂质层重叠的区域形成邻接于所述低浓度的漏极层、比所述高浓度的漏极层深、且低浓度的中浓度的漏极层的工序。
9、如权利要求7或8所述的半导体装置的制造方法，其特征在于，具有：
在所述低浓度的漏极层上形成比所述栅极绝缘膜厚的绝缘膜的工序，
形成所述杂质层的工序为，以所述杂质层与所述厚绝缘膜的漏极侧的一端邻接的方式进行。
CNB2007101496432A 2006-09-15 2007-09-10 半导体装置及其制造方法 Expired - Fee Related CN100552975C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006251079 2006-09-15
JP251079/06 2006-09-15

Publications (2)

Publication Number Publication Date
CN101145580A CN101145580A (zh) 2008-03-19
CN100552975C true CN100552975C (zh) 2009-10-21

Family

ID=39187696

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2007101496432A Expired - Fee Related CN100552975C (zh) 2006-09-15 2007-09-10 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US8735997B2 (zh)
KR (1) KR100909171B1 (zh)
CN (1) CN100552975C (zh)
TW (1) TW200814320A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101800246A (zh) * 2010-03-12 2010-08-11 上海宏力半导体制造有限公司 一种esd器件

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010010408A (ja) * 2008-06-27 2010-01-14 Sanyo Electric Co Ltd 半導体装置及びその製造方法
CN101728384B (zh) * 2008-11-03 2011-07-06 世界先进积体电路股份有限公司 栅极绝缘双接面晶体管静电放电防护元件
CN102136491B (zh) * 2008-11-03 2013-04-10 世界先进积体电路股份有限公司 栅极绝缘双接面晶体管静电放电防护元件
US8049307B2 (en) 2009-01-23 2011-11-01 Vanguard International Semiconductor Corporation Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices
DE102010014370B4 (de) * 2010-04-09 2021-12-02 X-Fab Semiconductor Foundries Ag LDMOS-Transistor und LDMOS - Bauteil
CN104347702A (zh) * 2013-07-23 2015-02-11 旺宏电子股份有限公司 半导体装置及其制造方法
US9768283B1 (en) * 2016-03-21 2017-09-19 Vanguard International Semiconductor Corporation High-voltage semiconductor structure
US10658354B2 (en) * 2018-09-17 2020-05-19 Semiconductor Components Industries, Llc Electrostatic discharge handling for lateral transistor devices

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US43487A (en) * 1864-07-12 Improvement in corn-harvesters
US4811075A (en) * 1987-04-24 1989-03-07 Power Integrations, Inc. High voltage MOS transistors
US5072268A (en) * 1991-03-12 1991-12-10 Power Integrations, Inc. MOS gated bipolar transistor
JPH0652791A (ja) 1992-07-30 1994-02-25 Nippon Steel Corp 電子銃の製造方法
US6144070A (en) * 1997-08-29 2000-11-07 Texas Instruments Incorporated High breakdown-voltage transistor with electrostatic discharge protection
JP3315356B2 (ja) * 1997-10-15 2002-08-19 株式会社東芝 高耐圧半導体装置
US5918137A (en) * 1998-04-27 1999-06-29 Spectrian, Inc. MOS transistor with shield coplanar with gate electrode
US6489653B2 (en) * 1999-12-27 2002-12-03 Kabushiki Kaisha Toshiba Lateral high-breakdown-voltage transistor
JP4357127B2 (ja) * 2000-03-03 2009-11-04 株式会社東芝 半導体装置
EP1158583A1 (en) * 2000-05-23 2001-11-28 STMicroelectronics S.r.l. Low on-resistance LDMOS
JP2002043579A (ja) 2000-07-26 2002-02-08 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002134738A (ja) 2000-10-19 2002-05-10 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP3831615B2 (ja) * 2001-01-16 2006-10-11 三洋電機株式会社 半導体装置とその製造方法
JP4131647B2 (ja) * 2002-06-27 2008-08-13 三洋電機株式会社 半導体装置の製造方法
JP3753692B2 (ja) * 2002-12-20 2006-03-08 ローム株式会社 オープンドレイン用ｍｏｓｆｅｔ及びこれを用いた半導体集積回路装置
US6927453B2 (en) 2003-09-30 2005-08-09 Agere Systems Inc. Metal-oxide-semiconductor device including a buried lightly-doped drain region
US8890248B2 (en) * 2004-08-26 2014-11-18 Texas Instruments Incorporation Bi-directional ESD protection circuit
JP5114824B2 (ja) * 2004-10-15 2013-01-09 富士通セミコンダクター株式会社 半導体装置およびその製造方法
KR100638456B1 (ko) * 2004-12-30 2006-10-24 매그나칩 반도체 유한회사 이에스디 보호회로 및 그 제조방법
US7414287B2 (en) * 2005-02-21 2008-08-19 Texas Instruments Incorporated System and method for making a LDMOS device with electrostatic discharge protection
JP4845410B2 (ja) * 2005-03-31 2011-12-28 株式会社リコー 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101800246A (zh) * 2010-03-12 2010-08-11 上海宏力半导体制造有限公司 一种esd器件

Also Published As

Publication number Publication date
KR20080025351A (ko) 2008-03-20
US8735997B2 (en) 2014-05-27
TW200814320A (en) 2008-03-16
CN101145580A (zh) 2008-03-19
KR100909171B1 (ko) 2009-07-23
US20080067617A1 (en) 2008-03-20

Similar Documents

Publication Publication Date Title
CN100552975C (zh) 半导体装置及其制造方法
KR102224364B1 (ko) 고전압 반도체 소자 및 그 제조 방법
US7125777B2 (en) Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)
CN1755945B (zh) 半导体器件
US7981783B2 (en) Semiconductor device and method for fabricating the same
US8158475B2 (en) Gate electrodes of HVMOS devices having non-uniform doping concentrations
JP4384224B2 (ja) 高圧接合型電界効果トランジスタ
CN101425466B (zh) 半导体部件及其制造方法
US6888176B1 (en) Thyrister semiconductor device
US10910493B2 (en) Semiconductor device and method of manufacturing the same
US8673712B2 (en) Power transistor with high voltage counter implant
JP4477309B2 (ja) 高耐圧半導体装置及びその製造方法
KR20130103430A (ko) 반도체 장치의 제조 방법
KR100535853B1 (ko) 반도체 장치 및 그 제조 방법
JP5431663B2 (ja) 半導体装置及びその製造方法
KR100587605B1 (ko) 고전압 트랜지스터 및 그 제조방법
KR20150097946A (ko) 반도체 소자의 제조 방법
JP2009088449A (ja) 半導体装置およびその製造方法
KR101267889B1 (ko) 반도체 소자 및 그 제조방법
KR20060104023A (ko) 반도체 소자 및 그 제조방법
KR101175231B1 (ko) 반도체 소자 및 그 제조방법
CN101577230B (zh) 半导体器件的制造方法
KR20060108298A (ko) 반도체 소자 및 그 제조방법
KR20060108279A (ko) 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091021

Termination date: 20210910