CN103296084A - 用于FinFET的装置和方法 - Google Patents

用于FinFET的装置和方法 Download PDF

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CN103296084A
CN103296084A CN2012102449514A CN201210244951A CN103296084A CN 103296084 A CN103296084 A CN 103296084A CN 2012102449514 A CN2012102449514 A CN 2012102449514A CN 201210244951 A CN201210244951 A CN 201210244951A CN 103296084 A CN103296084 A CN 103296084A
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李宜静
林佑儒
万政典
吴政宪
柯志欣
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种FinFET，其包括形成在衬底中的隔离区、形成在衬底上方的斗篷形有源区，其中该斗篷形有源区具有突出在隔离区顶面之上的上部部分。此外，FinFET包括包围斗篷形有源区的沟道的栅电极。本发明还公开了用于FinFET的装置和方法。

Description

用于FinFET的装置和方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及用于FinFET的装置和方法。
背景技术
半导体工业由于各种电子元件(即：晶体管、二极管、电阻器、电容器等)集成密度的不断提高而得到了快速发展。在很大程度上，集成密度的提高得益于最小部件尺寸的不断减小，使得更多的元件可以集成在给定区域内。然而，部件尺寸越小可能导致漏电流越多。最近，对更小电子器件的需求有所增加，因而需要减少半导体器件的漏电流。
在互补金属氧化物半导体(CMOS)场效应晶体管(FET)中，有源区包括漏极、源极、连接在漏极和源极之间的沟道区以及位于沟道上控制沟道区开关状态的栅极。当栅极电压大于阈值电压时，漏极和源极之间建立起导电沟道。因此，电子或空穴可以在漏极和源极之间移动。另一方面，当栅极电压小于阈值电压时，理想情况下，沟道被截断，漏极和源极之间没有电子或空穴流动。不过，随着半导体器件尺寸不断缩小，由于短沟道漏电效应，栅极无法完全控制沟道区，尤其是沟道区远离栅极的部分。因此，在半导体器件缩小到深亚30纳米尺寸后，传统平面型晶体管的相应短栅极长度可导致栅极不能实质上关闭沟道区。
随着半导体技术的发展，鳍式场效应晶体管(FinFET)已成为进一步减少半导体器件的漏电流的有效选择。在FinFET中，包括漏极、沟道区和源极的有源区从FinFET设置在其上的半导体衬底的表面向上突起。FinFET的有源区像鳍一样，横截面的形状呈矩形。此外，FinFET的栅极结构像倒置的U形一样从三面包围有源区。因此，栅极结构对沟道的控制得以增强。传统平面型晶体管的短沟道漏电效应得以减少。这样，当FinFET被关闭时，栅极结构可以更好地控制沟道，以便减少漏电流。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种装置，包括：
形成在衬底中的第一隔离区，其中所述第一隔离区具有第一非垂直侧壁；
形成在所述衬底中的第二隔离区，其中所述第二隔离区具有第二非垂直侧壁；
形成在所述衬底中的V形凹槽，其中所述V形凹槽、所述第一非垂直侧壁和所述第二非垂直侧壁形成在所述衬底中的斗篷形凹槽；
在所述衬底上方的形成在所述斗篷形凹槽中的斗篷形有源区，其中所述斗篷形有源区具有在所述隔离区的顶面之上突出的上部部分，并且其中所述斗篷形有源区包括：
第一漏极/源极区；
第二漏极/源极区；以及
在所述第一漏极/源极区与所述第二漏极/源极区之间连接的沟道；
以及
包围所述斗篷形有源区的所述沟道的栅电极。
在可选实施例中，所述装置进一步包括：形成在所述斗篷形有源区与所述栅电极之间的栅极介电层。
在可选实施例中，所述斗篷形有源区由硅锗形成。
在可选实施例中，由所述第一非垂直侧壁和所述V形凹槽形成的转角在约130度到约160度的范围内。
在可选实施例中，所述第一隔离区为浅沟槽隔离结构。
在可选实施例中，所述V形凹槽具有范围在约100度到约110度之间的内角。
在可选实施例中，所述栅电极、所述第一漏极/源极区、所述第二漏极/源极区和所述沟道形成FinFET。
根据本发明的另一个方面，提供了一种器件，包括：
形成在衬底中的第一漏极/源极区；
形成在所述衬底中的第二漏极/源极区；
在所述第一漏极/源极区和所述第二漏极/源极区之间连接的沟道，其中所述第一漏极/源极区、所述第二漏极/源极区和所述沟道形成斗篷形有源区；以及，包围所述沟道的栅电极。
在可选实施例中，所述斗篷形有源区具有V形底部。
在可选实施例中，所述V形底部具有范围在约100度到约110度之间的内角。
在可选实施例中，所述器件进一步包括：形成在所述衬底中的第一隔离区；
形成在所述衬底中的第二隔离区，其中所述第一隔离区和所述第二隔离区形成在所述斗篷形有源区的相对侧；以及形成在所述栅电极和所述斗篷形有源区之间的栅极介电层。
在可选实施例中，所述栅极介电层包括：形成在所述第一隔离区与所述栅电极之间的第一部分；形成在所述斗篷形有源区的第一侧壁与所述栅电极之间的第二部分；形成在所述斗篷形有源区的顶面与所述栅电极之间的第三部分；形成在所述斗篷形有源区的第二侧壁与所述栅电极之间的第四部分；以及形成在所述第二隔离区与所述栅电极之间的第五部分。
在可选实施例中，所述第一隔离区包括浅沟槽隔离结构；以及所述第二隔离区包括所述浅沟槽隔离结构。
在可选实施例中，所述第一漏极/源极区由硅锗形成；所述第二漏极/源极区由硅锗形成；以及所述沟道由硅锗构成。
根据本发明的又一个方面，提供了一种方法，包括：
在衬底中形成第一隔离区；
在所述衬底中形成第二隔离区；
通过去除所述衬底的一部分，在所述第一隔离区与所述第二隔离区之间形成凹槽；
对所述凹槽进行表面处理以形成斗篷形凹槽；以及
使用外延生长形成斗篷形有源区。
在可选实施例中，所述方法进一步包括：使用第一离子注入工艺在所述斗篷形有源区中形成第一漏极/源极区；使用第二离子注入工艺在所述斗篷形有源区中形成第二漏极/源极区；以及形成在所述第一漏极/源极区与所述第二漏极/源极区之间连接的沟道。
在可选实施例中，所述方法进一步包括：对所述斗篷形有源区实施化学机械抛光工艺以形成平面；去除所述第一隔离区的第一上部部分；去除所述第二隔离区的第二上部部分；在所述斗篷形有源区的顶面上沉积栅极介电层；以及
在所述栅极介电层上形成栅电极。
在可选实施例中，所述栅电极包围沟道。
在可选实施例中，所述方法进一步包括：在所述斗篷形凹槽中形成硅锗外延区。
在可选实施例中，所述方法进一步包括：在所述衬底上沉积光刻胶层；图案化所述光刻胶层；实施蚀刻工艺以在所述衬底中形成沟槽；以及将介电材料填充到所述沟槽中以形成所述第一隔离区。
附图说明
为更完整的理解本发明及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1示出了根据一实施例的具有斗篷形有源区的FinFET的横截面图；
图2示出了根据一实施例的具有多个隔离区的半导体衬底的横截面图；
图3示出了根据一实施例的图2所示的衬底被移除一部分衬底后的横截面图；
图4示出了根据一实施例的图3所示的衬底被进行表面处理后的横截面图；
图5示出了根据一实施例的图4所示的衬底在衬底的凹槽中生长外延硅锗层后的横截面图；
图6示出了根据一实施例的对硅锗外延区的突出部分实施化学机械抛光工艺后的图5所示半导体器件的横截面图；
图7示出了根据一实施例的图6中所示的衬底被移除STI结构上部部分后的横截面图；
图8示出了根据一实施例的图7中所示的衬底形成有栅极介电层后的横截面图；以及
图9示出了根据一实施例的图8中所示的衬底形成有栅电极后的横截面图。
除非另有说明，不同附图中的相应标号和符号通常指相应部分。附图被绘制成清楚地示例说明各实施例的相关方面，并且不必成比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
本发明将参考具体环境下的实施例，即具有斗篷形有源区的鳍式场效应晶体管(FinFET)，进行描述。然而，本发明的实施例也可以应用于各种不同的半导体器件。以下结合附图对各种实施例进行详细说明。
图1示出了根据一实施例的具有斗篷形有源区的FinFET的横截面图。FinFET 100形成在衬底102上方。FinFET 100包括从横截面图看呈斗篷形的有源区110。更具体地，斗篷形有源区110可包括第一漏极/源极区、第二漏极/源极区以及在第一漏极/源极区和第二漏极/源极区之间连接的沟道(未分别示出)。如图1所示，斗篷形有源区110位于两个隔离区(即第一隔离区106和第二隔离区108)之间。根据一实施例，第一隔离区106和第二隔离区108都可通过采用浅沟槽隔离(STI)结构来实现。
FinFET 100可进一步包括在斗篷形有源区110上方形成的栅电极114。更具体地，栅极介电层112形成在斗篷形有源区110和栅电极114之间。如图1所示，栅极介电层112沉积在斗篷形有源区110以及隔离区106和108的顶部上。根据一实施例的制造FinFET 100的方法将在下面参考图2-图9进行描述。
具有斗篷形有源区110的有利特点是在硅锗外延生长工艺之前，斗篷形凹槽(图4中未示出但有说明)为后续的外延生长提供清洁的表面。因此，斗篷形沟槽中可生长单晶硅锗外延层。所述单晶硅锗外延层有助于提高FinFET 100的沟道的结晶质量。
图2示出了根据一实施例的具有多个隔离区的半导体衬底的横截面图。衬底102可以是硅衬底。可选地，衬底102也可包括其他半导体材料(如锗)和化合物半导体材料(如碳化硅、砷化镓、砷化铟、磷化铟等)。根据一实施例，衬底102可以是晶体结构。根据另一实施例，衬底102可以是绝缘体上硅(SOI)衬底。
在衬底102中形成隔离区106和108。根据一实施例，隔离区106和108采用STI结构实现。STI结构(如隔离区106)可采用包括光刻和蚀刻工艺的合适技术来制造。特别是，光刻和蚀刻工艺可包括在衬底102上方沉积诸如光刻胶的常用掩模材料，将掩模材料曝光成图案，根据图案蚀刻衬底102。以这种方式，结果可形成多个开口。然后，用介电材料填充这些开口从而形成STI结构(如隔离区106和108)。然后，实施化学机械抛光工艺(CMP)以去除介电材料的过量部分，剩余部分即为隔离区106和108。
如图2所示，隔离区106和108的侧壁彼此相对。应注意，尽管图2示出了两个分开的隔离区106和108，然而，隔离区106和108也可以是一个连续区域的不同部分，该连续区域根据一实施例可形成一隔离环。衬底102的上部部分104位于隔离区106和108之间，并与这两个隔离区邻接。上部部分104的宽度W可以很小。根据一实施例，宽度W小于约50nm。应当理解，整个说明书中列举的尺寸仅为示例，可改变为不同的值。
图3示出了根据一实施例的图2所示的衬底被移除一部分后的横截面图。衬底部分104(如图2所示)的上部部分被去除，形成了V形凹槽302。根据一实施例，V形凹槽302的底部高于隔离区106和108的底面。根据另一实施例，V形凹槽302底部可以实质上与隔离区106和108的底部齐平或低于隔离区106和108的底部。
衬底部分104的上部部分可采用合适的技术去除。更具体地，可使用蚀刻工艺获得V形凹槽302。例如，采用沉积和光刻技术在隔离区106和108顶面上方形成诸如光刻胶掩模和/或硬掩膜的图案化掩模(未示出)。其后，实施蚀刻工艺，如反应离子蚀刻(RIE)或其他干蚀刻、各向异性湿蚀刻或其他任何合适的各向异性蚀刻工艺，以形成V形凹槽302。根据一实施例，可使用诸如四甲基氢氧化铵(TMAH)的蚀刻剂进行各向异性湿蚀刻工艺。这样的各向异性湿蚀刻工艺可具有约3-5％的TMAH浓度。蚀刻工艺可以在约20°到约35℃的温度范围内进行。
如图3所示，V槽形底部具有一个内角。根据一实施例，该内角在约100度到约110度的范围内。具有图3所示的V形凹槽的一个有利特点是V形凹槽有助于改善后续硅锗外延生长的质量。
图4示出了根据一实施例的图3中所示的衬底进行表面处理后的横截面图。实施表面处理以处理衬底102的暴露表面，其中暴露表面在V形凹槽内部。表面处理可以在能够具有真空环境的腔室(未示出)内进行。处理所用的工艺气体包括含氧气体和蚀刻气体，这两种气体可同时使用。蚀刻气体具有蚀刻衬底102的功能。根据一实施例，含氧气体包括氧气(O2)、臭氧(O3)或它们的组合。蚀刻气体可包括含氟气体，如CF4。根据另一实施例，蚀刻气体可包括含氯气体，如HCl。在表面处理期间，流量比，即含氧气体流量与含氧气体和蚀刻气体总流量之比，可在约0.99到约0.995的范围内。含氧气体和蚀刻气体的总压力可在约500毫托mTorr到1.5托Torr的范围内。根据另一实施例，表面处理可包括等离子体处理，其中等离子体的相应的射频(RF)功率可在约1,100Watt到约1,500Watt的范围内。在表面处理期间，衬底102可加热到温度在约150°到约300℃的范围内。
由于表面处理，衬底102的表面得到了改善。衬底102表面上形成的小凹陷和岛状物被去除。此外，如图4所示，隔离区(如隔离区106)的部分侧壁也由于表面处理被去除。结果，形成了斗篷形凹槽402。该斗篷形凹槽有助于改善后续外延生长的结晶质量。外延生长将在下面参考图5进行描述。
斗篷形凹槽402可由三个角确定。如图4所示，隔离区106的侧壁不是垂直的。侧壁与垂直方向之间的偏离由第一角α来限定。根据一实施例，第一角α在约0度到约20度的范围内。非垂直侧壁与V形凹槽之间的转向点可由第二角β来限定。根据一实施例，第二角β在约130度到约160度的范围内。V形凹槽可由第三角γ来限定。根据一实施例，第三角γ在约100度到约110度的范围内。
表面处理后，可对衬底102及隔离区106和108的侧壁进行清洁工艺。可利用清洁工艺去除衬底102表面上形成的原生氧化物(如果有)。根据一实施例，清洁工艺可用稀释后的HF溶液和/或高温H2烘烤工艺来实施。
图5示出了根据一实施例的图4所示的衬底在衬底的斗篷形凹槽中生长外延硅锗区后的横截面图。可使用诸如选择性外延生长(SEG)合适的技术在斗篷形凹槽402(如图4所示)中生长硅锗以形成斗篷形外延区110。根据一实施例，可在外延生长过程中原位掺杂n型掺杂剂(如硼)或p型掺杂剂(如磷)。可选地，外延层可采用其他合适的技术(如离子注入、扩散等)进行掺杂。如图5所示，斗篷形外延区110的顶面可生长成高于隔离区(如隔离区106)的顶面。
根据一实施例，斗篷形外延区110可包括锗。可选地，斗篷形外延区110可包括硅锗。外延层可采用CMOS兼容外延工艺来生长。CMOS兼容外延工艺可包括CVD等。
取决于斗篷形外延区110的期望成分，用于外延生长的前体可包括含硅气体和含锗气体，如SiH4和GeH4，和/或类似物，并且对含硅气体和含锗气体的分压力进行调节以改变锗与硅的原子比。根据一实施例，斗篷形外延区110的硅锗可以表示为Si1-xGex，其中x是锗的原子百分比，并且可以在0与1之间的范围内。根据一实施例，斗篷形外延区110包括高纯度锗(x等于1)。该斗篷形外延区110也可包括低锗浓度。例如，x在约0.1到0.3的范围内。
根据另一实施例，该斗篷形外延区110可包括其他半导体材料，如碳化硅、高纯度硅；III-V化合物半导体材料，如GaN、AlAs、GaN、InN、AlN、InxGa(1-x)N、AlxGa(1-x)N、AlxIn(1-x)N、AlxInyGa(1-x-y)N以及它们的组合，其中x和y每一个都可在约0到约1的范围内。
根据一实施例，该斗篷形外延区110的下部部分和上部部分可具有不同的组成。例如，该斗篷形外延区110的下部部分和上部部分的锗可具有不同的百分比。例如，上部部分可具有比下部部分高的锗百分比。这种结构可用于形成p型FinFET。斗篷形外延区110的上部部分可具有比下部部分低的锗百分比。这种结构可用于形成n型FinFET。
图6示出了根据一实施例的在对硅锗外延区的突出部分实施化学机械抛光工艺后的图5所示的半导体器件的横截面图。根据硅锗FinFET的制造工艺，硅锗外延生长形成的突出部分被去除，以便得到如图6所示的平面。特别是，对图5所示的硅锗外延生长区的突出部分进行研磨直到硅锗部分的顶面与邻接的隔离区(如隔离区106)的顶面齐平。
可采用合适的技术(如研磨、抛光和/或化学蚀刻)来实施去除工艺。根据一实施例，去除工艺可以采用CMP工艺来实施。在CMP工艺中，将蚀刻材料和研磨材料放置成与硅锗区110的顶面接触，使用研磨垫(未示出)将突出部分磨掉，直至得到期望的平面。
图7示出了根据一实施例的图6中所示的半导体器件在隔离区的上部部分被去除后的横截面图。FinFET的形成过程可包括对隔离区106和108开槽，以便所得到的隔离区106和108的顶面低于斗篷形外延区110的顶面。斗篷形外延区110高于隔离区106和108顶面的部分形成了半导体鳍状件。
图8示出了根据一实施例的图7中所示的衬底形成有栅极介电层后的横截面图。栅极介电层112可由氧化物材料形成，以及可通过合适的氧化工艺(如湿或干热氧化)、溅射来形成或者通过使用正硅酸乙酯(TEOS)和氧气作为前体的CVD技术来形成。此外，栅极介电层112可以是高K介电材料，如氧化硅、氮氧化硅、氮化硅、氧化物、含氮氧化物、氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪、它们的组合或者类似材料。
图9示出了根据一实施例的图8中所示的衬底形成有栅电极后的横截面图。栅电极114可包括选自以下组的导电材料：该组包括多晶硅(poly-Si)、多晶硅锗(poly-SiGe)、金属材料、金属硅化物材料、金属氮化物材料、金属氧化物材料和类似材料。例如，金属材料可包括钽、钛、钼、钨、铂、铝、铪、钌，它们的组合以及类似物。金属硅化物材料包括硅化钛、硅化钴、硅化镍、硅化钽、它们的组合以及类似物。金属氮化物材料包括氮化钛、氮化钽、氮化钨、它们的组合以及类似物。金属氧化物材料包括氧化钌、氧化铟锡、它们的组合或类似物。
应注意，也可以采用其他制造工艺来形成栅电极。其他制造工艺包括但不限于CVD、物理气相沉积(PVD)、等离子体增强CVD(PECVD)、常压CVD(APCVD)、高密度等离子体CVD(HDPCVD)、低压化学气相沉积(LPCVD)、原子层CVD(ALCVD)以及类似工艺。
应注意，栅电极114形成后可能是非平面。可采用CMP工艺平坦化栅极的顶面。前面已参考图6对CMP工艺进行了描述，因而在此不再赘述。
尽管已经详细地描述了本发明实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员通过本发明应理解，现有的或今后开发的用于执行与根据本发明采用的相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在范围内。

Claims (10)

1.一种装置，包括：
形成在衬底中的第一隔离区，其中所述第一隔离区具有第一非垂直侧壁；
形成在所述衬底中的第二隔离区，其中所述第二隔离区具有第二非垂直侧壁；
形成在所述衬底中的V形凹槽，其中所述V形凹槽、所述第一非垂直侧壁和所述第二非垂直侧壁形成在所述衬底中的斗篷形凹槽；
在所述衬底上方的形成在所述斗篷形凹槽中的斗篷形有源区，其中所述斗篷形有源区具有在所述隔离区的顶面之上突出的上部部分，并且其中所述斗篷形有源区包括：
第一漏极/源极区；
第二漏极/源极区；以及
在所述第一漏极/源极区与所述第二漏极/源极区之间连接的沟道；以及
包围所述斗篷形有源区的所述沟道的栅电极。
2.根据权利要求1所述的装置，进一步包括：
形成在所述斗篷形有源区与所述栅电极之间的栅极介电层。
3.根据权利要求1所述的装置，其中所述斗篷形有源区由硅锗形成。
4.一种器件，包括：
形成在衬底中的第一漏极/源极区；
形成在所述衬底中的第二漏极/源极区；
在所述第一漏极/源极区和所述第二漏极/源极区之间连接的沟道，其中所述第一漏极/源极区、所述第二漏极/源极区和所述沟道形成斗篷形有源区；以及
包围所述沟道的栅电极。
5.根据权利要求4所述的器件，其中所述斗篷形有源区具有V形底部。
6.根据权利要求5所述的器件，其中所述V形底部具有范围在约100度到约110度之间的内角。
7.根据权利要求4所述的器件，进一步包括：
形成在所述衬底中的第一隔离区；
形成在所述衬底中的第二隔离区，其中所述第一隔离区和所述第二隔离区形成在所述斗篷形有源区的相对侧；以及
形成在所述栅电极和所述斗篷形有源区之间的栅极介电层。
8.一种方法，包括：
在衬底中形成第一隔离区；
在所述衬底中形成第二隔离区；
通过去除所述衬底的一部分，在所述第一隔离区与所述第二隔离区之间形成凹槽；
对所述凹槽进行表面处理以形成斗篷形凹槽；以及
使用外延生长形成斗篷形有源区。
9.根据权利要求8所述的方法，进一步包括：
使用第一离子注入工艺在所述斗篷形有源区中形成第一漏极/源极区；
使用第二离子注入工艺在所述斗篷形有源区中形成第二漏极/源极区；以及
形成在所述第一漏极/源极区与所述第二漏极/源极区之间连接的沟道。
10.根据权利要求9所述的方法，进一步包括：
对所述斗篷形有源区实施化学机械抛光工艺以形成平面；
去除所述第一隔离区的第一上部部分；
去除所述第二隔离区的第二上部部分；
在所述斗篷形有源区的顶面上沉积栅极介电层；以及
在所述栅极介电层上形成栅电极。
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CN106206727A (zh) * 2014-10-17 2016-12-07 台湾积体电路制造股份有限公司 鳍式场效应晶体管（FinFET）器件及其形成方法
CN106803505A (zh) * 2015-11-25 2017-06-06 三星电子株式会社 半导体装置
CN108987473A (zh) * 2017-05-31 2018-12-11 台湾积体电路制造股份有限公司 半导体结构及其形成方法

Families Citing this family (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8742509B2 (en) * 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US9559099B2 (en) 2012-03-01 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US8957476B2 (en) * 2012-12-20 2015-02-17 Intel Corporation Conversion of thin transistor elements from silicon to silicon germanium
US9029246B2 (en) 2013-07-30 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming epitaxial structures
KR102058895B1 (ko) 2013-08-23 2019-12-24 현대모비스 주식회사 요크 유격 보상장치
US9553012B2 (en) 2013-09-13 2017-01-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and the manufacturing method thereof
KR102151768B1 (ko) * 2014-01-27 2020-09-03 삼성전자주식회사 반도체 장치 및 그 제조방법
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
EP2924722A1 (en) * 2014-03-28 2015-09-30 IMEC vzw Method for manufacturing a semiconductor-on-insulator device
US9209185B2 (en) * 2014-04-16 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for FinFET device
US9443769B2 (en) 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
US9484376B2 (en) * 2014-05-30 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor isolation structure and manufacturing method thereof
KR101595780B1 (ko) * 2014-08-14 2016-02-19 경북대학교 산학협력단 GaN-Fin 구조 및 FinFET를 제조하는 방법 및 이러한 방법으로 제조된 GaN-Fin 구조를 사용하는 소자 및 FinFET
US9324868B2 (en) * 2014-08-19 2016-04-26 Globalfoundries Inc. Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections
TWI556285B (zh) * 2014-08-21 2016-11-01 國立中央大學 在矽基板上磊晶成長鍺薄膜的方法
US9391201B2 (en) 2014-11-25 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure and manufacturing the same
US9349652B1 (en) 2014-12-12 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device with different threshold voltages
US9780214B2 (en) 2014-12-22 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin- FET and manufacturing method thereof
US9768301B2 (en) 2014-12-23 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Short channel effect suppression
US10141310B2 (en) 2014-12-23 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Short channel effect suppression
US10134871B2 (en) 2014-12-23 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of high-K dielectric oxide by wet chemical treatment
US9515071B2 (en) 2014-12-24 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Asymmetric source/drain depths
US9425250B2 (en) 2014-12-30 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor with wurtzite channel
US9647090B2 (en) 2014-12-30 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Surface passivation for germanium-based semiconductor structure
US9601626B2 (en) 2015-01-23 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structure with two channel layers and manufacturing method thereof
US9443729B1 (en) 2015-03-31 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming FinFET devices
CN106158748B (zh) * 2015-04-07 2022-01-18 联华电子股份有限公司 半导体元件及其制作方法
US9590102B2 (en) 2015-04-15 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9680014B2 (en) 2015-04-17 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin structures and manufacturing method thereof
US9570557B2 (en) 2015-04-29 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Tilt implantation for STI formation in FinFET structures
US9773786B2 (en) 2015-04-30 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. FETs and methods of forming FETs
US9461110B1 (en) 2015-04-30 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. FETs and methods of forming FETs
US10269968B2 (en) 2015-06-03 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9647071B2 (en) 2015-06-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. FINFET structures and methods of forming the same
US9449975B1 (en) 2015-06-15 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices and methods of forming
US10755984B2 (en) 2015-06-24 2020-08-25 Intel Corporation Replacement channel etch for high quality interface
KR102445837B1 (ko) 2015-06-26 2022-09-22 인텔 코포레이션 고 이동도 반도체 소스/드레인 스페이서
US9425313B1 (en) 2015-07-07 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9953881B2 (en) 2015-07-20 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET device
US9472620B1 (en) 2015-09-04 2016-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US10734488B2 (en) 2015-09-11 2020-08-04 Intel Corporation Aluminum indium phosphide subfin germanium channel transistors
US9680017B2 (en) 2015-09-16 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin FET and manufacturing method thereof
DE112015006945T5 (de) 2015-09-25 2018-06-21 Intel Corporation Transistoren mit hoher Elektronenbeweglichkeit mit Heteroübergang-Dotierstoffdiffusionsbarriere
US10388764B2 (en) 2015-09-25 2019-08-20 Intel Corporation High-electron-mobility transistors with counter-doped dopant diffusion barrier
US9922975B2 (en) 2015-10-05 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof
KR102323943B1 (ko) 2015-10-21 2021-11-08 삼성전자주식회사 반도체 장치 제조 방법
US10121858B2 (en) 2015-10-30 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated semiconductor structure planarization
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9960273B2 (en) 2015-11-16 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9997615B2 (en) * 2015-11-30 2018-06-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure with epitaxial growth structure
US9564317B1 (en) 2015-12-02 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a nanowire
US9716146B2 (en) 2015-12-15 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method with solid phase diffusion
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US9660033B1 (en) 2016-01-13 2017-05-23 Taiwan Semiconductor Manufactuing Company, Ltd. Multi-gate device and method of fabrication thereof
US9876098B2 (en) 2016-01-15 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a gate spacer
US10038095B2 (en) 2016-01-28 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. V-shape recess profile for embedded source/drain epitaxy
US10453925B2 (en) 2016-01-29 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth methods and structures thereof
CN107045983B (zh) * 2016-02-05 2020-07-10 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US10340383B2 (en) 2016-03-25 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having stressor layer
US10164061B2 (en) 2016-05-19 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating non-volatile memory device array
US10734522B2 (en) 2016-06-15 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with gate stacks
WO2017218015A1 (en) * 2016-06-17 2017-12-21 Intel Corporation High-mobility field effect transistors with wide bandgap fin cladding
WO2017218014A1 (en) 2016-06-17 2017-12-21 Intel Corporation Field effect transistors with gate electrode self-aligned to semiconductor fin
US10008414B2 (en) 2016-06-28 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for widening Fin widths for small pitch FinFET devices
US9620628B1 (en) 2016-07-07 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming contact feature
US10269938B2 (en) 2016-07-15 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having a doped passivation layer
EP3273468B1 (en) * 2016-07-20 2023-03-15 Imec Vzw Monolithic integration of semiconductor materials
US10002759B2 (en) 2016-07-26 2018-06-19 Applied Materials, Inc. Method of forming structures with V shaped bottom on silicon substrate
US10217741B2 (en) 2016-08-03 2019-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure and method of forming same through two-step etching processes
US9853150B1 (en) 2016-08-15 2017-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating epitaxial gate dielectrics and semiconductor device of the same
US9865589B1 (en) 2016-10-31 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. System and method of fabricating ESD FinFET with improved metal landing in the drain
US11152362B2 (en) 2016-11-10 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure
US10879240B2 (en) 2016-11-18 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure
US9847334B1 (en) 2016-11-18 2017-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with channel layer
US10134870B2 (en) 2016-11-28 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method of manufacturing the same
US10529862B2 (en) * 2016-11-28 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming semiconductor fin thereof
US10062782B2 (en) 2016-11-29 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device with multilayered channel structure
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US11011634B2 (en) 2016-11-30 2021-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Elongated source/drain region structure in finFET device
US9865595B1 (en) 2016-12-14 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same
US9899273B1 (en) 2016-12-15 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with dopants diffuse protection and method for forming the same
EP3339244A1 (en) * 2016-12-21 2018-06-27 IMEC vzw Source and drain contacts in fin- or nanowire- based semiconductor devices.
US10522643B2 (en) 2017-04-26 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate
US10522417B2 (en) 2017-04-27 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with different liners for PFET and NFET and method of fabricating thereof
US10453753B2 (en) 2017-08-31 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET
US10276697B1 (en) 2017-10-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance FET with improved reliability performance
US10522557B2 (en) 2017-10-30 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Surface topography by forming spacer-like components
US10366915B2 (en) 2017-11-15 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices with embedded air gaps and the fabrication thereof
US10510894B2 (en) 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure having different distances to adjacent FinFET devices
US10854615B2 (en) 2018-03-30 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having non-merging epitaxially grown source/drains
US10665697B2 (en) 2018-06-15 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11302535B2 (en) 2018-06-27 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Performing annealing process to improve fin quality of a FinFET semiconductor
US10790352B2 (en) 2018-06-28 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. High density capacitor implemented using FinFET
US10388771B1 (en) 2018-06-28 2019-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and device for forming cut-metal-gate feature
US10886226B2 (en) 2018-07-31 2021-01-05 Taiwan Semiconductor Manufacturing Co, Ltd. Conductive contact having staircase barrier layers
US10998241B2 (en) 2018-09-19 2021-05-04 Taiwan Semiconductor Manufacturing Co., Ltd. Selective dual silicide formation using a maskless fabrication process flow
US10971605B2 (en) 2018-10-22 2021-04-06 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy dielectric fin design for parasitic capacitance reduction
KR102655419B1 (ko) 2019-05-14 2024-04-05 삼성전자주식회사 반도체 장치
US11728344B2 (en) 2019-06-28 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid SRAM design with nano-structures
US11469238B2 (en) 2019-09-26 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Non-interleaving N-well and P-well pickup region design for IC devices
CN113823565A (zh) * 2020-06-18 2021-12-21 新时代电力系统有限公司 基于超结的垂直型氮化镓jfet和mosfet功率器件的方法和系统
US11804374B2 (en) * 2020-10-27 2023-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strain relief trenches for epitaxial growth

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156202A1 (en) * 2004-01-17 2005-07-21 Hwa-Sung Rhee At least penta-sided-channel type of FinFET transistor
JP2005228781A (ja) * 2004-02-10 2005-08-25 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20080277745A1 (en) * 2007-05-07 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Fin filled effect transistor and method of forming the same
US20080296667A1 (en) * 2007-05-29 2008-12-04 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
US20090039361A1 (en) * 2005-05-17 2009-02-12 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
CN101924105A (zh) * 2009-05-29 2010-12-22 台湾积体电路制造股份有限公司 集成电路结构
US20110147828A1 (en) * 2009-12-21 2011-06-23 Murthy Anand S Semiconductor device having doped epitaxial region and its methods of fabrication

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1555688B1 (en) 2004-01-17 2009-11-11 Samsung Electronics Co., Ltd. Method of manufacturing a multi-sided-channel finfet transistor
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7442609B2 (en) * 2004-09-10 2008-10-28 Infineon Technologies Ag Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
US20070267722A1 (en) * 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7547637B2 (en) * 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7777250B2 (en) * 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US7829407B2 (en) 2006-11-20 2010-11-09 International Business Machines Corporation Method of fabricating a stressed MOSFET by bending SOI region
KR100991382B1 (ko) 2007-05-10 2010-11-02 주식회사 하이닉스반도체 다면 채널을 갖는 트랜지스터 및 그 형성방법
US8629478B2 (en) * 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US9484462B2 (en) 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US8609517B2 (en) * 2010-06-11 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. MOCVD for growing III-V compound semiconductors on silicon substrates
US8183134B2 (en) * 2010-10-19 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces
US8455930B2 (en) * 2011-01-05 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Strained semiconductor device with facets
US8598675B2 (en) * 2011-02-10 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure profile for gap filling
US8349692B2 (en) * 2011-03-08 2013-01-08 Globalfoundries Singapore Pte. Ltd. Channel surface technique for fabrication of FinFET devices
US8618556B2 (en) * 2011-06-30 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design and method of fabricating same
US9105660B2 (en) 2011-08-17 2015-08-11 United Microelectronics Corp. Fin-FET and method of forming the same
US8841701B2 (en) * 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US9559099B2 (en) * 2012-03-01 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8742509B2 (en) 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8836016B2 (en) * 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US9159554B2 (en) * 2013-05-01 2015-10-13 Applied Materials, Inc. Structure and method of forming metamorphic heteroepi materials and III-V channel structures on si

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156202A1 (en) * 2004-01-17 2005-07-21 Hwa-Sung Rhee At least penta-sided-channel type of FinFET transistor
JP2005228781A (ja) * 2004-02-10 2005-08-25 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20090039361A1 (en) * 2005-05-17 2009-02-12 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US20080277745A1 (en) * 2007-05-07 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Fin filled effect transistor and method of forming the same
US20080296667A1 (en) * 2007-05-29 2008-12-04 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
CN101924105A (zh) * 2009-05-29 2010-12-22 台湾积体电路制造股份有限公司 集成电路结构
US20110147828A1 (en) * 2009-12-21 2011-06-23 Murthy Anand S Semiconductor device having doped epitaxial region and its methods of fabrication

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097935B (zh) * 2014-05-23 2018-05-29 安华高科技通用Ip(新加坡)公司 具有无掺杂本体块的鳍式场效应晶体管
CN105097935A (zh) * 2014-05-23 2015-11-25 美国博通公司 具有无掺杂本体块的鳍式场效应晶体管
CN106206727B (zh) * 2014-10-17 2020-04-17 台湾积体电路制造股份有限公司 鳍式场效应晶体管(FinFET)器件及其形成方法
US10546956B2 (en) 2014-10-17 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
CN106206727A (zh) * 2014-10-17 2016-12-07 台湾积体电路制造股份有限公司 鳍式场效应晶体管（FinFET）器件及其形成方法
US10686077B2 (en) 2014-10-17 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10840378B2 (en) 2014-10-17 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10964819B2 (en) 2014-10-17 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US11158744B2 (en) 2014-10-17 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US11721762B2 (en) 2014-10-17 2023-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
CN106803505A (zh) * 2015-11-25 2017-06-06 三星电子株式会社 半导体装置
CN106803505B (zh) * 2015-11-25 2021-08-17 三星电子株式会社 半导体装置
CN108987473A (zh) * 2017-05-31 2018-12-11 台湾积体电路制造股份有限公司 半导体结构及其形成方法

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