EP3273468B1

EP3273468B1 - Monolithic integration of semiconductor materials

Info

Publication number: EP3273468B1
Application number: EP17181795.0A
Authority: EP
Inventors: Amey Mahadev Walke; Nadine Collaert; Rita Rooyackers
Original assignee: Interuniversitair Microelektronica Centrum vzw IMEC
Current assignee: Interuniversitair Microelektronica Centrum vzw IMEC
Priority date: 2016-07-20
Filing date: 2017-07-18
Publication date: 2023-03-15
Anticipated expiration: 2037-07-18
Also published as: US20180025911A1; EP3273468A1; US10236183B2

Description

Technical field of the invention

The present invention relates to the field of integration of further semiconductor materials and devices on (pre-processed) semiconductor substrates, and in particular to the integration of III-V materials and devices thereon.

Background of the invention

Si MOSFETs are typically suitable for analog, logic and memory applications which have an operating frequency up to a few 10s of GHz. Conversely, radio frequency (RF) components operating at frequencies above 100 GHz are fabricated separately on III-V wafers, such as GaAs or InP. Sequential integration of III-V materials and devices on top of 300 mm and larger Si wafers would allow to expand the available operating frequency on a single chip beyond 100 GHz. Furthermore, the Si wafers may be pre-processed to comprise semiconductor devices, so that different device types may be combined on a single chip. One way to achieve this monolithic integration is by bonding a III-V wafer to a Si wafer. However, these III-V wafers are typically only available in a smaller size (below 300 mm) and are very expensive.
US2015/0279725 discloses methods for manufacturing semiconductor-on-insulator devices comprising providing a pre-patterned donor wafer, providing a handling wafer, and bonding the pre-patterned donor wafer to the handling wafer.
There is thus still a need within the art for good methods of integrating semiconductor materials, and in particular III-V materials, on other substrates without the need for expensive III-V wafers.

Summary of the invention

It is an object of the present invention to provide methods of integrating further materials on semiconductor substrates.
It is an advantage of embodiments of the present invention that the further materials can be III-V materials.
It is an advantage of embodiments of the present invention that no expensive III-V wafers need to be used.
It is an advantage of embodiments of the present invention that the substrate can have been pre-processed to comprise a first semiconductor device.
It is an advantage of embodiments of the present invention that a second semiconductor device can be fabricated from the further materials, without degrading the first semiconductor device.
It is an advantage of embodiments of the present invention that the vertical integration of a first and second semiconductor device allows for a reduced amount and/or length of interconnects; as compared to a horizontal integration of both.
It is an advantage of embodiments of the present invention that devices comprising III-V materials and devices comprising group IV materials can be integrated into a single structure.
It is an advantage of embodiments of the present invention that the integrated further materials may have a low amount of defects, such as threading dislocations.
The above objective is accomplished by a method and device according to the present invention.
In a first aspect, the present invention relates to a method for forming a semiconductor structure, comprising:

a. providing a donor substrate (100) having a trench (300) therein and having a plurality of semiconductor layers (200) epitaxially grown on top of one another on the donor substrate (100) in such a way that at least a first of the semiconductor layers is present in the trench (300), wherein the trench (300):
1. (i) is opening toward a top of the donor substrate (100),
2. (ii) is defined by a monocrystalline bottom (310) and non-crystalline sidewalls (320), and
3. (iii) has a width of from 10 nm to 10 µm;
b. providing a carrier substrate (400) comprising:
1. (i) a semiconductor substrate at a bottom thereof,
2. (ii) a first semiconductor device on the semiconductor substrate, and
3. (iii) electrical contacts to the first semiconductor device, at a top of the carrier substrate (400);
c. bonding the donor substrate (100) to the carrier substrate (400) with the top of the donor substrate (100) and the top of the carrier substrate (400) facing each other;
d. removing at least part of said donor substrate (100) in such a way as to expose a semiconductor layer (210) grown on the monocrystalline bottom (310);
e. removing at least part of the semiconductor layer (210) grown on the monocrystalline bottom (310), thereby modifying the plurality of semiconductor layers (200); and
f. optionally forming a second semiconductor device from the modified plurality of semiconductor layers (200), and
wherein the trench (300) has a depth to width aspect ratio smaller than 1.42:1.

In a second aspect, the present invention relates to a semiconductor structure as defined in claim 13.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as set out in the claims.
Although there has been constant improvement, change and evolution of devices in this field, the present concepts are believed to represent substantial new and novel improvements, including departures from prior practices, resulting in the provision of more efficient, stable and reliable devices of this nature.
The above and other characteristics, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is given for the sake of example only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.

Brief description of the drawings

Fig. 1 is a schematic representation of an embodiment according to the present invention.
Fig. 2 shows electron microscope images of layers of semiconductor material grown, in accordance with embodiments of the present invention, in a trench having a V-shaped bottom.
Fig. 3 to 7 shows schematic representations of vertical cross-sections of different second semiconductor devices which may be formed from the layers of semiconductor material, in accordance with embodiments of the present invention.

In the different figures, the same reference signs refer to the same or analogous elements.

Description of illustrative embodiments

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.
Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Moreover, the terms ton, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
Similarly, it is to be noticed that the term "coupled", also used in the claims, should not be interpreted as being restricted to direct connections only. The terms "coupled" and "connected", along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Thus, the scope of the expression "a device A coupled to a device B" should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means. "Coupled" may mean that two or more elements are either in direct physical or electrical contact, or that two or more elements are not in direct contact with each other but yet still co-operate or interact with each other.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art, and as long as they remain within the scope of the claims. For example, in the following claims, any of the claimed embodiments can be used in any combination.
Furthermore, some of the embodiments are described herein as a method or combination of elements of a method that can be implemented by a processor of a computer system or by other means of carrying out the function. Thus, a processor with the necessary instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
In a first aspect, the present invention relates to a method for forming a semiconductor structure, comprising:

a. providing a donor substrate having a plurality of semiconductor layers epitaxially grown on top of one another, at least one semiconductor layer being present in a trench of the donor substrate, wherein the trench:
1. (i) is opening toward a top of the donor substrate,
2. (ii) is defined by a monocrystalline bottom and non-crystalline sidewalls, and
3. (iii) has a width of from 10 nm to 10 µm;
b. providing a carrier substrate comprising:
1. (i) a semiconductor substrate at a bottom thereof,
2. (ii) a first semiconductor device on the semiconductor substrate, and
3. (iii) electrical contacts to the first semiconductor device, at a top of the carrier substrate;
c. bonding the donor substrate to the carrier substrate with the top of the donor substrate and the top of the carrier substrate facing each other;
d. removing at least part of said donor substrate in such a way as to expose a semiconductor layer grown on the monocrystalline bottom;
e. removing at least part of the semiconductor layer grown on the monocrystalline bottom, thereby modifying the plurality of semiconductor layers; and
f. optionally forming a second semiconductor device from the modified plurality of semiconductor layers,
wherein the trench has a depth to width aspect ratio smaller than 1.42:1.

In other words, step a may consist in providing a donor substrate having a plurality of semiconductor layers epitaxially grown on top of one another, at least one semiconductor layer being present in a trench of the donor substrate.
In other words, the first aspect relates to a method for forming a semiconductor structure, comprising

bonding a donor substrate, having a plurality of semiconductor layers (200) epitaxially grown on top of one another thereon wherein at least a first of the semiconductor layers is in a trench (300) present in the donor substrate, to a carrier substrate comprising a first semiconductor device thereon;
removing at least part of said donor substrate (100) in such a way as to expose a semiconductor layer (210) grown on the bottom (310) of the trench,
removing at least part of the semiconductor layer (210) grown on the bottom (310), thereby modifying the plurality of semiconductor layers (200); and
optionally forming a second semiconductor device from the modified plurality of semiconductor layers (200),
wherein the trench has a depth to width aspect ratio smaller than 1.42:1.

The semiconductor structure is a structure comprising a second semiconductor device integrated on top of, i.e. at a level above, a first semiconductor device. It may be referred to as a sequentially or monolithically integrated structure. In preferred embodiments, the second semiconductor device on top of the first semiconductor device may overlap with that first semiconductor device, i.e. a projection of the first and of the second semiconductor device onto a same plane, perpendicular to the substrate normal, may at least partially coincide. The semiconductor structure typically comprises III-V and/or group IV semiconductor materials.
The donor substrate comprises a semiconductor substrate having a monocrystalline top surface (e.g. a monocrystalline semiconductor substrate), a non-crystalline layer overlaying the semiconductor substrate, and at least one trench in the non-crystalline layer and exposing part of the monocrystalline top surface. In a preferred embodiment, obtaining such a donor substrate may comprise the steps of a1. Providing a silicon wafer, a2. Forming preliminary trenches in the silicon wafer (e.g. by using a hard mask such a mask formed of an oxide layer and a nitride layer; preferably the preliminary trenches are separated from one another by an average distance of from 10 nm to 10 µm), a3. Filling the preliminary trenches with an oxide (e.g. silicon dioxide) in such a way that the top surface of the oxide is co-planar with the top surface of the silicon wafer (this can for instance be achieved by overfilling the preliminary trenches with the oxide, followed by performing a CMP step and removing the hard mask), a4. Forming (final) trenches by etching through the silicon wafer exposed between the oxide filling (this can for instance be performed by using tetramethylammonium hydroxide (TMAH), NaOH or KOH which leads to the formation of V-shaped final trenches having exposed {111} planes), thereby forming trenches opening toward a top of the donor substrate, defined by a Si monocrystalline bottom and oxide non-crystalline sidewalls (the final trenches preferably have an average width of from 10 nm to 10 µm).
The monocrystalline top surface of the semiconductor substrate typically comprises the monocrystalline bottom of the trench. In preferred embodiments, the semiconductor substrate may comprise one or more group IV or III-V materials. For example, the semiconductor substrate may be a Si, Ge, GaAs or InP substrate, or an on-insulator type substrate such as an Si-on-insulator or a Ge-on-insulator substrate. Preferably, the semiconductor substrate is made of a group IV material. Most preferably, it is made of Si. The trench extends upwards from the semiconductor substrate through a non-crystalline material present on the monocrystalline surface. The non-crystalline material may for example be part of a shallow trench isolation (STI). Growing at least one (first)semiconductor layer inside the trench advantageously limits the area over which a uniform layer need to be grown and thus limits the appearance of defect in the layer. In embodiments, the trench may have a length of from 1 µm to 1 mm. The length of the trench is typically larger than the width of the trench. Preferably, the trench has a uniform shape along its length. In particular, the vertical cross-section of the trench taken perpendicularly to the longitudinal direction of the trench is the same all along the length of the trench. In particular, it is especially preferred that the height of the trench is uniform along its length. Also, if more than one trench is made, e.g. for the purpose of forming more than one second semiconductor device, the trenches preferably all have the same vertical cross-section taken perpendicularly to the longitudinal direction of the trench. In typical embodiments wherein filling the trenches comprises a step wherein a semiconductor layer (e.g. the first semiconductor layer) forms an overburden above the trench, the overburden will be similar for the different trenches when the trenches have the same vertical cross-section, thus simplifying a subsequent removal of said overburden (e.g. through CMP) as typically desired. In other embodiments wherein the plurality of semiconductor layers does not extend above the top of the trench, trenches having the same vertical cross-section enable for instance that a subsequent CMP step stops within or at the same layer for each plurality of layers in each trench. This problem is much easier to solve by using a wide-field approach where a single wide trench is used and where the plurality of layers is patterned into separate devices after growth. In embodiments which are not part of the invention, the trench may have a depth to width aspect ratio of 1.42:1 or larger and preferably 2:1 or larger. A trench of this first type may typically have a width of 10 nm to 100 nm and may be referred to as an aspect ratio trapping (ART) trench. In the invention the trench has a depth to width aspect ratio smaller than 1.42:1 (e.g. from 1.41: 1 to 0.1:1 or from 1.41:1 to 0.5:1). A trench of this second type may typically have a width of 200 nm to 5 µm and may be referred to as a wide field trench. A wide field trench advantageously allows for a less critical alignment of the carrier and the donnor substrates during bonding. Furthermore, it advantageously allows a plurality of second semiconductor devices to be formed from a single plurality of multilayers in a trench.
In preferred embodiments, the trench may comprise a bottom portion, i.e. a portion of the trench at its lower end, having a vertical cross-section having a V-shape. The V-shape is typically oriented such that the trench tapers towards its bottom. In other embodiments, the vertical cross section may have another tapered shape. In embodiments, the vertical cross-section may be taken perpendicularly to the longitudinal direction of the trench. In preferred embodiments, a bottom portion of the trench may be defined by two crystalline planes having miller indexes {111}. In particular, it may have a vertical cross-section having a V-shape and be defined by two crystalline planes having miller indexes {111}. The trench as such and the shape and crystal orientation of the bottom portion advantageously hinder threading dislocations and other crystal defects in the semiconductor layers, which may arise from a lattice mismatch between a semiconductor layer and the surface it is epitaxially grown on (e.g. between a first semiconductor layer grown on the semiconductor bottom on one hand and the monocrystalline bottom on another hand), from propagating upwards and into further semiconductor layers. When the semiconductor bottom is Si, in order to form a bottom portion defined by two crystalline planes having miller indexes {111}, we can selectively etch the Si present between the non-crystalline sidewalls by e.g. using a KOH or NaOH solution.
In typical embodiments, the plurality of semiconductor layers will comprise one or more layers of III-V materials. In preferred embodiments, the plurality of semiconductor layers may be two or more layers of III-V materials. In embodiments, at least one of the one or more layers of III-V materials may be selected from InP, InAlAs, InGaAs, InAs, GaAs, InGaSb, GaSb, InGaP, AlGaAs, and InGaAlP. In preferred embodiments, the plurality of semiconductor materials may be grown in an order (before bonding) which is reverse to an order in which they will appear in the second semiconductor device (after bonding).
The first layer of the plurality of layer is typically a buffer layer having a thickness (i.e. height) of from 100 to 500 nm. This is much less than the buffer layer typically used for blanket growth of a III-V buffer on a Si substrate.
The buffer layer may for instance be made of InP. The buffer layer may either have the same lattice constant as the surface present at the bottom of the trench, or may have a different lattice constant. In this latter case, the buffer will typically be strained at the bottom of the trench and will relax towards the top of the trench. Preferably, the buffer layer has the same lattice constant as the surface present at the bottom of the trench. When the first layer is a buffer layer (e.g. InP), the second layer grown on top of the buffer layer will typically be a junction layer also called cap layer. This layer has for purpose to ensure a good contact with the metal that will serve to interconnect the device in the final semiconductor structure according to an embodiment of the present invention. This is therefore typically a doped semiconductor layer such as a n-doped InGaAs layer. The third layer is preferably an etch stop layer. This layer can be for instance an InP layer. It permits to protect the next layer during step e where some etching steps are often involved. Depending on the type of second semiconductor device formed, the fourth layer can be a layer of channel material or it can be a barrier/spacer layer.
In preferred embodiments, the plurality of semiconductor layers may extend above the top of the trench. This is preferably achieved by growing at least one semiconductor layer inside the trench and, after filling the trench therewith, and preferably after a CMP step making coinciding the top of the trench filling with the top of the trench, further growing one or more further semiconductor layers above the trench filling. In such a case, any further semiconductor layer will typically use the layer it is grown on as a seed layer; thereby again advantageously limiting the area over which uniform layers need to be grown. For instance, each of the further semiconductor layer may have an horizontal cross-section substantially equal in shape and dimensions to the top surface of the semiconductor layer on which it is epitaxially grown.
In a particularly preferred embodiment, the first semiconductor layer completely fills the trench and the further semiconductor layer(s) are grown on the first semiconductor layer.
In other embodiments, the top surface of the plurality of semiconductor layers may be coplanar with the top surface of the donor substrate, i.e. the plurality of semiconductor layers is completely within the trench.
In embodiments, at least one of the plurality of semiconductor layers may have a top surface substantially free of threading dislocations, i.e. comprising less than 10⁸ threading dislocations per cm². In preferred embodiments, the semiconductor layer grown on the monocrystalline bottom may have a top surface comprising less than 10⁸ threading dislocations per cm². A semiconductor layer which is substantially free of defects may typically be obtained when growing the layer over a limited area in a trench, particularly when combined with a trench shape which promotes aspect ratio trapping (e.g. when the first semiconductor layer is epitaxially grown on the monocrystalline bottom) and/or when a semiconductor layer is epitaxially grown on a sufficiently defect free layer with which it has only a limited lattice mismatch (e.g. when a further semiconductor layer is grown on the first semiconductor layer, the first semiconductor layer being sufficiently free of defects and matching the lattice constant of the further layer). In embodiments, defects, such as treading dislocations, may also be reduced by annealing at least one of the plurality of semiconductor layers, such as the buffer layer (i.e. the first semiconductor layer). This is particularly relevant when a wide field trench is used. In the particularly preferred embodiment where upon growing the first semiconductor layer in the trench, it overfills the trench, an annealing step is preferably performed before a planarization (e.g. CMP) step. In some embodiments, a layer of the plurality of semiconductor layers may be annealed prior to growing a further layer thereon. Annealing is particularly advantageous when the trench has a depth to width aspect ratio smaller than 2:1, such as smaller than 1.42:1. Such an annealing causes some of the eventually remaining threading dislocations to migrate towards the sidewalls where they will be trapped, thereby decreasing the threading dislocation density of the top surface. This annealing step can typically be dispensed of for trenches having an aspect ratio of 2:1 or more, or even 1.42: 1 or more.
The carrier substrate comprises a semiconductor substrate, a first (pre-processed) semiconductor device thereon and electrical contacts to said first semiconductor device. Expressed differently, the carrier substrate comprises a semiconductor substrate, a front-end-of-line (FEOL) and a back-end-of-line (BEOL). The material used for the semiconductor substrate comprised in the carrier substrate may be any of the material described as being suitable for the semiconductor substrate that may be comprised in the donor substrate. The material used in each of these semiconductor substrates may be independently selected. Silicon is preferred as it is cheaper and will ultimately be sacrificed. The first semiconductor device may for example be a transistor or a memory device. The electrical contacts allow the device to be operated.
Bonding the donor substrate to the carrier substrate allows the two to be integrated into a single bonded structure. In preferred embodiments, the donor substrate and carrier substrate may be aligned, during bonding, such that the trench in the donor substrate overlaps the first semiconductor device in the carrier substrate. In preferred embodiments, the method may further comprise a step b', before step c, of providing a bonding layer on top of the donor substrate, the carrier substrate, or preferably both. The material of each bonding layer may be independently selected. In preferred embodiments, each bonding layer may be a dielectric layer. A dielectric bonding layer has the advantage of providing electrical isolation between the donor and carrier substrate. In preferred embodiments, each bonding layer may comprise an oxide (e.g. SiO₂) or a carbide-nitride (e.g. SiCN). In preferred embodiments, the dielectric bonding layer(s) may be selectively etchable with respect to the non-crystalline material of the non-crystalline sidewalls. For instance, the dielectric bonding layer may be a carbide-nitride (e.g. SiCN) layer while the non-crystalline material of the non-crystalline sidewalls may be an oxide (e.g. SiO₂). For the formation of a high electron mobility transistor (HEMT), in the prior art, a high band-gap material is used between the wafer (e.g. InP or GaAs) and the channel. In embodiments of the present invention where a bonding layer is present, a further high band-gap material is not necessary. After the provision of the bonding layers, a planarization step (e.g. CMP) of these bonding layers may be performed to facilitate bonding.
In step d, removing at least part of the donor substrate may for example be performed by using an ion cut technique, also known as smart cut, backside grinding and/or (wet or dry) etching.
In step d, at least part of the donor substrate is removed. The donor substrate is typically formed of a semiconductor wafer and non-crystalline sidewalls (typically STIs) which together define one or more trenches. The part of the donor substrate which is typically remove is the semiconductor wafer. This can be achieved by first removing a large portion of it by grinding or cutting, followed by a selective removal of the remaining of it. This selective removal can be achieved by using tetramethylammonium hydroxide if the semiconductor wafer is silicon.
In step e of removing at least part of the (first) semiconductor layer grown on the monocrystalline bottom may typically comprise an etching of said semiconductor layer. The removed part of the semiconductor layer is preferably a part comprising the entirety of the interface between the first semiconductor layer and the monocrystalline bottom. The removed part of said first semiconductor layer typically comprises at least the first portion of the first semiconductor layer comprising a majority (and preferably substantially all) of the threading dislocations, as well as other crystal defects; such that the remainder of the semiconductor layers after removal may be low in threading dislocations (and preferably substantially free of threading dislocations). In embodiments, removing at least part of the first semiconductor layer grown on the monocrystalline bottom may be accompanied by removing at least part of the non-crystalline sidewalls. Preferably, the complete first layer may be removed.
Once the semiconductor wafer of the donor semiconductor substrate has been removed in step d, all or part of the non-crystalline material forming the side-walls (e.g. an oxide such as SiO₂ typically provided as STIs) and optionally part of the bonding layer may also be removed. For instance, particularly when the plurality of semiconductor layers does not extend above the top of the trench, part of the STIs may be removed by CMP. The CMP step may be continued in step e until part or all of the first semiconductor layer is removed as well. When only part of the first semiconductor layer is removed, it is the part that contacts the bottom of the trench and which is therefor the richest in defects which is removed. The CMP is preferably performed in such a way that the first semiconductor layer and the STI are polished at the same rate. Once that (at least) defective part has been removed, the remaining of the STI may optionally be removed as well. In another instance, particularly when the first epitaxial (buffer) layer fills the trench and the rest of the plurality of semiconductor layers extends above the top of the trench, all of STIs may be removed. This can be done by CMP, thereby simultaneously removing the first (buffer) semiconductor layer. This can also be done by removing the STI selectively towards the bonding layer (e.g. by etching), followed by removing selectively (for instance by etching) the first (buffer) semiconductor layer, thereby exposing the second grown semiconductor layer, and optionally removing part of the of the bonding layer. In embodiments, when more than one trench and more than one plurality of semiconductor layers was grown on the carrier substate, part of the bonding layer between two modified pluralities of semiconductor layers may optionally be removed. Removing the remaining STI or part of the bonding layer is not always required because the isolation provided by either is typically a wished feature. However, if for instance, an isolation of a different quality is preferred, the remaining STI or part of the bonding layer can indeed be removed and eventually replaced by the isolation of a different quality.
Forming a second semiconductor device from the plurality of semiconductor layers may typically comprise removing, such as etching, part of the plurality of semiconductor layers and/or forming additional device features, such as a gate, source, drain and contacts. In preferred embodiments, step f may comprise patterning the modified plurality of semiconductor layers to form at least one second semiconductor device. In embodiments, step f may comprise at least partially, such as completely, removing the non-crystalline sidewalls. The vertical integration of a second semiconductor device on top of a first semiconductor device advantageously allows for a reduced amount and/or length of interconnects; as compared to a structure where both are horizontally integrated. In embodiments, two or more second semiconductor devices may be formed from the plurality of semiconductor layers.
In preferred embodiments, the first semiconductor device may be a complementary metal-oxide-semiconductor (CMOS) device and the second semiconductor device may be a radio-frequency (RF) device. In preferred embodiments, the second semiconductor device may comprise a high-electron-mobility transistor or a metal-oxide-semiconductor field-effect transistor. The independent selection of materials in the first and second semiconductor device advantageously enables different device types to be combined in the same structure. In particular, embodiments of the present invention advantageously allow a device suitable for radio-frequency operation and a lower frequency CMOS device to be combined on a single chip, i.e. in a single structure.
In a particularly preferred embodiment of the first aspect, the present invention may relate to a method for forming a semiconductor structure, comprising:

a1. Providing a silicon wafer,
a2. Forming preliminary trenches in the silicon wafer (e.g. by using a hard mask such a mask formed of an oxide layer and a nitride layer; preferably the preliminary trenches are separated from one another by an average distance of from 10 nm to 10 µm),
a3. Filling the preliminary trenches with an oxide (e.g. silicon dioxide) in such a way that the top surface of the oxide is co-planar with the top surface of the silicon wafer (this can for instance be achieved by overfilling the preliminary trenches with the oxide, followed by performing a CMP step and removing the hard mask),
a4. Forming final trenches by etching through the silicon wafer exposed between the oxide filling (this can for instance be performed by using a tetramethylammonium hydroxide (TMAH) solution, a NaOH solution, or a KOH solution, which leads to the formation of V-shaped final trenches having exposed {111} planes), thereby forming trenches opening toward a top of the donor substrate, defined by a Si monocrystalline bottom and oxide non-crystalline sidewalls (the final trenches preferably have an average width of from 10 nm to 10 µm),
a5. Growing a first semiconductor layer (preferably a III-V material and most preferably InP) in the final trenches (this is typically done by letting the first semiconductor layer overgrow the final trenches, followed by an optional annealing step to increase defect trapping at the sidewalls, followed by a CMP step to obtain a flat surface for the top of the first semiconductor layer coinciding with the top of the final trench),
a6. Growing the further semiconductor layer(s) on the first semiconductor layer in order to form the plurality of semiconductor layers,
- b. providing a carrier substrate comprising:
  - (i) a Si wafer at a bottom thereof,
  - (ii) a first semiconductor device on the semiconductor substrate (i.e. a FEOL), and
  - (iv) electrical contacts to the first semiconductor device, at a top of the carrier substrate (i.e. a REOL),
- b' 1. depositing a bonding dielectric layer on top of the carrier substrate and on top of the donor substrate (this bonding dielectric is preferably selected in such a way that it can be preserved upon selective etching of the oxide filling the preliminary trenches and forming the sidewalls of the final trenches; this selectivity has the advantage that it preserves isolation of the host wafer after bonding, which saves process steps in some embodiments),
- b'2. Perfoming a planarization step of the bonding layers (e.g. by CMP; this planarization facilitates bonding),
- c. bonding the donor substrate to the carrier substrate with the top of the donor substrate and the top of the carrier substrate facing each other (in this step, the bonding layers are bonded to each other),
- d. removing the Si wafer (this can be for instance performed by SMART cut or by grinding combined with CMP followed by dry or preferably wet etching),
- e. removing the oxide selectively with respect to the bonding dielectric and removing the first semiconductor layer selectively with respect to the other semiconductor layers of the plurality of semiconductor layers, thereby exposing the remaining semiconductor layer(s) and forming a modified plurality of semiconductor layers, and
- f. optionally forming a second semiconductor device from the modified plurality of semiconductor layers (200).

Each step of this particularly preferred embodiment can of course be used in replacement to a corresponding step in any embodiment of the first aspect.
In embodiments, after step e, the modified plurality of semiconductor layers may comprise:

(i) a channel layer on top of the bonding layer;
(ii) a spacer layer on top of the channel layer and a barrier layer thereon, the spacer and barrier layer separated by a delta doping layer;
(iii) an etch stop layer on top of the barrier layer; and
(iv) a capping layer on top of the etch stop layer; (see e.g. Fig. 3 to 5)

(i) a barrier layer on top of the bonding layer and a spacer layer thereon, the barrier and spacer layer separated by a delta doping layer;
(ii) a channel layer on top of the spacer layer;
(iii) an etch stop layer on top of the channel layer; and
(iv) a capping layer on top of the etch stop layer; (see e.g. Fig. 6)

(i) a channel layer on top of the bonding layer, a delta doping layer present therein;
(ii) an etch stop layer on top of the channel layer; and
(iii) a capping layer on top of the etch stop layer; (see e.g. Fig. 7) and step f may comprise:
- f1. providing a contact layer on top of the capping layer,
- f2. opening a window in the contact layer, extending from the contact layer to the etch stop layer, thereby exposing the barrier layer or the channel layer;
- f3. providing a gate (e.g. by deposition of a metal followed by patterning and etching);
- f4. providing a gate isolation (e.g. by depositing an oxide layer embedding the gate, followed by planarization by CMP, deposition of an etch stop layer, deposition of an oxide layer on the etch stop layer, and opening a window where the contacts must be formed); and
- f5. providing a gate contact, a source contact and/or a drain contact.

The capping layer may for instance be a InGaAs layer.
The contact layer may for instance be a metal layer such as a molybdenum layer.
Step f2 can for instance be performed by forming a mask by lithography followed by etching of the contact layer and of the capping layer from the gate region.
Step f5 can for instance be performed by a damascene process.
In embodiments, the gate may be a T-shaped gate. For RF applications, very low resistance and capacitance are required. It is therefore advantageous to have very low resistance for the gate. A T-shaped gate permits this. To this effect, an opened window can be filled with gate material, followed by a CMP. Then windows may be opened for the contacts. The T shape is used to reduce the resistance of the gate. Since these RF circuit transistors can be quite wide (long channel), resistance of the gate can be very high. This T shape is characteristic of RF transistors. The horizontal bar of the T provides a region of lower resistance. The present flow has the advantage to permit the use of different metals for contacting the gate on one hand and the source/drain on the other. This can have an impact on the contact resistance of the III-V material. Gate and source/drain can be separately optimized.
The best metal to use on the S/D is not necessarily the best material to use for the gate on the InAlAs barrier. The gate material on the barrier is selected such that it provides minimum leakage through the gate and at the same time sets an appropriate threshold voltage of the transistor. In embodiments, the gate isolation may be an oxide, a nitride and/or an air gap. In embodiments, the gate, the gate contact, the source contact and/or the drain contact may, independently, consist of one or more materials, such as one or more metals. In preferred embodiments, the plurality of semiconductor layers may comprise a layer of channel material, i.e. a layer of material suitable to form a channel in a field-effect-transistor, and step c may form a bonded structure where one of the bonding layers is directly in contact with the layer of channel material. Particularly when the bonding layers are insulating layers, such as dielectric layers, the layer of channel material may advantageously be directly in contact with a bonding layer, dispensing with the need for any additional layers in between both.
In preferred embodiments, a delta doping monolayer may be present within one of the plurality of semiconductor layers. In embodiments, the delta doping monolayer may be present away from the centre of the thickness of the layer of channel material.
A delta doping layer permits to provide carriers to the channel and below spacers and below the n+ layer of the contacts.
In preferred embodiments, during or after step c, the carrier substrate may be kept at temperatures not exceeding 500 °C. Embodiments of the present invention advantageously allow the second semiconductor device to be formed without exposing the carrier substrate to high temperatures during or after the bonding. Not exposing the carrier substrate to these high temperatures advantageously allows any first semiconductor devices therein to not deteriorate and thus to remain functional.
In embodiments, wherein, in step a, only the first of the semiconductor layers is present in the trench and wherein, in step e, removing at least part of the semiconductor layer grown on the monocrystalline bottom of the trench consists in removing the whole semiconductor layer grown on the monocrystalline bottom of the trench.
The invention will now be described by a detailed description of several embodiments of the invention. It is clear that other embodiments of the invention can be configured according to the knowledge of the person skilled in the art without departing from the true technical teaching of the invention, the invention being limited only by the terms of the appended claims.
Reference will be made to transistors. These are three-terminal devices having a first main electrode such as a drain, a second main electrode such as a source and a control electrode such as a gate for controlling the flow of electrical charges between the first and second main electrodes.
It will be clear for a person skilled in the art that the present invention is also applicable to similar devices that can be configured in any transistor technology, including for example, but not limited thereto, CMOS, BICMOS, Bipolar and SiGe BICMOS technology.

Example 1: Fabrication and bonding of substrates in accordance with the present invention

We now refer to Fig. 1. In step (a), a donor substrate (100), e.g. comprising a Si wafer, is provided. The donor substrate (100) has a plurality of trenches (300) therein. The donor substrate (100) has a plurality of semiconductor layers (200) epitaxially grown thereon. Furthermore, the donor substrate (100) comprises a shallow trench isolation (STI), e.g. in silicon oxide, In this manner, each trench is defined by a monocrystalline bottom (310) and non-crystalline sidewalls (320). The plurality of semiconductor layers (200), e.g. layers of III-V materials, is epitaxially grown in and extending above the trenches. To obtain this plurality of semiconductor layers (200), for instance, a buffer layer filling each trench and forming an overburden can first be grown. Subsequently, an annealing step to move the defects towards the non-cyrstalline sidewalls may be performed, next, a chemical-mechanical polish (CMP) to remove the overburden can be performed. Finally, further semiconductor layers are grown on the buffer layer.

In a next step, the structure is covered with a bonding layer (500), e.g. a bonding oxide.

In step (b), a carrier substrate (400) is provided, comprising a first semiconductor device (not shown) on a semiconductor substrate and electrical contacts (not shown) thereto. The carrier substrate is also covered with a bonding layer (500) in a subsequent step, e.g. a bonding oxide.
In step (c), the donor substrate (100) is flipped and bonded to the carrier substrate (400) by joining both bonding layers (500).
In step (d1), the donor substrate (100) is partially removed, e.g. by a SMART cut technique. For instance, a top portion of the Si wafer can be removed if present.
In step (d2), a further crystalline portion of the donor substrate (100) (e.g. the rest of the Si wafer if present) is removed selectively by etching down to the first semiconductor layer (210), which was grown on the monocrystalline bottom (310).
In step (e), the shallow trench isolation is removed selectively with respect to the bonding layer (500); and the first semiconductor layer (210), comprising the treading dislocations, is etched back selectively with respect to the rest of the plurality of layers (200).
At the bottom left of Fig. 1, the full bonding layer is preserved acting as an isolation between several modified plurality of semiconductor layers (200).
At the bottom right of Fig. 1, optionally, part of the bonding layer is removed.
The remainder of the plurality of semiconductor layers (200) can then be further processed to form second semiconductor devices; e.g. see example 3.

Example 2: Epitaxial growth of semiconductor layers in a trench having a V-shaped bottom portion

We now refer to Fig. 2. Electron microscope images show the growth of an InP first semiconductor layer (210; Fig. 2a) and InGaAs (220) on InP (210) semiconductor layers (Fig. 2b) in a trench having a V-shaped bottom portion. For both images, the V-shape coincides with the Si crystalline bottom (310) having corresponding miller indices {111} and promotes the extinction of treading dislocations in the first semiconductor layer (210), so that they do not propagate into further semiconductor layers (220). The trench is further confined by the STI non-crystalline sidewalls (320).

Example 3: Different second semiconductor devices based on different integration schemes

Different second semiconductor devices can be made out of the remainder of the plurality of semiconductor layers (200), depending on the integration scheme used; a few possibilities are depicted in Figs. 3 to 7. Figs. 3 to 5 show variations of a high-electron mobility transistor (HEMT) second semiconductor device, whereas Figs. 6 to 7 show variations of a metal-oxide-semiconductor field-effect transistor (MOSFET) second semiconductor device.
We now refer to Fig. 3. Bonded to the carrier wafer (400), which comprises first semiconductor devices (not shown), through the bonding layer(s) (500; e.g. 150-1000 nm) is a plurality of semiconductor layers (250, 260, 280, 290). The plurality of semiconductor layers comprises a thick layer of InGaAs channel material (250; e.g. 5-12 nm), directly in contact with the bonding layer(s) (500); an InAlAs spacer (271; e.g. 2-4 nm such as 3nm) and an InAlAs barrier (272; e.g. 7-15 nm) layer thereon, comprising a Si delta doping monolayer (260); a 2-3 nm thick InP etch stop layer (280) and a 5-70 nm n++ InGaAs capping layer (290).
Molybdenum contacts (601) cover the capping layer. A window to the InAlAs barrier (272) is opened in the contact(s) (601), capping layer (290) and etch stop layer (280), and a T-shaped gate contact in a second metal (602) is made. Source and drain contacts in a third metal (603) to the molybdenum contacts are provided. The source, drain and gate contacts are isolated from one another by and oxide (701), which comprises an etch stop layer (800). This structure was formed as follow.
To form this structure, on the InGaAs capping layer, we deposited molybdenum. We removed molybdenum from the gate region, thereby opening a window. For this purpose, we used lithography and etched Molybdenum and InGaAs from the gate region and we formed the vertical bar of a T-shaped gate by deposition, patterning and etching, then we deposited an oxide layer embedding the vertical bar of the T-shaped gate, we planarized by CMP and we deposited an etch stop layer. Then we deposited an oxide on the etch stop layer and we opened a window corresponding to the horizontal bar of the T-shaped gate. Then, by a damascene process, the metal for the horizontal bar of the T-shaped gate was deposited. For RF applications, very low resistance and capacitance are required. We therefore need very low resistance for the gate. We therefore used a T-shaped gate. We then opened windows for the source and drain contacts. The T shape is used to reduce the resistance of the gate. Since these RF circuit transistors are quite wide (long channel), resistance of the gate can be very high. This T shape is characteristic of RF transistors. The horizontal bar of the T is a region of lower resistance. The present flow has the advantage to permit the use of different metals for contacting the gate on one hand and the source/drain on the other. This can have an impact on the contact resistance of the III-V material. Gate and source/drain can be separately optimized.
The best metal to use on the molybdenum S/D is not necessarily the best material to use for the gate on the InAlAs barrier.
We now refer to Fig. 4. Starting from a same plurality of III-V semiconducting layers, a different flow leads to a similar HEMT device, differing in that the source, drain and gate contacts all comprise a bottom portion in a second metal (602) and a top portion in a third metal (603).
For this purpose, we open a window like in the example of Fig. 3, then we deposited an oxide, we performed a CMP and we opened windows for the gate and source/drain (S/D) simultaneously in a single step. Then we filled the windows with a metal and we performed a CMP. This method has the advantage to be one step shorter than the flow used for the structure of Fig. 3. In the next step, we deposited an etch stop layer (SiN) which can resist etching in conditions where silicon oxide would not. Then we deposited a layer of oxide and we opened a window for the horizontal bar of the T-shaped gate. A different metal can be chosen for the head of the gate than for the bottom part of the gate. The same is true for the source/drain regions. We can open the S/D together with the gate because you do not need a gate dielectric. For HEMT, it is a schottky contact between the gate and the InAlAs. For a MOSFET flow, a gate dielectric is needed so one need to open the S/D areas after that the gate oxide is deposited. In HEMT, we used Molybdenum over the InGaAs for good contact in the S/D regions but we did not want too much current to flow from gate to channel so we put the gate directly in contact with the InAlAs barrier. The InAlAs was chosen so that it does not allow too much current to flow to the gate. For the horizontal bar of the T we can for instance use copper or W.
We now refer to Fig. 5. Again starting from a same plurality of III-V layers, a different flow leads to a similar HEMT device; here electrical isolation of the gate contact is partially provided by air gaps (702).
It is a self-aligned flow, we deposited Molybdenum on the InGaAs capping layer, then we deposited an oxide thereon. We opened a window in the oxide by dry etching then we etched the Mo and the n+ InGaAs by wet etching, thereby forming a wider window in the Mo and InGaAs than in the oxide. Then we opened widows in the oxide for the S/D contacts. Then we etched anisotropically the etch stop part of the etch stop layer to expose the part of the InAlAs barrier which is overlapping with the opening formed in the oxide. Then we deposited the metal and we performed a CMP. The advantage of this flow is that, since it is self-aligned, access resistance for source and drain is the same. In the previous flows leading to Fig. 3 or 4, if alignment is not perfect, the access resistance will be different for the S and the D. Speed depends on both resistance and capacitance. Resistance is determined by the length of the channel. In Fig. 3 or 4, we can choose to make the capacitance smaller on the drain side by placing the horizontal bar of the T-shaped gate assymetrically. This helps to improve the performances. So forming the T-shaped gate in two steps permits to place the head of the T assymetrically and thereby reduce the capacitance of the drain. It is also possible to shift the gate closer to the source than to the drain so as to reduce the capacitance. However, the self-aligned concept is more reliable. Alignment is difficult and bad alignment can cause the opposite asymmetry as wished. In this process flow leading to Fig. 5, the distance between the S and the G and the G and the D are defined by a single litho step not requiring alignment. In Fig. 3 and 4, there were two lithographic steps, one to open the first window in the Mo and the n+ InGaAs, and one to open the gate in the oxide. This came with a risk of misalignment. In Fig. 5, the dielectric constant of air being 1, the air gaps reduce the capacitance. In fig. 4, we had oxide instead of air so the capacitance was nine times higher.
We now refer to Fig. 6. In contrast with the HEMT device, the order of the channel (250)/ spacer (271)/ delta doping (260)/barrier (272) layers is reversed in this MOSFET device. Furthermore, a wider gate contact (602, 603) is provided.
Here the device has a gate dielectric and there is a small difference in the stack. This is again a self-aligned gate. In HEMT, the InAlAs layer was between InP and inGaAs but for MOSFET we switched InGaAs and InAlAs so that it is InAlAs which is on the bonding layer. The InAlAs serves as a carrier supply layer for the channel. To this effect it comprises a delta doping layer. This is to reduce the access resistance of the source and drain. InAlAs (or InP) is a high band gap material and InGaAs is a low band gap material. Furthermore, the electron affinity of the InGaAs is higher than InAlAs (or InP). Therefore electrons in delta doped InAlAs (or InP) will fall in the channel. Current flows in the region which is typically undoped, where you have more mobility. The distance between the delta doping and the channel is typically 2-3 nm. We provided a molybdenum layer on the InGaAs capping layer, we deposited an oxide on the molybdenum layer, we then opened a window in the oxide, the Mo and the n+InGaAs capping layer. We then deposited a silicon nitride material to form spacers. Then we deposited a gate dielectric and then we deposited the metal and we performed a CMP step. Then we opened windows for forming source and drains, filled with metal then performed a CMP. The flow is almost the same as for the HEMT except for the nitride (or oxide) spacers and by the fact that we need a dielectric between the gate and the channel in the case of the MOSFET. This means that the metal for the gate and the S/D can never be deposited simultaneously because we have to open the dielectric in the S/D regions. In principles it is also possible to open the S/D windows before to fill simultaneously the S/D and the gate with metal but this means that for opening the S/D windows, a resist was deposited, and the presence of resist material in the gate window will make for a bad gate after filling so it is best to first fill the gate, then open the S/D windows. After the gate, we opened windows for S and D, then we performed a CMP. Then we deposited the next layer of the metal. We formed again a T shape head on the top of the gate and again contacts for the source and drains. Three different metals can be used here, one for the bottom of the gate (vertical bar of the T), one for the S/D and one for the head of the gate (horizontal bar of the T). An etch stop layer can be present above the S/D and gate metals. Then an oxide is deposited, windows are open for contacts. Then we performed a CMP.
We now refer to Fig.7. Compared to the previous MOSFET device, the spacer (271) and barrier (272) layers are not provided and the delta doping monolayer (260) is present inside the channel material (250). As was the case for the HEMT devices, the channel material (250) is again in direct contact with the bonding layer(s) (500). To form this structure, we skipped the InAlAs layer which was between the bonding oxide and the channel and we inserted a delta doping at the bottom of the channel. The onset current flows on the top portion of the layer so inserting dopants close to the bonding do not impact too much the mobility because the dopants are restricted on to a bottom region, away from the gate dielectric/channel interface. The rest of the process is analogous to the one described for obtaining the structure of Fig. 6.

Claims

A method for forming a semiconductor structure, comprising:
a. providing a donor substrate (100) having a trench (300) therein and having a plurality of semiconductor layers (200) epitaxially grown on top of one another on the donor substrate (100) in such a way that at least a first of the semiconductor layers (200) is present in the trench (300), wherein the trench (300):
(i) is opening toward a top of the donor substrate (100),

(ii) is defined by a monocrystalline bottom (310) and non-crystalline sidewalls (320), and

(iii) has a width of from 10 nm to 10 µm;

b. providing a carrier substrate (400) comprising:
(i) a semiconductor substrate at a bottom thereof,

(ii) a first semiconductor device on the semiconductor substrate, and

(iii) electrical contacts to the first semiconductor device, at a top of the carrier substrate (400);

c. bonding the donor substrate (100) to the carrier substrate (400) with the top of the donor substrate (100) and the top of the carrier substrate (400) facing each other;

d. removing at least part of said donor substrate (100) in such a way as to expose a semiconductor layer (210) grown on the monocrystalline bottom (310);

e. removing at least part of the semiconductor layer (210) grown on the monocrystalline bottom (310), thereby modifying the plurality of semiconductor layers (200); and

f. optionally forming a second semiconductor device from the modified plurality of semiconductor layers (200),
characterized in that the trench (300) has a depth to width aspect ratio smaller than 1.42:1.
The method according to claim 1, wherein at least one of the plurality of semiconductor layers (200) has a top surface comprising less than 10⁸ threading dislocations per cm².
The method according to claim 2, wherein the semiconductor layer (210) grown on the monocrystalline bottom (310) has a top surface comprising less than 10⁸ threading dislocations per cm².
The method according to any of the previous claims, further comprising a step b', before step c, of providing a bonding layer (500) on top of the donor substrate (100), the carrier substrate (400), or both.
The method according to claim 4, wherein the plurality of semiconductor layers (200) comprises a layer of channel material (250) and wherein step c forms a bonded structure where one of the bonding layers (500) is directly in contact with the layer of channel material (250).
The method according to any of the previous claims, wherein a delta doping monolayer (260) is present within one of the plurality of semiconductor layers (200).
The method according to claim 6, wherein the delta doping monolayer (220) is present away from the centre of the thickness of the layer of channel material (210).
The method according to any one of the preceding claims, wherein step f comprises patterning the plurality of layers to form at least one second semiconductor device.
The method according to any of the previous claims, wherein the first semiconductor device is a complementary metal-oxide-semiconductor device and/or wherein the second semiconductor device is a radio-frequency device.
The method according to any of the previous claims, wherein the second semiconductor device comprises a high-electron-mobility transistor or a metal-oxide-semiconductor field-effect transistor.
The method according to any of the previous claims, wherein, during or after step c, the carrier substrate (400) is kept at temperatures not exceeding 500 °C.
The method according to any one of the preceding claims, wherein, in step a, only the first of the semiconductor layers (200) is present in the trench (300) and wherein, in step e, removing at least part of the semiconductor layer (210) grown on the monocrystalline bottom of the trench consists in removing the whole semiconductor layer (210) grown on the monocrystalline bottom of the trench.
A semiconductor structure, comprising:
a) a carrier substrate (400) comprising:
(i) a semiconductor substrate at a bottom thereof,

(ii) a first semiconductor device on the semiconductor substrate, and

(iii) electrical contacts to the first semiconductor device, at a top of the carrier substrate (400);

b) a donor substrate (100) having a trench (300) therein and having a plurality of semiconductor layers (200) epitaxially grown on top of one another on the donor substrate (100) in such a way that at least a first of the semiconductor layers (200) is present in the trench (300), wherein the trench (300):
(i) is opening toward a top of the donor substrate (100),

(ii) is defined by a monocrystalline bottom (310) and non-crystalline sidewalls (320), and

(iii) has a width of from 10 nm to 10 µm;
wherein the donor substrate (100) is bonded to the carrier substrate (400) with the top of the donor substrate (100) and the top of the carrier substrate (400) facing each other,

characterized in that the trench (300) has a depth to width aspect ratio smaller than 1.42:1.