TWI521706B - 半導體元件、半導體裝置及其製造方法 - Google Patents

半導體元件、半導體裝置及其製造方法 Download PDF

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TWI521706B
TWI521706B TW101128185A TW101128185A TWI521706B TW I521706 B TWI521706 B TW I521706B TW 101128185 A TW101128185 A TW 101128185A TW 101128185 A TW101128185 A TW 101128185A TW I521706 B TWI521706 B TW I521706B
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李宜靜
林佑儒
萬政典
吳政憲
柯誌欣
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台灣積體電路製造股份有限公司
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Description

半導體元件、半導體裝置及其製造方法
本發明係關於半導體製作，且特別是關於一種半導體裝置、元件及其製造方法。
由於各種電子構件(例如電晶體、二極體、電阻、電容等)之整合密度持續改進，半導體積體電路已經歷了迅速成長。最重要部分為，整合密度的改善者要來自最小特徵尺寸(minimum feature size)的持續縮減，其使得於一特定區域內可更整合有更多構件。然而，較小之特徵尺寸可能導致了更多的漏電流(leakage current)情形。隨著近年來更小電子裝置的需求的提升，便需要降低半導體裝置之漏電流情形。
於互補型金氧半導體(CMOS)場效電晶體(FET)中，主動區包括了一汲極(drain)、一源極(source)、連結於上述汲極與源極之間的一通道區(channel region)、以及位於上述通道區上之一閘極(gate)，以控制通道區的開關狀態。當一閘極電壓(gate voltage)超過一臨界電壓(threshold voltage)時，於源極與汲極之間便形成了一導電通道。因此，於源極與汲極之間便允許了電子或電洞的移動。另一方面，當上述閘極電壓係低於臨界電壓時，於理想狀態中，上述通道區為關閉的，於其處並沒有電子或電洞可於汲極與源極之間流通。然而，雖著半導體裝置的持續微縮，由於短通道漏電流(short channel leakage)效應，閘極無法完全地控制 通道區，特別是較遠離閘極之通道區的部份。如此，當半導體裝置縮減至次30奈米(sub-30 nm)之尺寸時，習知之平面型電晶體之對應短閘極通道長度可能導致了閘極無法關閉通道區。
隨著半導體技術的演進，鰭型場效電晶體(FinFET)已提供了一有效選擇，以更降低於半導體裝置內之漏電流。於一場效電晶體中，包括汲極、通道區與源極之一主動區突出此鰭型場效電晶體所在位置之半導體基板的表面。鰭型場效電晶體之主動區，類似一鰭狀物，其剖面情形為一長方形形狀。此外，鰭型場效電晶體之閘極結構沿著三個側面而包覆了主動區，類似倒U形。因此，閘極結構對於通道區的控制變的更強。因而可減少習知平坦型電晶體之短通道漏電效應。如此，於鰭型場效電晶體關閉時，閘極結構可較佳地控制通道區並減少漏電流之情形。
依據一實施例，本發明提供了一種半導體裝置，包括：一第一隔離區，位於一基板內，其中該第一隔離區具有一第一非垂直側壁；一第二隔離區，位於該基板內，其中該第二隔離區具有一第二非垂直側壁；一V形槽，位於該基板內，其中該V形槽、該第一非垂直側壁與該第二非垂直側壁於該基板內形成了一斗蓬形凹口；一斗蓬形主動區，位於該基板上之該斗蓬形凹口之內，其中該斗蓬形主動區具有突出於該第一隔離區與該第二隔離區之一頂面之一上方部，且該斗蓬形主動區包括：一第一源極/汲極區； 一第二源極/汲極區；以及一通道區，連結於該第一源極/汲極區與該第二源極/汲極區之間；以及一閘電極，包覆該斗蓬形主動區之該通道區。
依據另一實施例，本發明提供了一種半導體元件，包括：一第一源極/汲極區，位於一基板內；一第二源極/汲極區，位於該基板內；一通道，連結於該第一源極/汲極區與該第二源極/汲極區之間，其中該第一源極/汲極區、該第二源極/汲極區與該通道形成了一斗蓬形主動區；以及一閘電極，包覆該通道。
依據又一實施例，本發明提供了一種半導體裝置之製造方法，包括：形成一第一隔離區於一基板內；形成一第二隔離區於該基板內；移除該基板之一部，以形成一凹口於該第一隔離區與該第二隔離區之間；於該凹口處施行一表面處理，以形成一斗蓬形凹口；以及使用一磊晶成長，以形成一斗蓬形主動區。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
於下文中藉由不同實施例以解說本發明之具有斗蓬形(cloak-shaped)主動區之一鰭型場效電晶體(FinFET)之解說。然而，本發明亦可應用於各種半導體裝置中。於下文 中，將藉由下述圖式以解說本發明之不同實施例。
第1圖為一剖面圖，繪示了依據本發明之一實施例之具有斗蓬狀主動區之一鰭型場效電晶體。在此，鰭型場效電晶體100係形成於一基板102之上。自剖面觀之，鰭型場效電晶體100包括一斗蓬狀主動區110。尤其是，斗蓬狀主動區110可包括一第一源極/汲極區、一第二源極/汲極區以及連結於第一源極/汲極區與第二源極汲極區(皆未顯示)間之一通道(在此未顯示)。如第1圖所示，斗蓬狀主動區110係位於兩隔離區之間，即隔離區106與隔離區108。依據一實施例，隔離區106與隔離區108皆採用了一淺溝槽隔離(shallow trench isolation，STI)結構。
鰭型場效電晶體100可更包括形成於斗蓬狀主動區110上之一閘電極114。特別地，閘介電層112係形成於斗蓬狀主動區110與閘電極114之間。如第1圖所示，閘介電層112係設置於斗蓬狀主動區110以及隔離區106與隔離區108之上。於下文中將配合第2-9圖以解說鰭型場效電晶體100之製造方法之一實施例。
具有一斗蓬狀主動區110之一較佳元件係於施行一矽鍺磊晶成長製程之前，提供具有適用於後續磊晶成長之潔淨表面之一斗蓬狀凹口(cloak-shaped recess，未顯示，請參照第4圖)。因此，可於斗蓬狀凹口內成長單晶矽鍺磊晶層(single crystalline silicon germanium epitaxial layer)。如此之單晶矽鍺磊晶層有助於改善鰭型場效電晶體100之通道之結晶品質。
第2圖為一剖面圖，繪示了依據本發明之一實施例之 具有數個隔離區之一半導體基板。在此，基板102可為一矽基板。或者，基板102可包括如鍺之其他半導體材料、或如碳化矽、砷化鎵、砷化銦、磷化銦及相似物之化合物半導體材料。依據一實施例，基板102可為一結晶結構。依據另一實施例，基板102可為一絕緣層上覆矽(silicon-on-insulator，SOI)基板。
隔離區106與108係形成於基板102之內。依據一實施例，隔離區106與108係採用淺溝槽隔離結構。此些淺溝槽隔離結構(例如隔離區106)可採用包括微影與蝕刻製程之適當技術所形成。特別地，微影與蝕刻製程可包括沈積如阻劑之常用罩幕材料於基板102上、曝光此罩幕材料以形成一圖案、以及依據上述圖案以蝕刻基板102。依照此方法，可形成複數個開口。此些開口接著為介電材料所填滿，以形成數個淺溝槽隔離結構(例如隔離區106與108)。接著施行一化學機械研磨製程，以移除過量之介電材料，而剩餘部份便形成了此些隔離區106與108。
如第2圖所示，隔離區106與108具有相對之側壁。值得注意的是，於第2圖中僅顯示了分隔之兩隔離區106與108，此些隔離區106與108可為一連續區域之數個部份，而於一實施例中此連續區域可形成一隔離環(isolation ring)。基板102之一上部104係介於隔離區106與108之間並鄰近於隔離區106與108。此上部104之寬度W為小的。依據一實施例，此寬度W約少於50奈米。較佳地，上述尺寸於描述中之僅作為範例之用，且可改變為其他數值。
第3圖為一剖面圖，繪示了依據本發明之一實施例中第2圖所示之基板於移除其一部份後之情形。基板102之上部104之一上方部(請參照第2圖)經過移除而形成一V形槽302。依據一實施例，此V形槽302之底部係高於隔離區106與108之底面。依據另一實施例，V形槽302之底部可大體水平於或低於隔離區106與108之底部。
可採用適當技術移除基板102之上部104之上方部。 特別地，此V形槽302可使用一蝕刻製程所形成。舉例來說，如阻劑罩幕及/或一硬罩幕之一圖案化罩幕(未顯示)可採用沈積與微影技術而形成於隔離區106與108之頂面上。接著，施行如反應性離子蝕刻、其他乾蝕刻、非等向性濕蝕刻或其他適當非等向性蝕刻製程之一蝕刻程序，以形成V形槽302。依據一實施例，可使用如氫氧化四甲基銨(TMAH)之蝕刻化學品，以施行一非等向性濕蝕刻。如此之非等向性濕蝕刻可具有約為3-5%之TMAH濃度。此蝕刻製程可於介於約20-35℃之一溫度下施行。
請參照第3圖，此V形槽302底部具有一內角。依據一實施例，此內角約為100-110度。如第3圖所示之具有V形槽之一優點為如此之V形槽有助於改善後續矽鍺磊晶成長之品質。
第4圖為一剖面圖，繪示了依據本發明之一實施例中第3圖內基板於施行一表面處理後之情形。可施行一表面處理以處理基板102之露出表面，其中上述露出表面係位於V形槽的內部。而上述表面處理可具有一真空環境之一腔體內(未顯示)內施行。此表面處理之製程氣體包括了含 氧氣體以及一蝕刻氣體，上述氣體可同時使用。上述蝕刻氣體具有蝕刻基板102之功能。依據一實施例，含氧氣體包括了氧氣、臭氧及其組合。而蝕刻氣體則可包括含氟氣體，例如CF4。依據一實施例，蝕刻氣體可包括如氟化氫(HCl)之含氯氣體。於此表面處理中，所使用之流率比率，即含氧氣體之流率與含氧氣體流率與蝕刻氣體之總流率之一比率，約介於0.99-0.995。含氧氣體與蝕刻氣體之總壓力約介於500mTorr至1.5 Torr。依據另一實施例，此表面處理可包括一電漿處理，其中電漿之各別射頻功率可介於約1100-1500瓦特。於上述表面處理中，基板102可加熱至介於約150-300℃之一溫度。
基於此表面處理，可改善基板102之表面。可移除形成於基板102之表面上之凹處(pits)與凸處(islands)。此外，如第4圖所示，隔離區(例如隔離區106)之部份側壁於上述表面處理中被移除。因此，形成了一斗蓬形凹口402。如此之斗蓬形凹口有助於改善後續磊晶成長之結晶品質。磊晶成長將參照第5圖而於下文中描述。
此斗蓬狀凹口402可由三個角度所定義形成。如第4圖所示，隔離區106之一側壁為非垂直的。上述側壁偏離於垂直之一角度定義出了一第一角度α。依據一實施例，此第一角度α介於約0-20度。而介於非垂直側壁與V形槽之轉折點處則可定義出一第二角度β。依據一實施例，第二角度β介於約130-160度。此V形槽可定義出一第三角度γ。依據一實施例，第三角度γ具有介於約100-110度之一角度。
於表面處理之後，可於基板102以及隔離區106與108之側壁上施行一潔淨程序(cleaning process)。可採用此潔淨程序以移除表面氧化物(native oxide)，當其形成於基板102之上時。依據一實施例，潔淨程序可施行採用經稀釋之氫氟酸(HF)溶液(diluted HF solution)及/或一高溫氫氣烘焙程序(high temperature H2 bake process)。
第5圖為一剖面圖，繪示了依據本發明之一實施例中第4圖基板於斗蓬狀凹口內成長一磊晶矽鍺層後之情形。可於斗蓬狀凹口402(請參見第4圖)內使用如選擇性磊晶成長(selective epitaxial growth，SEG)之適當技術以成長矽鍺，進而形成一斗蓬狀磊晶區110。於一實施例中，可於上述磊晶成長中臨場地摻雜有如硼之P型摻質或如磷之N型摻質。或者，此磊晶層可採用如離子佈值製程、擴散製程或相似製程之其他製程而摻雜之。如第5圖所示，斗蓬狀磊晶區110之頂面可成長至高於隔離區(例如隔離區106)頂面之一程度。
於一實施例中，斗蓬狀磊晶區110可包括鍺。或者，斗蓬狀磊晶區110可包括矽鍺。可使用CMOS相容磊晶製程以成長此磊晶層。上述CMOS相容磊晶製程可包括化學氣相沈積(CVD)或相似方法。
依照斗蓬狀磊晶區110之期望組成情形，用於磊晶成長之前驅物可包括含矽氣體以及含鍺氣體，例如SiH4、GeH4及或相似物，而含矽氣體以及含鍺氣體的分壓(partial pressure)可經過調整，以調整鍺與矽的原子比。依據一實施例，斗蓬狀磊晶區110之矽鍺可表示為Si1-xGex，其中x 為鍺之原子百分比，且其可介於0-1。依據一實施例，斗蓬狀磊晶區110包括大體純鍺(具有x等於1)。或者，斗蓬狀磊晶區110可具有一低鍺含量。例如，x約介於0.1-0.3。
依據另一實施例，斗蓬狀磊晶區110可包括其他半導體材料，例如碳化矽，大體純矽、如GaN、AlAs、InN、AlN、InxGa(1-x)N、AlxGa(1-x)N、AlxGa(1-x)N、AlxIn(1-x)N、AlxInyGa(1-x-y)N之III-V化合物半導體材料及其組合，其中x與y可介於約0-1。
依據一實施例，斗蓬狀磊晶區110之下部與上部可具有不同成分。舉例來說，斗蓬狀磊晶區110之下部與上部可具有不同之鍺比例。例如，上部可具有高於下部之鍺含量。如此之結構可用於形成一p型鰭型場效電晶體。或者，斗蓬狀磊晶區110之上部可具有低於下部之一鍺含量。如此之結構可用於形成一n型鰭型場效電晶體。
第6圖為一剖面圖，繪示了依據本發明之一實施例中第5圖基板於針對突出之磊晶矽鍺層施行一化學機械研磨製程後之情形。依據矽鍺鰭型場效電晶體之製程，需移除矽鍺磊晶成長之突出部，以形成如第6圖所示之一平坦表面。特別地，可去除如第5圖所示之矽鍺磊晶層之突出部直至矽鍺部的頂面水平於鄰近隔離區(例如隔離區106)之頂面。
上述移除可藉由適當技術所形成，例如研磨、拋光及/或化學蝕刻。依據一實施例，上述移除製程可藉由化學機械研磨製程所施行。於一化學機械研磨製程中，導入蝕刻材料與研磨材料的組合物並使之接觸矽鍺區110之頂面， 並使用研磨墊(未顯示)以研磨去除突出部直至達成一期望之平坦表面。
第7圖為一剖面圖，繪示了依據本發明之一實施例中第6圖基板於移除淺溝槽隔離結構之一上部部份後之情形。鰭型場效電晶體之製程可更包括凹陷隔離區106與108，使得隔離區106與108之頂面低於斗蓬狀磊晶區110之頂面。斗蓬狀磊晶區110高於隔離區106與108之頂面之一部形成了一半導體鰭狀物。
第8圖為一剖面圖，繪示了依據本發明之一實施例中第7圖基板於形成一閘介電層後之情形。閘介電層112可由氧化物材料所形成，且可由如濕式熱氧化或乾式熱氧化之適當氧化製程、濺鍍或藉由採用四乙基矽氧烷(TEOS)與氧氣做為前驅物之化學氣相沈積所形成。此外，閘介電層112可為一高介電常數(high-K)介電材料，例如氧化矽、氮氧化矽、與氧化物、含氮氧化物、氧化鋁、氧化鑭、氧化鉿、氧化鉺、氮氧化鉿、其組合或相似物。
第9圖為一剖面圖，繪示了依據本發明之一實施例中第8圖之基板於形成一閘電極後之情形。閘電極114可包括擇自由包括多晶矽、多晶矽鍺、金屬材料、金屬矽化物材料、金屬氮化物材料、金屬氧化物材料及相似物所組成族群之一導電材料。舉例來說，金屬材料可包括鉭、鈦、鉬、鎢、鉑、鋁、鉿、釕、其組合以及相似物。金屬矽化物材料可包括鈦矽化物、鈷矽化物、鎳矽化物、鉭矽化物、其組合或相似物。金屬氮化物可包括鈦氮化物、鉭氮化物、鎢氮化物、其組合及相似物。金屬氧化物材料可包括氧化 釕、氧化銦錫、其組合及相似物。
值得注意的是，亦可使用其他製程以形成閘電極。上述其他適當製程包括化學氣相沈積(CVD)、物理氣相沈積(PVD)、電漿加強型CVD、大氣壓CVD、高密度電漿CVD、低壓CVD、原子層CVD及相似製程，但非以其為限。
可以理解的是，於閘電極114形成後可能形成一非平坦表面。因此可施行一化學機械研磨製程以平坦化閘電極的頂面。此化學機械研磨製程可參照第6圖所示，故於此並不再次描述。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧鰭型場效電晶體
102‧‧‧基板
104‧‧‧基板之上部
106、108‧‧‧隔離區
110‧‧‧斗蓬狀主動區
112‧‧‧閘介電層
114‧‧‧閘電極
302‧‧‧V形槽
402‧‧‧斗蓬狀凹口
W‧‧‧寬度
A、β、γ‧‧‧角度
第1圖為一剖面圖，繪示了依據本發明之一實施例之具有斗蓬狀主動區之一鰭型場效電晶體；第2圖為一剖面圖，繪示了依據本發明之一實施例之具有數個隔離區之一半導體基板；第3圖為一剖面圖，繪示了依據本發明之一實施例中第2圖之基板於移除其一部份後之情形；第4圖為一剖面圖，繪示了依據本發明之一實施例中第3圖之基板於經過一表面處理後之情形；第5圖為一剖面圖，繪示了依據本發明之一實施例中第4圖之基板於基板凹口之內成長一磊晶矽鍺層後之情形；第6圖為一剖面圖，繪示了依據本發明之一實施例中第5圖之基板於針對磊晶矽鍺層施行一化學機械研磨製程後之情形；第7圖為一剖面圖，繪示了依據本發明之一實施例中第6圖之基板於移除淺溝槽隔離結構之上部部份後之情形；第8圖為一剖面圖，繪示了依據本發明之一實施例中第7圖之基板於形成一閘介電層後之情形；以及第9圖為一剖面圖，繪示了依據本發明之一實施例中第8圖之基板於形成一閘電極後之情形。
100‧‧‧鰭型場效電晶體
102‧‧‧基板
106、108‧‧‧隔離區
110‧‧‧斗蓬狀主動區
112‧‧‧閘介電層
114‧‧‧閘電極

Claims (10)

  1. 一種半導體裝置，包括：一第一隔離區，位於一基板內，其中該第一隔離區具有一第一非垂直側壁；一第二隔離區，位於該基板內，其中該第二隔離區具有一第二非垂直側壁；一V形槽，位於該基板內，其中該V形槽、該第一非垂直側壁與該第二非垂直側壁於該基板內形成了一斗蓬形凹口；一斗蓬形主動區，位於該基板上之該斗蓬形凹口之內，其中該斗蓬形主動區具有突出於該第一隔離區與該第二隔離區之一頂面之一上方部、一第一三角區埋置於該第一隔離區中、以及一第二三角區埋置於該第二隔離區中，且該斗蓬形主動區包括：一第一源極/汲極區；一第二源極/汲極區；以及一通道區，連結於該第一源極/汲極區與該第二源極/汲極區之間；以及一閘電極，包覆該斗蓬形主動區之該通道區。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括：一閘介電層，位於該斗蓬形主動區與該閘電極之間。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該斗蓬形主動區係由矽鍺所形成。
  4. 如申請專利範圍第1項所述之半導體裝置，其中由 該第一非垂直側壁與該V型槽形成了約介於130-160度之一轉折角度，而該V型槽具有介於約100-110度之一內角。
  5. 一種半導體元件，包括：一第一源極/汲極區，位於一基板內；一第二源極/汲極區，位於該基板內；一通道，連結於該第一源極/汲極區與該第二源極/汲極區之間，其中該第一源極/汲極區、該第二源極/汲極區與該通道形成了一斗蓬形主動區，其中該斗蓬形主動區具有一第一三角區埋置於該第一隔離區中，以及一第二三角區埋置於該第二隔離區中；以及一閘電極，包覆該通道。
  6. 如申請專利範圍第5項所述之半導體元件，其中該斗蓬形主動區具有一V形底部。
  7. 如申請專利範圍第5項所述之半導體元件，更包括：一第一隔離區，位於該基板內；一第二隔離區，位於該基板內，其中該第一隔離區與該第二隔離區係形成於該斗蓬形主動區之對稱側；以及一閘介電層，位於該閘電極與該斗蓬形主動區之間。
  8. 如申請專利範圍第5項所述之半導體元件，其中：該第一源極/汲極區係由矽鍺所形成；該第二源極/汲極區係由矽鍺所形成；以及該通道係由矽鍺所形成。
  9. 一種半導體裝置之製造方法，包括：形成一第一隔離區於一基板內；形成一第二隔離區於該基板內； 移除該基板之一部，以形成一凹口於該第一隔離區與該第二隔離區之間；於該凹口處施行一表面處理，以形成一斗蓬形凹口；以及使用一磊晶成長，以形成一斗蓬形主動區，其中該斗蓬形主動區具有一第一三角區埋置於該第一隔離區中，以及一第二三角區埋置於該第二隔離區中。
  10. 如申請專利範圍第9項所述之半導體裝置之製造方法，更包括：形成一矽鍺磊晶區於該斗蓬形凹口內。
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