CN103295988B - 具有集成插槽的系统级封装 - Google Patents

具有集成插槽的系统级封装 Download PDF

Info

Publication number
CN103295988B
CN103295988B CN201210371500.7A CN201210371500A CN103295988B CN 103295988 B CN103295988 B CN 103295988B CN 201210371500 A CN201210371500 A CN 201210371500A CN 103295988 B CN103295988 B CN 103295988B
Authority
CN
China
Prior art keywords
active chip
intermediate layer
slot
chip
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201210371500.7A
Other languages
English (en)
Other versions
CN103295988A (zh
Inventor
赵子群
胡坤忠
桑帕施·K·V·卡里卡兰
雷佐尔·拉赫曼·卡恩
彼得·沃伦坎普
陈向东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of CN103295988A publication Critical patent/CN103295988A/zh
Application granted granted Critical
Publication of CN103295988B publication Critical patent/CN103295988B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/164—Material
    • H01L2924/165—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/164—Material
    • H01L2924/16586—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Connecting Device With Holders (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本文公开了具有集成插槽的系统级封装的各种实施方式。在一种实施方式中，系统级封装包括第一有源芯片，其具有在第一有源芯片的上表面上的第一多个电连接器；中间层，其位于第一有源芯片上方；以及第二有源芯片，其具有在第二有源芯片的下表面上的第二多个电连接器。中间层被配置为选择性将第一多个电连接器中的至少一个耦接至第二多个电连接器中的至少一个。此外，插槽包围第一有源芯片和第二有源芯片以及中间层，该插槽电耦接至第一有源芯片、第二有源芯片和中间层中的至少一个。

Description

具有集成插槽的系统级封装
技术领域
本发明涉及一种具有集成插槽的系统级封装。
背景技术
封装解决方案持续发展以满足受具有更高集成电路密度的电子系统影响的日益严格的设计限制。例如，用于将电源和接地以及输入/输出（I/O）信号提供给单个半导体封装内的多个有源芯片的一种解决方案利用了一个或多个中间层来将有源芯片电耦接至封装基板。
然而，随着趋向更大规模集成系统的趋势通过将越来越多的有源芯片一同封装而继续，例如，这些系统对于由于不充分的散热和/或电磁屏蔽和/或差的信号完整性的性能下降的脆弱性可能变得尖锐。考虑到对通过更先进的系统级封装实施来确保可靠性能的这些及其他挑战，单使用中间层可能不能提供用于容纳形成大规模集成系统的有源芯片中的功率和热量分布的最佳解决方案。
发明内容
本发明提供了一种系统级封装，包括：第一有源芯片，其具有在所述第一有源芯片的上表面上的第一多个电连接器；中间层，其位于所述第一有源芯片上方；第二有源芯片，其具有在所述第二有源芯片的下表面上的第二多个电连接器；所述中间层被配置为选择性将所述第一多个电连接器中的至少一个耦接至所述第二多个电连接器中的至少一个；插槽，其包围所述第一有源芯片和所述第二有源芯片以及所述中间层，所述插槽电耦接至所述第一有源芯片、所述第二有源芯片和所述中间层中的至少一个。
上述系统级封装中，所述中间层包括至少一层选择性导电膜。
上述系统级封装中，所述选择性导电膜包括具有分散于其中的纳米线或纳米管的聚合物基体。
上述系统级封装中，所述插槽被配置为屏蔽所述第一有源芯片、所述第二有源芯片和所述中间层使之免于电磁干扰。
上述系统级封装中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述中间层提供共用封装接地。
上述系统级封装中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述中间层提供散热片。
本发明还提供了一种系统级封装，包括：第一有源芯片，其具有在所述第一有源芯片的上表面上的第一多个电连接器。选择性导电膜，其位于所述第一有源芯片上方；第二有源芯片，其具有在所述第二有源芯片的下表面上的第二多个电连接器；所述选择性导电膜被配置为选择性将所述第一多个电连接器中的至少一个耦接至所述第二多个电连接器中的至少一个；插槽，其包围所述第一有源芯片和所述第二有源芯片以及所述选择性导电膜。
上述系统级封装中，所述插槽电耦接至所述第一有源芯片、所述第二有源芯片和所述选择性导电膜中的至少一个。
上述系统级封装中，所述插槽被配置为屏蔽所述第一有源芯片、所述第二有源芯片和所述选择性导电膜使之免于电磁干扰。
上述系统级封装中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述选择性导电膜提供共用封装接地。
上述系统级封装中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述选择性导电膜提供散热片。
上述系统级封装中，所述选择性导电膜包括具有分布于其中的纳米线或纳米管的聚合物基体。
上述系统级封装中，所述选择性导电膜包括具有分布于其中的导电体的聚合物基体。
上述系统级封装中，所述选择性导电膜包括各向异性导电膜（ACF）。
本发明提供了一种用于制造系统级封装的方法，所述方法包括：配置第一有源芯片，所述第一有源芯片具有在所述第一有源芯片上表面上的第一多个电连接器；将中间层置于所述第一有源芯片上方；将第二有源芯片置于所述中间层上方，所述第二有源芯片具有在所述第二有源芯片的下表面上的第二多个电连接器；利用所述中间层选择性将所述第一多个电连接器中的至少一个耦接至所述第二多个电连接器中的至少一个；将所述第一有源芯片和所述第二有源芯片以及所述中间层密封在插槽中，所述插槽电耦接至所述第一有源芯片、所述第二有源芯片和所述中间层中的至少一个。
上述方法中，所述中间层包括至少一层选择性导电膜。
上述方法中，所述选择性导电膜包括具有分布于其中的纳米线或纳米管的聚合物基体。
上述方法中，所述插槽被配置为屏蔽所述第一有源芯片、所述第二有源芯片和所述中间层使之免于电磁干扰。
上述方法中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述中间层提供共用封装接地。
上述方法中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述中间层提供散热片。
附图说明
本公开针对具有集成插槽的系统级封装，结合至少一个附图充分示出和/或描述了该系统级封装，并在权利要求中更完整地做了叙述。
图1示出了具有集成插槽的系统级封装的一种实施的截面图。
图2示出了具有集成插槽的系统级封装的另一实施的截面图。
图3示出了给出一种用于制造具有集成插槽的系统级封装的示例性方法的流程图。
具体实施方式
以下描述包括关于本公开中的实施方式的具体信息。本领域技术人员将认识到，本公开可以不同于本文具体讨论的方法来实施。本申请中的附图及其所附详细描述仅针对示例性实施。除非指出，否则图中相似或相应的元件可由相似或相应的附图标记来表示。此外，本申请中的附图和图示一般不成比例，且并非旨在符合实际的相对尺寸。
图1示出了具有集成插槽的系统级封装的一种实施的截面图。如图1所示，系统级封装100包括第一有源芯片110、第二有源芯片120以及包括中介层电介质132和穿过中间层的连接134a和134b的中间层130，其全部被包括插槽接触162的插槽160包围。此外，系统级封装100包括用于将第二有源芯片粘附至插槽160内表面的粘附层164、包括将第一有源芯片110的上表面111粘附至中间层130的微凸块112a和112b的微凸块112、包括将第二有源芯片120的下表面121粘附至中间层130的微凸块122a和122b的微凸块122。图1中还示出了将系统级封装110电连接至基板102的焊球104，基板102可以是例如封装基板或印刷电路板。
需要注意，尽管仅一个焊球104被图1中的附图标记具体指出，但任何或全部所示的将系统级封装100连接至基板102的焊球均可被表征或称作焊球104。此外，尽管各微凸块112和微凸块122中仅一个被这样明确标注，但示出在第一有源芯片110上表面111上的任何或全部微凸块（包括微凸块112a和112b）均可被表征或称作微凸块112，同时，示出在第二有源芯片120下表面121上的任何或全部微凸块（包括微凸块122a和122b）均可被表征或称作微凸块122。
如图1所示，第一有源芯片110具有在第一有源芯片110上表面111上的微凸块112形式的电连接器。再如图1所示，中间层130位于第一有源芯片110和微凸块122上。此外，根据图1所示的实施方式，包括在第二有源芯片120的下表面121上的微凸块122形式的电连接器的第二有源芯片120被示出在中间层130之上。需要注意，如图1所示，中间层130被配置为将至少一个微凸块112选择性耦接至至少一个微凸块122。换言之，根据本实施，中间层130被配置为提供穿过中间层的连接134a用于选择性将第一有源芯片110上表面111上的微凸块112a耦接至第二有源芯片120下表面121上的微凸块122a，以及通过选择性提供穿过中间层的连接134b来选择性将微凸块112b连接至微凸块122b。如图1所示，根据一种实施方式，插槽160包围第一有源芯片110、第二有源芯片120和中间层130，并由插槽接触162电连接至中间层130。
插槽160可以是导电和导热的插槽，且可以由例如金属或合金（诸如铜或铜合金）制成。可选地，插槽160可由非金属材料（诸如塑料或模塑料）制成，但却具有电布线和/或一个或多个在其中形成的接地面来通过插槽接触162提供电连接。在一种实施方式中，例如，插槽160可被配置为屏蔽第一有源芯片110、第二有源芯片120和中间层130使之免于电磁干扰和/或被配置为向包括第一有源芯片110、第二有源芯片120和中间层130的系统级封装100提供共用封装接地。此外，在一些实施方式中，插槽160可被配置为向第一有源芯片110、第二有源芯片120和中间层130提供散热片，以能够增强系统级封装100的热耗散。在又一实施方式中，插槽160可被配置为向系统级封装100提供增强的环境保护，诸如潮湿保护。
例如，第一有源芯片110和第二有源芯片120可以是封装或未封装的芯片。如图1所示，第二有源芯片120由粘附层164粘附至插槽160内表面，粘附层164也可被实施为用作热分流器，以使得将插槽160有效用作第二有源芯片120的散热片。粘附层164可以是例如芯片粘结膜（DAF），或任何适当的导热粘结材料。需要注意，尽管图1所示实施描述了系统级封装100具有两个由插槽160包围并由中间层130电耦接在一起的有源芯片，例如第一有源芯片110和第二有源芯片120，但在一种实施中，除第一有源芯片110和第二有源芯片120之外的几个或甚至许多有源芯片可由一个或多个中间层（诸如中间层130）电耦接在一起，并被插槽160包围以根据本发明原理形成系统级封装。
如上所述，中间层130包括中间层电介质132和形成在中间层电介质中的穿过中间层的连接134a和134b。例如，中间层电介质132可由刚性介电材料（诸如纤维强化双马来酰亚胺三嗪（BT）、FR-4、玻璃或陶瓷）形成。可选择地，中间层电介质132可由环氧酚或氰酸盐环氧酯构建材料形成。作为一个具体实例，在一种实施中，中间层电介质132可由AjinomotoTM构建材料（ABF）形成。根据该示例性实施方式，可在用于形成中间层电介质132的构建期间，使用本领域内已知的任何合适技术来形成穿过中间层的连接134a和134b。
在又一实施方式中，中间层130可包括至少一个选择性导电膜。例如，如图1具体所示，中间层电介质132可以是由聚酰亚胺膜或其它适当聚合物基体形成的柔性电介质，其具有用于选择性提供穿过中间层的连接（诸如穿过中间层的连接134a和134b）的分布于其中的导电体。作为一个具体实例，在一种实施方式中，中间层130可由B级聚合物膜形成，其用作中间层电介质132且具有分布于其中的导电体（诸如导电纳米线或导电纳米管）。在一些实施方式中，该导电体可大致均匀分布在中间层电介质132中，并使它们的主轴（例如，纳米线或纳米管的长轴）方向大致平行于中间层130的平面。在这种实施方式中，外部场（诸如外部电磁场）例如可被施加在中间层电介质132上，以选择性将分布于其中的一些导电体重定向，从而形成穿过中间层的连接134a和134b。当形成选择性导电膜时，例如，中间层130随后可经过固化处理（诸如紫外线（UV）固化或其他辐射固化）来永久建立穿过中间层的连接134a和134b。
根据图1所示实施方式，第一有源芯片110和第二有源芯片120分别通过微凸块112和122电连接至中间层130。然而，需要注意，更一般地，微凸块112和122可相当于任何适于将第一有源芯片110和第二有源芯片120耦接至中间层130的电连接器。因此，在其他实施方式中，微凸块112和/或122可相当于导电柱或导电杆，例如，诸如由铜形成的金属柱或金属杆。此外，在其他实施方式中，焊球104可相当于任何适于在系统级封装100与基板102之间形成稳定电连接的导电体。
现转向图2，图2示出了具有集成插槽的系统级封装的另一实施的截面图。如图2所示，系统级封装200包括第一有源芯片210、第二有源芯片220、包括中间层电介质232和穿过中间层的连接234a和234b的第一中间层230、第三有源芯片240以及包括中间层电介质252和穿过中间层的连接254c和254d的第二中间层250，其全部被包括插槽接触262的插槽260包围。需要注意，尽管对应于附图标记210、220和240的特征当前被表征为相应的有源芯片，但在其他实施方式中，一个或多个这些特征可以是有源封装。换言之，在各种实施方式中，由附图标记210、220和240表示的特征可对应于有源芯片、有源封装或任何有源芯片和有源封装的组合。
再如图2所述，系统级封装200包括将第三有源芯片240粘附于插槽260内表面的粘附层264、包括将第一有源芯片210的上表面211耦接至第一中间层230的微凸块212a和212b的微凸块212、包括将第二有源芯片220的下表面221耦接至第一中间层230的微凸块222a和222b的微凸块222、包括将第二有源芯片220的上表面223耦接至第二中间层250的微凸块225c和225d的微凸块225、以及包括将第三有源芯片240的下表面241耦接至第二中间层250的微凸块242c和242d的微凸块242。图2还示出了将系统级封装200电连接至基板202的焊球204。
第一有源芯片210、第二有源芯片220、包括穿过中间层的连接234a和234b的第一中间层230、粘附层264、微凸块212和222、焊球204和基板202分别对应于图1中的第一有源芯片110、第二有源芯片120、包括穿过中间层的连接134a和134b的中间层130、粘附层164、微凸块112和122、焊球104和基板102，且可共享属于这些上述相应特征的特性。此外，包括插槽接触262的插槽260大体上对应于图1中的插槽160。然而，根据图2所示实施方式，插槽260通过插槽接触262电耦接至第一有源芯片210、第二有源芯片220和第三有源芯片240中的每一个。
需要注意，尽管仅一个微凸块225和一个微凸块242被图2中这些相应附图标记具体标出，但示出在第二有源芯片220上表面223上的任何或全部微凸块（包括微凸块225c和225d）以及示出在第三有源芯片240下表面241上的任何或全部微凸块（包括微凸块242c和242d）均可被表征或称作相应的微凸块225和242。还需要注意，尽管图2所示实施方式示出系统级封装200包括三个有源芯片和两个被插槽260包围的中间层（例如，第一有源芯片210、第二有源芯片220、第三有源芯片240、第一中间层230和第二中间层250），但在其他实施方式中，例如，系统级封装200可包括许多有源芯片，诸如五十个有源芯片或一百个有源芯片，其使用任何适当数量和类型的中间层相互连接。
如图2所示，第二有源芯片220具有在第二有源芯片220上表面223上的微凸块225形式的电连接器，同时，第三有源芯片240具有在第三有源芯片240的下表面241上的微凸块242形式的电连接器。再如图2所示，第二中间层250与第一中间层230类似，可包括例如位于第二有源芯片220与第三有源芯片240之间的至少一层选择性导电膜。
图2还示出了被配置为将至少一个微凸块225选择性耦接至至少一个微凸块242的第二中间层250。换言之，第二中间层250被配置为提供穿过中间层的连接254c来将第二有源芯片220上表面223上的微凸块225c选择性耦接至第三有源芯片240下表面241上的微凸块242c，以及通过提供穿过中间层的连接254d来将微凸块225d选择性耦接至微凸块242d。
第二中间层250包括中间层电介质252和建立在中间层电介质252中的穿过中间层的连接254c和254d。与图1中的中间层电介质132类似，中间层电介质252可由刚性介电材料形成，诸如BT、FR-4、玻璃或陶瓷，例如，或者可由ABFTM形成。此外，在一些实施方式中，中间层电介质252可被形成在半导体中间层基板（诸如硅基板）上（中间层基板未在图2中示出）。
在一种实施方式中，第二中间层250可包括至少一层选择性导电膜。在这些实施方式中，中间层电介质252可以是由例如聚合物基体（诸如B级聚合物膜）形成的具有分布于其中的诸如导电纳米线或导电纳米管的导电体的柔性电介质，以选择性提供穿过中间层的连接254c和254d，如以上参照图1的中间层130中的选择性导电膜的使用所述。在一些实施方式中，第二中间层250可由各向异性导电膜（ACF）形成。在一些实施方式中，例如，ACF内导电体的分布可被规划为在确保其他地方电介质完整的同时，在对应于图2中的穿过中间层的连接254c和254d的中间层电介质252内期望位置处提供穿过中间层的连接。
继续至图3，图3示出了流程图300，其描述了一种用于制造具有集成插槽的系统级封装的示例性方法。对于图3中略述的方法，需要注意，为不混淆本申请中对发明特征的讨论，流程图300省略了某些细节和特征。
参照流程图300并另外参照图1的系统级封装100，当具有在上表面111上的微凸块112形式的电连接器的第一有源芯片110被配置为封装在系统级封装100内部时，流程图300开始（310）。流程图300以将中间层130置于第一有源芯片110上表面111上而继续（320）。如上所讨论，中间层130包括中间层电介质132，其可以是由聚酰亚胺膜或其他适当聚合物基体形成的柔性电介质，该柔性电介质具有分布于其中的用于选择性提供穿过中间层的连接的导电体。在一种实施方式中，中间层130可由ACF形成，例如，其中，ACF内的导电体分布被规划为在中间层130内的期望位置处选择性提供穿过中间层的连接，例如，穿过中间层的连接134a和134b。
当包括在下表面121上的微凸块122形式的电连接器的第二有源芯片120被置于中间层130上时，流程图300继续（330）。根据流程图300，中间层130随后被用于选择性将至少一个微凸块112耦接至至少一个微凸块122（340）。例如，在一些实施方式中，中间层130可包括B级聚合物中间层电介质132，其具有分布于其中的导电纳米线或导电纳米管。如上所述，导电纳米线或导电纳米管可大致均匀分布在中间层电介质132中，并使它们的主轴（例如，纳米线或纳米管的长轴）方向大致平行于中间层130的平面。外部场（诸如外部电磁场）例如可被施加在中间层电介质132上来选择性将分布于其中的一些导电纳米线或导电纳米管重定向，从而选择性形成能将第一有源芯片110上表面111上的相应微凸块112a和112b耦接至第二有源芯片120下表面121上的相应微凸块122a和122b的穿过中间层的连接134a和134b。例如，中间层电介质132随后可经过固化处理（诸如UV固化或其他辐射固化），以在中间层130内永久建立穿过中间层的连接134a和134b。
参照图1中的穿过中间层的连接134a和134b以及图2中的穿过中间层的连接234a、234b、254c和254d，需要注意，可选择性确定电容量（例如，电流承载能力）以及在其相应中间层电介质内的那些穿过中间层的连接的位置。例如可被实施为提供高功率连接的穿过中间层的连接134a和234a，例如被示出为大致宽于可被配置为传递低功率的芯片到芯片的信号的穿过中间层的连接134b、234b和254c。此外，根据图1和图2所示实施方式，穿过中间层的连接254d可被实施为支持第二有源芯片220与第三有源芯片240之间的中间功率通信。
再一同参照图1和图3，流程图300通过用插槽160密封第一有源芯片110、第二有源芯片120和中间层130以及将插槽160电耦接至至少一个第一有源芯片110、第二有源芯片120和中间层130来结束（350）。在图1的实施方式中，插槽160被插槽接触162电耦接至中间层130。可选择地，根据图2所示的实施方式，插槽260被插槽接触262电耦接至第一有源芯片210和第二有源芯片220以及第三有源芯片240。
因此，如上所述，在一种实施方式中，插槽160/260可被配置为有利地屏蔽第一有源芯片110/210、第二有源芯片120/220和中间层130/230以及第三有源芯片240和第二中间层150使之免于电磁干扰。此外，在一些实施方式中，插槽160/260可被配置为向系统级封装100/200提供共用封装接地。此外，在一些实施方式中，插槽160/260可被配置为有利地提供能增强对于第一有源芯片110/210、第二有源芯片120/220和中间层130/230以及第三有源芯片240和第二中间层250的热耗散的散热片。在又一实施方式中，插槽160/260可被配置为向系统级封装100/200提供增强的环境保护，诸如潮湿保护。
根据以上描述，显然在不背离本发明的概念的范围的前提下，各种技术可被用于实施本申请中所述的概念。此外，尽管已具体参照某些实施方式描述了这一概念，但本领域普通技术人员将认识到，在不背离这些概念的思想和范围的前提下，可在形式和细节上进行更改。因此，所述实施方式应被理解为在所示出的所有方面内且并非限定。还应理解，本申请不限于本文所述的具体实施方式，而是在不背离本公开的范围的前提下，许多重排、修改和替代也是可行的。

Claims (7)

1.一种系统级封装，包括：
第一有源芯片，其具有在所述第一有源芯片的上表面上的第一多个互不连接的电连接器；
中间层，其位于所述第一有源芯片上方；
第二有源芯片，其具有在所述第二有源芯片的下表面上的第二多个互不连接的电连接器；
所述中间层被配置为选择性将所述第一多个互不连接的电连接器中的至少一个耦接至所述第二多个互不连接的电连接器中的至少一个；插槽，其包围所述第一有源芯片和所述第二有源芯片以及所述中间层，所述插槽电耦接至所述第一有源芯片、所述第二有源芯片和所述中间层中的至少一个；其中，所述插槽是导电和导热的插槽，其被配置为屏蔽所述第一有源芯片、所述第二有源芯片和所述中间层使之免于电磁干扰，以及
插槽接触，电耦接在所述插槽与所述第一有源芯片、所述第二有源芯片或所述中间层中的至少一个中间。
2.根据权利要求1所述的系统级封装，其中，所述中间层包括至少一层选择性导电膜。
3.根据权利要求2所述的系统级封装，其中，所述选择性导电膜包括具有分散于其中的纳米线或纳米管的聚合物基体。
4.根据权利要求1所述的系统级封装，其中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述中间层提供共用封装接地。
5.根据权利要求1所述的系统级封装，其中，所述插槽被配置为向所述第一有源芯片、所述第二有源芯片和所述中间层提供散热片。
6.一种系统级封装，包括：
第一有源芯片，其具有在所述第一有源芯片的上表面上的第一多个电连接器；
选择性导电膜，其位于所述第一有源芯片上方；
第二有源芯片，其具有在所述第二有源芯片的下表面上的第二多个电连接器；
所述选择性导电膜被配置为选择性将所述第一多个电连接器中的至少一个耦接至所述第二多个电连接器中的至少一个；
插槽，其包围所述第一有源芯片和所述第二有源芯片以及所述选择性导电膜；其中，所述插槽是导电和导热的插槽，其被配置为屏蔽所述第一有源芯片、所述第二有源芯片和所述选择性导电膜使之免于电磁干扰，以及
插槽接触，电耦接在所述插槽与所述第一有源芯片、所述第二有源芯片或所述选择性导电膜中的至少一个中间。
7.一种用于制造系统级封装的方法，所述方法包括：
配置第一有源芯片，所述第一有源芯片具有在所述第一有源芯片上表面上的第一多个电连接器；
将中间层置于所述第一有源芯片上方；
将第二有源芯片置于所述中间层上方，所述第二有源芯片具有在所述第二有源芯片的下表面上的第二多个电连接器；
利用所述中间层选择性将所述第一多个电连接器中的至少一个耦接至所述第二多个电连接器中的至少一个；
将所述第一有源芯片和所述第二有源芯片以及所述中间层密封在插槽中，所述插槽电耦接至所述第一有源芯片、所述第二有源芯片和所述中间层中的至少一个；其中，所述插槽是导电和导热的插槽，其被配置为屏蔽所述第一有源芯片、所述第二有源芯片和所述中间层使之免于电磁干扰，以及
形成插槽接触，所述插槽接触电耦接在所述插槽与所述第一有源芯片、所述第二有源芯片或所述中间层中的至少一个中间。
CN201210371500.7A 2012-02-24 2012-09-28 具有集成插槽的系统级封装 Expired - Fee Related CN103295988B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/405,207 US9275976B2 (en) 2012-02-24 2012-02-24 System-in-package with integrated socket
US13/405,207 2012-02-24

Publications (2)

Publication Number Publication Date
CN103295988A CN103295988A (zh) 2013-09-11
CN103295988B true CN103295988B (zh) 2016-12-21

Family

ID=47262940

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2012205062547U Expired - Fee Related CN203205406U (zh) 2012-02-24 2012-09-28 具有集成插槽的系统级封装件
CN201210371500.7A Expired - Fee Related CN103295988B (zh) 2012-02-24 2012-09-28 具有集成插槽的系统级封装

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2012205062547U Expired - Fee Related CN203205406U (zh) 2012-02-24 2012-09-28 具有集成插槽的系统级封装件

Country Status (5)

Country Link
US (1) US9275976B2 (zh)
EP (1) EP2631943B1 (zh)
KR (1) KR101362819B1 (zh)
CN (2) CN203205406U (zh)
TW (1) TWI493636B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130082365A1 (en) 2011-10-03 2013-04-04 International Business Machines Corporation Interposer for ESD, EMI, and EMC
US9275976B2 (en) 2012-02-24 2016-03-01 Broadcom Corporation System-in-package with integrated socket
KR102210332B1 (ko) 2014-09-05 2021-02-01 삼성전자주식회사 반도체 패키지
WO2016174899A1 (ja) * 2015-04-27 2016-11-03 富士電機株式会社 半導体装置
US10178786B2 (en) 2015-05-04 2019-01-08 Honeywell International Inc. Circuit packages including modules that include at least one integrated circuit
US9741644B2 (en) 2015-05-04 2017-08-22 Honeywell International Inc. Stacking arrangement for integration of multiple integrated circuits
CN205542769U (zh) 2015-11-30 2016-08-31 奥特斯(中国)有限公司 电子装置和电子设备
DE112015007196T5 (de) * 2015-12-18 2018-08-23 Intel IP Corporation Interposer mit an den seitenwänden freigelegtem leitfähigem routing
US10062634B2 (en) 2016-12-21 2018-08-28 Micron Technology, Inc. Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology
US10475771B2 (en) * 2018-01-24 2019-11-12 Micron Technology, Inc. Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods
CN108633170B (zh) * 2018-06-25 2020-01-10 维沃移动通信有限公司 一种印刷电路板组件及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
CN101390207A (zh) * 2006-02-23 2009-03-18 索尼化学&信息部件株式会社 安装方法
CN203205406U (zh) * 2012-02-24 2013-09-18 美国博通公司 具有集成插槽的系统级封装件

Family Cites Families (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198963A (en) 1991-11-21 1993-03-30 Motorola, Inc. Multiple integrated circuit module which simplifies handling and testing
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
TW411037U (en) 1999-06-11 2000-11-01 Ind Tech Res Inst Integrated circuit packaging structure with dual directions of thermal conduction path
JP2001203318A (ja) 1999-12-17 2001-07-27 Texas Instr Inc <Ti> 複数のフリップチップを備えた半導体アセンブリ
JP3597754B2 (ja) 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
WO2002027786A1 (fr) 2000-09-25 2002-04-04 Ibiden Co., Ltd. Element semi-conducteur, procede de fabrication d'un element semi-conducteur, carte a circuit imprime multicouche, et procede de fabrication d'une carte a circuit imprime multicouche
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
JP4422323B2 (ja) * 2000-12-15 2010-02-24 株式会社ルネサステクノロジ 半導体装置
US6525407B1 (en) 2001-06-29 2003-02-25 Novellus Systems, Inc. Integrated circuit package
JP4595265B2 (ja) 2001-08-13 2010-12-08 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
JP4254248B2 (ja) * 2002-04-05 2009-04-15 株式会社村田製作所 電子装置
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
JP2004079701A (ja) 2002-08-14 2004-03-11 Sony Corp 半導体装置及びその製造方法
TWI278048B (en) 2003-11-10 2007-04-01 Casio Computer Co Ltd Semiconductor device and its manufacturing method
TWI245388B (en) 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
TWI269423B (en) 2005-02-02 2006-12-21 Phoenix Prec Technology Corp Substrate assembly with direct electrical connection as a semiconductor package
TWI264094B (en) 2005-02-22 2006-10-11 Phoenix Prec Technology Corp Package structure with chip embedded in substrate
US7326592B2 (en) 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
US7208345B2 (en) 2005-05-11 2007-04-24 Infineon Technologies Ag Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device
US20070065984A1 (en) * 2005-09-22 2007-03-22 Lau Daniel K Thermal enhanced package for block mold assembly
US7585702B1 (en) 2005-11-08 2009-09-08 Altera Corporation Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate
US7981726B2 (en) 2005-12-12 2011-07-19 Intel Corporation Copper plating connection for multi-die stack in substrate package
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
FR2901636A1 (fr) 2006-05-24 2007-11-30 Commissariat Energie Atomique Connecteur a vias isoles
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
DE102006032251A1 (de) 2006-07-12 2008-01-17 Infineon Technologies Ag Verfahren zum Herstellen von Chip-Packages sowie derartig hergestelltes Chip-Package
US7473577B2 (en) 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
KR100813625B1 (ko) * 2006-11-15 2008-03-14 삼성전자주식회사 반도체 소자 패키지
KR100840788B1 (ko) 2006-12-05 2008-06-23 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
JP4926692B2 (ja) 2006-12-27 2012-05-09 新光電気工業株式会社 配線基板及びその製造方法と半導体装置
US20080157322A1 (en) 2006-12-27 2008-07-03 Jia Miao Tang Double side stacked die package
JP2008166373A (ja) 2006-12-27 2008-07-17 Nec Electronics Corp 半導体装置およびその製造方法
US7675163B2 (en) 2007-03-21 2010-03-09 Sun Microsystems, Inc. Carbon nanotubes for active direct and indirect cooling of electronics device
DE102007019552B4 (de) 2007-04-25 2009-12-17 Infineon Technologies Ag Verfahren zur Herstellung eines Substrats mit Durchführung sowie Substrat und Halbleitermodul mit Durchführung
KR100923562B1 (ko) 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US8476735B2 (en) * 2007-05-29 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Programmable semiconductor interposer for electronic package and method of forming
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
EP2186134A2 (en) 2007-07-27 2010-05-19 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
KR101348748B1 (ko) 2007-08-24 2014-01-08 삼성전자주식회사 재배선 기판을 이용한 반도체 패키지 제조방법
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
US7618849B2 (en) 2007-10-22 2009-11-17 Broadcom Corporation Integrated circuit package with etched leadframe for package-on-package interconnects
KR100891537B1 (ko) * 2007-12-13 2009-04-03 주식회사 하이닉스반도체 반도체 패키지용 기판 및 이를 갖는 반도체 패키지
US8030136B2 (en) 2008-05-15 2011-10-04 Stats Chippac, Ltd. Semiconductor device and method of conforming conductive vias between insulating layers in saw streets
US8350377B2 (en) 2008-09-25 2013-01-08 Wen-Kun Yang Semiconductor device package structure and method for the same
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US20100133534A1 (en) * 2008-12-03 2010-06-03 Byung Tai Do Integrated circuit packaging system with interposer and flip chip and method of manufacture thereof
US8222718B2 (en) * 2009-02-05 2012-07-17 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same
US8008125B2 (en) 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US8916958B2 (en) * 2009-04-24 2014-12-23 Infineon Technologies Ag Semiconductor package with multiple chips and substrate in metal cap
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
KR101086972B1 (ko) 2009-10-01 2011-11-29 앰코 테크놀로지 코리아 주식회사 관통전극을 갖는 웨이퍼 레벨 패키지 및 그 제조 방법
US20110241185A1 (en) 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration
US8455995B2 (en) 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
KR101680082B1 (ko) 2010-05-07 2016-11-29 삼성전자 주식회사 웨이퍼 레벨 패키지 및 웨이퍼 레벨 패키지의 형성방법
US8674513B2 (en) 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
KR101855294B1 (ko) 2010-06-10 2018-05-08 삼성전자주식회사 반도체 패키지
WO2012003568A1 (en) * 2010-07-05 2012-01-12 Mosaid Technologies Incorporated Multi-chip package with thermal frame and method of assembling
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8299608B2 (en) 2010-07-08 2012-10-30 International Business Machines Corporation Enhanced thermal management of 3-D stacked die packaging
US8796842B2 (en) * 2010-08-20 2014-08-05 Ati Technologies Ulc Stacked semiconductor chip device with thermal management circuit board
US9385055B2 (en) * 2010-08-20 2016-07-05 Ati Technologies Ulc Stacked semiconductor chips with thermal management
TWI398943B (zh) 2010-08-25 2013-06-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
TWI416679B (zh) * 2010-12-06 2013-11-21 Ind Tech Res Inst 半導體結構及其製造方法
US8299371B2 (en) 2010-12-20 2012-10-30 Endicott Interconnect Technologies, Inc. Circuitized substrate with dielectric interposer assembly and method
US8617987B2 (en) 2010-12-30 2013-12-31 Stmicroelectronics Pte Ltd. Through hole via filling using electroless plating
KR101817159B1 (ko) 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US9064781B2 (en) 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8535981B2 (en) 2011-03-10 2013-09-17 Stats Chippac Ltd. Integrated circuit package-on-package system with underfilling structures and method of manufacture thereof
US8779562B2 (en) 2011-03-24 2014-07-15 Stats Chippac Ltd. Integrated circuit packaging system with interposer shield and method of manufacture thereof
TWI506738B (zh) 2011-06-09 2015-11-01 Unimicron Technology Corp 封裝結構及其製法
US20120319293A1 (en) 2011-06-17 2012-12-20 Bok Eng Cheah Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package
US20130000968A1 (en) 2011-06-30 2013-01-03 Broadcom Corporation 1-Layer Interposer Substrate With Through-Substrate Posts
US9013037B2 (en) 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
US8587123B2 (en) 2011-09-27 2013-11-19 Broadcom Corporation Multi-chip and multi-substrate reconstitution based packaging
US8659126B2 (en) 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US8922013B2 (en) 2011-11-08 2014-12-30 Stmicroelectronics Pte Ltd. Through via package
US8749072B2 (en) * 2012-02-24 2014-06-10 Broadcom Corporation Semiconductor package with integrated selectively conductive film interposer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
CN101390207A (zh) * 2006-02-23 2009-03-18 索尼化学&信息部件株式会社 安装方法
CN203205406U (zh) * 2012-02-24 2013-09-18 美国博通公司 具有集成插槽的系统级封装件

Also Published As

Publication number Publication date
US20130221500A1 (en) 2013-08-29
KR20130097626A (ko) 2013-09-03
EP2631943A3 (en) 2014-01-22
CN203205406U (zh) 2013-09-18
TWI493636B (zh) 2015-07-21
KR101362819B1 (ko) 2014-02-13
EP2631943A2 (en) 2013-08-28
TW201336003A (zh) 2013-09-01
CN103295988A (zh) 2013-09-11
US9275976B2 (en) 2016-03-01
EP2631943B1 (en) 2020-05-27

Similar Documents

Publication Publication Date Title
CN103295988B (zh) 具有集成插槽的系统级封装
CN105655310B (zh) 封装结构、电子设备及封装方法
CN100524951C (zh) 连接部件和安装体及其制造方法
CN107408547A (zh) 扇出型系统级封装件及其形成方法
CN103688353B (zh) 微电子器件、层叠管芯封装及包含层叠管芯封装的计算系统、制造层叠管芯封装中的多通道通信路径的方法以及实现层叠管芯封装的部件之间的电通信的方法
US10595414B2 (en) Component carrier and manufacturing method
CN107732651A (zh) 光发射器封装件
CN106169466A (zh) 半导体封装组件及其制造方法
CN106057788A (zh) 具有中介层的半导体封装及其制造方法
CN103985695B (zh) 一种扇出型封装结构及其制作工艺
KR20160014475A (ko) 스택 패키지
CN105321926A (zh) 封装装置及其制作方法
CN106409780A (zh) 电子封装件及其制法
CN107622983A (zh) 半导体封装装置及其制造方法
KR20150035251A (ko) 외부접속단자부와 외부접속단자부를 갖는 반도체 패키지 및 그들의 제조방법
CN107431065B (zh) 堆叠式封装配置及其制造方法
CN110581104A (zh) 容置在部件承载件中的阶梯式腔内的阶梯式部件组件
CN103227164A (zh) 半导体封装构造及其制造方法
CN102800598A (zh) 埋置有源元件的基板及埋置方法
CN112928028A (zh) 一种具有嵌入式线路的板级芯片封装方法及其封装结构
CN107845610A (zh) 基板结构及其制作方法
CN103474363B (zh) 一种基于有机基板技术的封装工艺及封装结构
CN105390477B (zh) 一种多芯片3d二次封装半导体器件及其封装方法
CN104218034A (zh) 半导体封装
CN203491244U (zh) 一种封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1185717

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170306

Address after: Singapore Singapore

Patentee after: Avago Technologies Fiber IP Singapore Pte. Ltd.

Address before: American California

Patentee before: Zyray Wireless Inc.

TR01 Transfer of patent right

Effective date of registration: 20181022

Address after: Singapore Singapore

Patentee after: Annwa high tech Limited by Share Ltd

Address before: Singapore Singapore

Patentee before: Avago Technologies Fiber IP Singapore Pte. Ltd.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20161221

Termination date: 20180928

CF01 Termination of patent right due to non-payment of annual fee
REG Reference to a national code

Ref country code: HK

Ref legal event code: WD

Ref document number: 1185717

Country of ref document: HK