CN103199019A - 具有垂直鳍状件的鳍式场效应晶体管及其形成方法 - Google Patents
具有垂直鳍状件的鳍式场效应晶体管及其形成方法 Download PDFInfo
- Publication number
- CN103199019A CN103199019A CN2012101937633A CN201210193763A CN103199019A CN 103199019 A CN103199019 A CN 103199019A CN 2012101937633 A CN2012101937633 A CN 2012101937633A CN 201210193763 A CN201210193763 A CN 201210193763A CN 103199019 A CN103199019 A CN 103199019A
- Authority
- CN
- China
- Prior art keywords
- silicon substrate
- groove
- silicon
- semiconductor bar
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 171
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 171
- 239000010703 silicon Substances 0.000 claims abstract description 171
- 239000000758 substrate Substances 0.000 claims abstract description 141
- 239000004065 semiconductor Substances 0.000 claims abstract description 106
- 238000002955 isolation Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 21
- 230000012010 growth Effects 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 11
- 150000001875 compounds Chemical class 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 238000000407 epitaxy Methods 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 28
- 238000000576 coating method Methods 0.000 description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910017115 AlSb Inorganic materials 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- -1 InAlAs Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
在形成器件的方法中,蚀刻(110)硅衬底以在(110)硅衬底中形成第一沟槽,其中,位于第一沟槽之间的(110)硅衬底的剩余部分形成硅条。硅条的侧壁具有(111)表面方向。用电介质材料填充第一沟槽以形成浅沟槽隔离(STI)区域。去除硅条以形成位于STI区域之间的第二沟槽。实施外延以在第二沟槽中生长半导体条。对STI区域的顶部部分开槽,位于STI区域的被去除顶部部分之间的半导体条的顶部部分以形成半导体鳍状件。本发明还公开了具有垂直鳍状件的鳍式场效应晶体管及其形成方法。
Description
技术领域
本发明涉及涉及半导体技术领域,更具体地,涉及具有垂直鳍状件的鳍式场效应晶体管及其形成方法。
背景技术
随着集成电路的尺寸逐渐减小以及更多的对集成电路的速度的要求,晶体管需要在尺寸逐渐更小的同时具有更高的驱动电流。因此开发了鳍式场效应晶体管(FinFET)。在传统的FinFET形成工艺中,半导体鳍状件可以以如下方式形成:在硅衬底中形成沟槽,用电介质材料填充沟槽以形成浅沟槽隔离(STI)区域,然后对STI区域的顶部开槽。因此,在STI区域的被开槽部分之间的硅衬底部分形成半导体鳍状件,FinFET形成于半导体鳍状件之上。
硅衬底可以是(100)衬底或者(110)衬底。如果使用(100)衬底来形成FinFET,则得到的鳍状件具有粗糙并且略微倾斜的侧壁表面,并且受邻近效应的影响。此外,图案密集区域中的鳍状件的轮廓与图案稀疏区域中的鳍状件的轮廓不同。另一方面,如果使用(110)衬底来形成FinFET,则得到的鳍状件具有高质量并且垂直的侧壁表面。然而,可能由于使用(110)衬底而牺牲基于(110)衬底的FinFETs的器件性能。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种方法,包括:
蚀刻(110)硅衬底以在所述(110)硅衬底中形成第一沟槽,其中位于所述第一沟槽之间的所述(110)硅衬底的剩余部分形成硅条,所述硅条的侧壁具有(111)表面方向;
用电介质材料填充所述第一沟槽以形成浅沟槽隔离(STI)区域;
去除所述硅条以在所述STI区域之间形成第二沟槽;
实施外延以在所述第二沟槽中生长半导体条;以及
对所述STI区域的顶部部分开槽,其中位于所述STI区域的被去除顶部部分之间的所述半导体条的顶部部分形成半导体鳍状件。
在可选实施例中,在蚀刻所述(110)硅衬底的步骤之前,将(100)硅衬底通过界面层接合所述(110)硅衬底,并且在蚀刻所述(110)硅衬底的步骤中,所述界面层用作蚀刻停止层。
在可选实施例中,在实施外延的步骤之前,去除所述界面层通过所述第二沟槽暴露的部分以暴露所述(100)硅衬底,所述半导体条自所述(100)硅衬底外延生长。
在可选实施例中,所述界面层进一步包括氧化硅、氮氧化硅SiON、氮化硅、多晶硅、金属氧化物(例如TiO2,Al2O3,HfO2等)、金属氮化物(如TiN,TaN等)或金属(Ti,Ge等)。
在可选实施例中,当所述第一沟槽的底部位于所述(110)硅衬底的顶面和底面之间的中间水平位置时,停止蚀刻所述(110)硅衬底的步骤,并且其中所述半导体条包括非硅半导体材料。
在可选实施例中,所述方法还包括:在形成所述STI区域之后、去除所述硅条的步骤之前,将(100)硅衬底接合至所述STI区域上;减薄所述(110)硅衬底;在接合所述(100)硅衬底的步骤之后,去除所述硅条,其中在实施完去除所述硅条的步骤之后,所述(100)硅衬底通过所述第二沟槽暴露,并且其中所述半导体条自所述(100)硅衬底外延生长。
在可选实施例中,将(100)硅衬底直接接合所述(110)硅衬底,并且当所述(100)硅衬底暴露时,停止蚀刻所述(110)硅衬底的步骤。
在可选实施例中,所述半导体条自所述(100)硅衬底外延生长。
根据本发明的另一个方面,还提供了一种方法,包括:
提供复合衬底,所述复合衬底包括:
(100)硅衬底;
在所述(100)硅衬底上并接合所述(100)硅衬底的界面层;以及
在所述界面层上并接合所述界面层的(110)硅衬底;
蚀刻所述(110)硅衬底以形成在所述(110)硅衬底中的第一沟槽,其中位于所述第一沟槽之间的所述(110)硅衬底的剩余部分形成硅条;
用电介质材料填充所述第一沟槽以形成在所述第一沟槽中的浅沟槽隔离(STI)区域;
去除所述硅条以在所述STI区域之间形成第二沟槽,其中所述界面层通过所述第二沟槽暴露;
去除所述界面层通过所述第二沟槽暴露的部分,其中所述(110)硅衬底通过所述第二沟槽暴露;以及
实施外延以在所述第二沟槽中生长半导体条,其中所述半导体条自(100)硅衬底外延生长。
在可选实施例中,所述界面层进一步包括氧化硅、氮氧化硅SiON、氮化硅、多晶硅、金属氧化物(例如TiO2,Al2O3,HfO2等)、金属氮化物(如TiN,TaN等)或金属(Ti,Ge等)。
在可选实施例中,所述硅条的侧壁具有(111)表面方向。
在可选实施例中,所述方法还包括:对所述STI区域的顶部部分开槽,其中位于STI区域的顶部部分之间的所述半导体条的顶部部分形成半导体鳍状件。
在可选实施例中,所述半导体条包括基本上纯的硅。
在可选实施例中,所述半导体条包括非硅半导体材料。
在可选实施例中,所述方法还包括:在蚀刻所述(110)硅衬底的步骤之前,在所述(110)硅衬底上形成第一硬掩模;在所述第一硬掩模上形成并图案化第二硬掩模;在图案化后的所述第二硬掩模的顶面和侧壁上形成间隔膜;去除所述间隔膜的水平部分和所述第二硬掩模,其中所述间隔膜的垂直部分被保留以形成间隔件;使用所述间隔件作为蚀刻掩模来蚀刻所述第一硬掩模,其中所述第一硬掩模的剩余部分形成硬掩模图案,蚀刻所述(110)硅衬底的步骤使用所述硬掩模图案作为另外的蚀刻掩模来实施。
根据本发明的又一个方面,还提供了一种器件,包括:
(100)硅衬底;
平坦界面层,在所述(100)硅衬底的顶面上;
隔离区域,位于所述平坦界面层上并与所述界面层相接触,其中所述隔离区域与所述平坦界面层之间的界面是可区分的并且实质上是平坦的;以及
半导体条,自所述隔离区域的顶面延伸并进入到所述隔离区域以及所述平坦界面层中,其中所述半导体条的底面与所述(100)硅衬底接触。
在可选实施例中,所述平坦界面层基本上没有延伸至所述半导体条的侧壁上,并且其中所述半导体条与在所述半导体条的相对侧的两个所述隔离区域物理接触。
在可选实施例中,所述半导体条的顶部部分在所述隔离区域的所述顶面上方以形成半导体鳍状件。
在可选实施例中,所述平坦界面层和所述隔离区域由实质相同的材料形成。
在可选实施例中,所述平坦界面层和所述隔离区域包括不同的材料。
在可选实施例中,所述半导体条的底面大致平齐于所述平坦界面层的底面。
在可选实施例中,所述界面层进一步包括氧化硅、氮氧化硅SiON、氮化硅、多晶硅、金属氧化物(例如TiO2,Al2O3,HfO2等)、金属氮化物(如TiN,TaN等)或金属(Ti,Ge等)。
附图说明
为更完整的理解实施例及其优点,现将结合附图所进行的以下描述作为参考,其中:
图1至图9是根据本发明一些示例性实施例的在制造半导体鳍状件以及鳍式场效应晶体管(FinFET)过程中的中间阶段的截面图;以及,
图10至图30示出了根据本发明一些可选示例性实施例的在制造半导体鳍状件以及FinFET过程中的中间阶段的截面图。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅是示例性的,并不用于限制本发明的范围。
提供了可用于形成半导体鳍状件的方法,其中半导体鳍状用于形成鳍式场效应晶体管(FinFET)。示出了根据实施例的制造半导体鳍状件和FinFETs过程的中间阶段。讨论了实施例的变化形式。贯穿不同的示图以及示例性实施例,相同的附图标记用来指代相同的元件。
参考图1,提供了复合半导体衬底20。复合半导体衬底20包括晶体硅衬底22、在硅衬底22之上的氧化物层24、以及在氧化物层24之上晶体硅衬底26。硅衬底22和26与氧化物层24相接合。氧化物层24的厚度可以是在大约至大约之间,尽管可以使用其他的厚度。然而,本领域普通技术人员将意识到说明书通篇描述的尺寸仅仅是为了举例说明的作用,其可以改变至不同的数值。硅衬底22具有(100)表面方向。硅衬底26具有(110)表面方向。因此,硅衬底22和26分别也可以称为(100)衬底和(110)衬底。氧化物层24可包括氧化硅,然而也可使用其他类型的氧化物。
硬掩模28和30形成在硅衬底26上方。在一些实施例中,由氧化硅形成的氧化物焊盘(未示出)形成在硅衬底26与硬掩模28之间。硬掩模28和30可由诸如氮化硅、氮氧化硅以及碳化硅等形成。硬掩模28和30可由不同的材料形成。因此,在没有图案化硬掩模28的情况下图案化硬掩模30。然后,在硬掩模30的顶面以及侧壁上形成间隔膜32,例如使用共形沉积方法。
接下来,如图2所示,去除间隔膜32的水平部分,例如在蚀刻步骤中。然后去除硬掩模30。在下文中,将间隔膜32的剩余垂直部分称作间隔件34。通过实施图1和2中示出的步骤,间隔件34的节距可以减少至硬掩模30的节距的一半。在可选实施例中,可以跳过图1中所示的步骤,直接采用沉积步骤和图案化步骤形成间隔34。
接下来,如图3中所示,使用间隔件34作为蚀刻掩模以蚀刻硬掩模28,以使间隔件34的图案转移至硬掩模28,形成硬掩模图案36。然后去除间隔件34。
参考图4,硬掩模图案36用于蚀刻穿过下面的硅衬底26,以形成硅条40和沟槽42。实施蚀刻可以使用氧化物层24作为蚀刻停止层。因此,在蚀刻之后,可以通过硅衬底26中的沟槽42暴露氧化物层24。选择硬掩模30和间隔件34的纵向方向(在图1-3示出结构的俯视图中),以使硅条40的侧壁表面40A具有(111)表面方向。由于(111)表面相比于一些其他表面(诸如(100)和(110)表面)更为密实,因此硅条40的侧壁40A的质量更为光滑。此外,由于(111)表面是比其他表面(诸如(100)和(110)表面)具有更低蚀刻率的稳定表面(stable surface),因此,侧壁表面40A是垂直的,并且与衬底26的初始(110)表面相垂直。
图5示出了在沟槽42中填充电介质材料,然后实施化学机械抛光(Chemical Mechanical Polish,CMP)步骤以去除在硬掩模图案36上的电介质材料的多余部分。接下来,如图6所示,去除硬掩模图案36。氧化物焊盘层,如果有,则也去除。在下文中,将在硅条40之间的剩余的电介质材料称作浅沟槽隔离(STI)区域46。STI区域46可包括氧化硅和/或其他电介质材料。在一些实施例中,STI区域46和氧化物层24由诸如氧化硅的相同的材料形成。在可选实施例中,STI区域46和氧化物层24由不同的材料形成。由于STI区域46和氧化物层24是在不同的步骤中形成的,因此STI区域46和氧化物层24之间的界面是可见的,因此STI区域46和氧化物层24相互之间是可以区分开的。
参考图7,去除硅条40,从而形成STI区域46之间的沟槽48。因此,氧化物层24通过沟槽48来暴露。接下来,蚀刻氧化物层24的暴露部分,以使得其下的硅衬底22通过沟槽48来暴露。在接下来的步骤中,如图8中所示,形成外延,以使半导体条50外延生长在沟槽48中。由于半导体条50自(100)衬底20生长,因此半导体条50具有(100)顶面方向。
在一些示例性实施例中,半导体条50包括基本上纯的硅。在一些可选实施例中,半导体条50包括非硅半导体材料,诸如纯的或者基本上纯的锗、锗硅;或者包括III-V化合物半导体,诸如InAs,AlAs,GaAs,InP,GaN,InGaAs,InAlAs,GaSb,AlSb,AlP,GaP或类似物。在半导体条50是由非硅半导体材料形成的实施例中,半导体条50可包括缓冲区域50A以及其上覆盖的非硅半导体区域50B。缓冲区域50A可以具有在硅衬底22的晶格常数与非硅半导体区域50B的晶格常数之间的晶格常数,以使非硅半导体区域50B中的瑕疵数目减少。
在外延生长半导体条50之后,对STI区域开槽,以使半导体条50的顶部部分(在下文中称为鳍状件50’)位于剩余的STI区域46的顶面的上方。然后,半导体鳍状件50’可用于形成FinFET100。FinFET的形成可以包括在半导体鳍状件50’的顶面和侧壁上形成栅极电介质102,在栅极电介质102之上形成栅电极104,在栅电极104的相对侧形成源极区域和漏极区域(不在示出面上)。在此不详述形成细节。
由于氧化物层24和STI区域46是在不同的工艺步骤中形成的,因此在图8和9示出的结构中,不管氧化物层24和STI区域46是以相同的材料还是以不同的材料形成的,氧化物层24和STI区域46都具有可见的界面。因此,STI区域46和氧化物层24相互之间是可以区分开的。此外,氧化物层24是平坦的层,并且并不延伸至半导体条50的侧壁。此外,在半导体条50与硅衬底22之间可有可见的界面50C,例如在硅衬底22与半导体条50包括不同的材料时。
可以观察到由于半导体条50形成在硅条40(图6和7)留下的开口中,因此半导体条50的侧壁轮廓与硅条40的侧壁轮廓大致相同。由于硅条40具有(111)表面方向,因此其侧壁垂直并且光滑。因此半导体条50的侧壁也垂直并且光滑。因此提高了半导体条50的质量和最终得到的FinFET的质量。
图10至图17示出了根据可选实施例的在形成半导体鳍状件以及FinFET过程中的中间阶段的截面图。除非具体说明,否则在这些实施例(以及图18至30中所示的实施例)中的部件的材料和形成方法本质上与图1至9的实施例中相同的部件相同,并以与图1至9的实施例中的组件相同的附图标记来表示。因此,图10至30中示出的实施例的形成细节可在图1至9中示出的实施例的讨论中找到。
参考图10,提供硅衬底26,随后形成在氧化物焊盘(未示出)、硬掩模28以及硬掩模30。然后图案化硬掩模30,并在图案化硬掩模30的顶面和侧壁上形成间隔膜32。硅衬底26是具有(110)表面方向的(110)衬底。接下来,参考图11,形成间隔件34,其为图10中的间隔膜32的剩余部分。形成间隔件34的细节基本上与图2示出的相同。接下来,使用间隔件34作为蚀刻掩模以蚀刻硬掩模28。因此,形成图12中示出的硬掩模图案36。然后,去除间隔件34。
图13示出硅衬底26的蚀刻,其中蚀刻停止在硅衬底26的中间水平位置。因此,沟槽42形成在硅衬底26中。位于沟槽42之间的硅衬底26的部分是硅条40。选择硅条40的纵向方向(在图13示出结构的俯视图中),以使硅条40的侧壁40A具有(111)表面方向。因此,侧壁40A光滑且垂直。
接下来,如图14中所示,形成STI区域46。然后,通过蚀刻来去除硅条40和其上覆盖的硬掩模图案36,形成沟槽48。图15中示出了得到的结构。在一些实施例中,当沟槽48的底面48B与STI区域46的底面46A相平齐时,停止去除硅条40。可选地,底面48A可以比STI区域46的底面46A高或者低。虚线48B示出了根据这些实施例的沟槽48的相应的底面。
接下来,如图16中所示,半导体条50外延生长在沟槽48中,其中自硅衬底26开始外延,或者自硅条40的剩余部分(如果存在)开始外延。半导体条50的底面可以高于、平齐于或者低于STI区域46的底面46A。与图8中示出的实施例相似,半导体条50可以由硅或者非硅半导体材料形成。半导体条50的候选材料可以与图8中示出的实施例中的基本相同。在后续步骤中,如图17所示,对S TI区域46开槽以形成鳍状件50’。然后,包括栅极电介质102和栅电极104的FinFET 100可形成半导体鳍状件50’上。在最终得到的结构中,半导体鳍状件50’以及半导体条50具有侧壁50D。由于半导体条50自(110)衬底26生长,因此侧壁50D也具有表面方向。
图18至图22示出了根据本发明另一些可选实施例的在形成半导体鳍状件以及FinFET过程中的中间阶段的截面图。初始步骤与图10至14基本相同。因此,材料和工艺细节可参考图10至14中的实施例。接下来,如图18中所示,为(100)衬底的硅衬底22接合至STI区域46。STI区域46可由诸如氧化硅的氧化物形成。因此,该接合可以是熔融接合。
接下来,参考图19,初始硅衬底26减薄。在一些实施例中,通过研磨实施减薄,直至留下很薄的硅衬底26。在可选实施例中,实施减薄直至暴露STI区域46。接下来,如图20中所示,去除硅衬底26的所有剩余部分,包括硅条40。如在图19中示出的硬掩模图案36的剩余部分也通过蚀刻步骤来去除,从而形成STI区域46之间的沟槽48。
在图21中,可为硅条或者非硅条的半导体条50通过外延形成在沟槽48中。图22示出了通过对STI区域46开槽形成半导体鳍状件50’。然后,包括栅极电介质102和栅电极104的FinFET 100可形成于半导体鳍状件50’上。由于半导体条50自(100)衬底22生长,因此半导体条50以及半导体鳍状件50’具有(100)顶面方向。
图23至图30示出了根据本发明又一些可选实施例的在形成半导体鳍状件过程中的中间阶段的截面图。这些实施例与图1至7中示出的实施例相类似,除了复合半导体衬底20不包括位于硅衬底22和硅衬底26之间的氧化物层。如在图23至25中所示,实施多个工艺步骤(与图1至3中的基本相同)形成如图25中的硬掩模图案36。硅衬底22和26分别是(100)衬底和(110)衬底,并相互接合。在硅衬底22和硅衬底26之间可没有其他的层。接下来,如在图26中所示,蚀刻衬底26以形成硅条40和沟槽42。再次,硅条40的侧壁40A具有(111)表面方向。实施蚀刻直至通过沟槽42暴露硅衬底22。在一些实施例中,沟槽42延伸至硅衬底22中。因此倾斜面22B形成在硅衬底22中。
接下来,参考图27,STI区域46形成在沟槽42中,然后去除硬掩模图案36。在图28中,在蚀刻步骤中去除硅条40,并因此在STI区域46之间形成沟槽48。在去除硅条40之后,通过沟槽48暴露硅衬底22。接下来,如在图29中所示,形成可为硅条或者非硅半导体条的半导体条50。图30示出了通过对STI区域46开槽形成半导体鳍状件50’。然后,包括栅极电介质102和栅电极104的FinFET 100可形成在半导体鳍状件50’上。
在实施例中,半导体鳍状件从(110)衬底开始形成,并且半导体鳍状件的侧壁表面具有与(111)硅表面基本相同的轮廓和质量。在这些实施例中,具有(111)表面并自(110)衬底形成的硅鳍状件用作模具(mold),并且非硅鳍状件或(100)硅鳍状件从模具形成。因此,提高了最终得到的半导体鳍状件的质量。
根据实施例,蚀刻(110)硅衬底以在(110)硅衬底中形成第一沟槽,其中位于第一沟槽之间的(110)硅衬底的剩余部分形成硅条。硅条的侧壁具有(111)表面方向。用电介质材料填充第一沟槽以形成浅沟槽隔离(STI)区域。将硅条去除以形成位于STI区域之间的第二沟槽。实施外延以在第二沟槽中生长半导体条。对STI区域的顶部部分开槽,并且在位于STI区域的被去除顶部部分之间的半导体条的顶部形成半导体鳍状件。
根据其他实施例,一种方法包括提供复合衬底,该复合衬底包括(100)硅衬底,在(100)硅衬底上并且接合(100)硅衬底的氧化物层;以及在氧化物层上并接合氧化物层的(110)硅衬底。蚀刻(110)硅衬底以在(110)硅衬底中形成第一沟槽,其中位于第一沟槽之间的(110)硅衬底的剩余部分形成硅条。在蚀刻步骤期间,氧化物层用作蚀刻停止层。用电介质材料填充第一沟槽以形成在第一沟槽中的STI区域。去除硅条以在STI区域之间形成第二沟槽,通过第二沟槽暴露氧化物层。去除通过第二沟槽暴露的氧化物层的部分,使得通过第二沟槽暴露(100)硅衬底。实施外延以在第二沟槽中自(100)硅衬底生长半导体条。
根据另一其他实施例,一种器件包括(100)硅衬底、在(100)硅衬底的顶面上的平坦氧化物层、以及在平坦氧化物层上并与平坦氧化物层相接触的隔离区域。在隔离区域和平坦氧化物层之间的界面是可区分的并且大致是平坦的。半导体条自隔离区域的顶面延伸并进入到隔离区域以及平坦氧化物层中。半导体条的底面与(100)硅衬底相接触。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每项权利要求构成单独的实施例,并且各权利要求和实施例的组合在本发明的范围内。
Claims (10)
1.一种方法,包括:
蚀刻(110)硅衬底以在所述(110)硅衬底中形成第一沟槽,其中位于所述第一沟槽之间的所述(110)硅衬底的剩余部分形成硅条,所述硅条的侧壁具有(111)表面方向;
用电介质材料填充所述第一沟槽以形成浅沟槽隔离(STI)区域;
去除所述硅条以在所述STI区域之间形成第二沟槽;
实施外延以在所述第二沟槽中生长半导体条;以及
对所述STI区域的顶部部分开槽,其中位于所述STI区域的被去除顶部部分之间的所述半导体条的顶部部分形成半导体鳍状件。
2.根据权利要求1所述的方法,其中,在蚀刻所述(110)硅衬底的步骤之前,将(100)硅衬底通过界面层接合所述(110)硅衬底,并且在蚀刻所述(110)硅衬底的步骤中,所述界面层用作蚀刻停止层。
3.根据权利要求2所述的方法,其中,在实施外延的步骤之前,去除所述界面层通过所述第二沟槽暴露的部分以暴露所述(100)硅衬底,所述半导体条自所述(100)硅衬底外延生长。
4.一种方法,包括:
提供复合衬底,所述复合衬底包括:
(100)硅衬底;
在所述(100)硅衬底上并接合所述(100)硅衬底的界面层;以及
在所述界面层上并接合所述界面层的(110)硅衬底;
蚀刻所述(110)硅衬底以形成在所述(110)硅衬底中的第一沟槽,其中位于所述第一沟槽之间的所述(110)硅衬底的剩余部分形成硅条;
用电介质材料填充所述第一沟槽以形成在所述第一沟槽中的浅沟槽隔离(STI)区域;
去除所述硅条以在所述STI区域之间形成第二沟槽,其中所述界面层通过所述第二沟槽暴露;
去除所述界面层通过所述第二沟槽暴露的部分,其中所述(110)硅衬底通过所述第二沟槽暴露;以及
实施外延以在所述第二沟槽中生长半导体条,其中所述半导体条自(100)硅衬底外延生长。
5.一种器件,包括:
(100)硅衬底;
平坦界面层,在所述(100)硅衬底的顶面上;
隔离区域,位于所述平坦界面层上并与所述界面层相接触,其中所述隔离区域与所述平坦界面层之间的界面是可区分的并且实质上是平坦的;以及
半导体条,自所述隔离区域的顶面延伸并进入到所述隔离区域以及所述平坦界面层中,其中所述半导体条的底面与所述(100)硅衬底接触。
6.根据权利要求5所述的器件,其中所述平坦界面层基本上没有延伸至所述半导体条的侧壁上,并且其中所述半导体条与在所述半导体条的相对侧的两个所述隔离区域物理接触。
7.根据权利要求5所述的器件,其中所述半导体条的顶部部分在所述隔离区域的所述顶面上方以形成半导体鳍状件。
8.根据权利要求5所述的器件,其中所述平坦界面层和所述隔离区域由实质相同的材料形成。
9.根据权利要求5所述的器件,其中所述平坦界面层和所述隔离区域包括不同的材料。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/344,423 | 2012-01-05 | ||
US13/344,423 US8629038B2 (en) | 2012-01-05 | 2012-01-05 | FinFETs with vertical fins and methods for forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103199019A true CN103199019A (zh) | 2013-07-10 |
CN103199019B CN103199019B (zh) | 2016-12-21 |
Family
ID=48721477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210193763.3A Active CN103199019B (zh) | 2012-01-05 | 2012-06-12 | 具有垂直鳍状件的鳍式场效应晶体管及其形成方法 |
Country Status (3)
Country | Link |
---|---|
US (4) | US8629038B2 (zh) |
CN (1) | CN103199019B (zh) |
TW (1) | TWI508147B (zh) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104425275A (zh) * | 2013-09-04 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104425276A (zh) * | 2013-09-04 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
CN104465375A (zh) * | 2013-09-17 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | P型鳍式场效应晶体管的形成方法 |
CN105097517A (zh) * | 2014-04-25 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 一种FinFET器件及其制造方法、电子装置 |
CN105745759A (zh) * | 2013-12-23 | 2016-07-06 | 英特尔公司 | 非同质半导体衬底上的宽带隙晶体管及其制造方法 |
CN106960846A (zh) * | 2016-01-12 | 2017-07-18 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN107004710A (zh) * | 2014-12-23 | 2017-08-01 | 英特尔公司 | 形成具有侧壁衬垫的鳍状物结构的装置和方法 |
CN107636838A (zh) * | 2015-06-27 | 2018-01-26 | 英特尔公司 | 低损害自对准两性finfet尖端掺杂 |
CN109427900A (zh) * | 2017-08-21 | 2019-03-05 | 三星电子株式会社 | 包括沟道图案的半导体器件及其制造方法 |
US10580895B2 (en) | 2013-12-23 | 2020-03-03 | Intel Corporation | Wide band gap transistors on non-native semiconductor substrates |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8629038B2 (en) | 2012-01-05 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with vertical fins and methods for forming the same |
US8809178B2 (en) * | 2012-02-29 | 2014-08-19 | Globalfoundries Inc. | Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents |
US8710681B2 (en) * | 2012-05-31 | 2014-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation rings for blocking the interface between package components and the respective molding compound |
CN103779210A (zh) * | 2012-10-18 | 2014-05-07 | 中国科学院微电子研究所 | FinFET鳍状结构的制造方法 |
KR20160029005A (ko) * | 2013-06-28 | 2016-03-14 | 인텔 코포레이션 | III-N 에피택시를 위한 Si (100) 웨이퍼들 상의 Si (111) 평면들을 가진 나노구조들 및 나노피처들 |
EP2849219A1 (en) * | 2013-09-11 | 2015-03-18 | IMEC vzw | Method for manufacturing transistors and associated substrate |
US9324717B2 (en) * | 2013-12-28 | 2016-04-26 | Texas Instruments Incorporated | High mobility transistors |
US9640422B2 (en) | 2014-01-23 | 2017-05-02 | Intel Corporation | III-N devices in Si trenches |
KR20150101398A (ko) * | 2014-02-24 | 2015-09-03 | 아이엠이씨 브이제트더블유 | 기판 내 반도체 장치의 핀 구조체 제조방법 |
US9443769B2 (en) | 2014-04-21 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wrap-around contact |
US20150380258A1 (en) * | 2014-06-25 | 2015-12-31 | Stmicroelectronics, Inc. | Method for controlling height of a fin structure |
KR20160034492A (ko) * | 2014-09-19 | 2016-03-30 | 삼성전자주식회사 | 반도체 소자의 패턴 형성 방법 및 이를 이용하여 형성된 반도체 소자 |
CN107004712B (zh) * | 2014-12-23 | 2021-04-20 | 英特尔公司 | 利用基于深宽比沟槽的工艺形成均匀层 |
WO2016190858A1 (en) * | 2015-05-27 | 2016-12-01 | Intel Corporation | Apparatus and methods to create a buffer which extends into a gated region of a transistor |
KR102475832B1 (ko) * | 2015-06-16 | 2022-12-09 | 인텔 코포레이션 | 서브핀 층을 갖는 트랜지스터 |
US10546858B2 (en) | 2015-06-27 | 2020-01-28 | Intel Corporation | Low damage self-aligned amphoteric FINFET tip doping |
US9397005B1 (en) * | 2015-07-20 | 2016-07-19 | International Business Machines Corporation | Dual-material mandrel for epitaxial crystal growth on silicon |
KR102424963B1 (ko) | 2015-07-30 | 2022-07-25 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
US9583623B2 (en) | 2015-07-31 | 2017-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof |
KR102323943B1 (ko) | 2015-10-21 | 2021-11-08 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
CN106611787A (zh) * | 2015-10-26 | 2017-05-03 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
US9406566B1 (en) * | 2015-12-04 | 2016-08-02 | International Business Machines Corporation | Integration of III-V compound materials on silicon |
US9496260B1 (en) * | 2015-12-09 | 2016-11-15 | International Business Machines Corporation | Tall strained high percentage silicon germanium fins for CMOS |
US11018254B2 (en) * | 2016-03-31 | 2021-05-25 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
US9786546B1 (en) * | 2016-04-06 | 2017-10-10 | International Business Machines Corporation | Bulk to silicon on insulator device |
US9627511B1 (en) | 2016-06-21 | 2017-04-18 | International Business Machines Corporation | Vertical transistor having uniform bottom spacers |
US10910223B2 (en) * | 2016-07-29 | 2021-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping through diffusion and epitaxy profile shaping |
US10515951B2 (en) | 2016-11-29 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
CN109994379B (zh) * | 2017-12-29 | 2021-10-19 | 长鑫存储技术有限公司 | 双重图形化方法及双重图形化结构 |
US10431686B1 (en) * | 2018-09-10 | 2019-10-01 | Qualcomm Incorporated | Integrated circuit (IC) employing a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity |
CN113078056B (zh) * | 2021-03-30 | 2022-06-24 | 长鑫存储技术有限公司 | 半导体结构的制作方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050184283A1 (en) * | 2004-02-20 | 2005-08-25 | Shigenobu Maeda | Semiconductor device having a triple gate transistor and method for manufacturing the same |
CN101303975A (zh) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管及其形成方法 |
US20090072276A1 (en) * | 2007-08-24 | 2009-03-19 | Kabushiki Kaisha Toshiba | Semiconductor wafer, semiconductor device and method of fabricating the same |
US20090256208A1 (en) * | 2008-04-11 | 2009-10-15 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
CN102217074A (zh) * | 2008-09-16 | 2011-10-12 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管(finfet) |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3953264A (en) * | 1974-08-29 | 1976-04-27 | International Business Machines Corporation | Integrated heater element array and fabrication method |
US5777370A (en) * | 1996-06-12 | 1998-07-07 | Advanced Micro Devices, Inc. | Trench isolation of field effect transistors |
US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
ATE546837T1 (de) * | 2004-01-22 | 2012-03-15 | Ibm | Vertikal fin-fet-mos-vorrichtungen |
US7300837B2 (en) * | 2004-04-30 | 2007-11-27 | Taiwan Semiconductor Manufacturing Co., Ltd | FinFET transistor device on SOI and method of fabrication |
TWI281257B (en) * | 2005-03-30 | 2007-05-11 | Taiwan Semiconductor Mfg | Quasi-planar and FinFET-like transistors on bulk silicon |
US8324660B2 (en) * | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US9153645B2 (en) * | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US7381649B2 (en) * | 2005-07-29 | 2008-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for a multiple-gate FET device and a method for its fabrication |
US7323374B2 (en) * | 2005-09-19 | 2008-01-29 | International Business Machines Corporation | Dense chevron finFET and method of manufacturing same |
US7719058B2 (en) * | 2005-10-12 | 2010-05-18 | Seliskar John J | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof |
KR100801315B1 (ko) * | 2006-09-29 | 2008-02-05 | 주식회사 하이닉스반도체 | 돌기형트랜지스터가 구비된 반도체소자의 제조 방법 |
US8106381B2 (en) * | 2006-10-18 | 2012-01-31 | Translucent, Inc. | Semiconductor structures with rare-earths |
US7544994B2 (en) * | 2006-11-06 | 2009-06-09 | International Business Machines Corporation | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure |
US20090098702A1 (en) * | 2007-10-16 | 2009-04-16 | Texas Instruments Incorporated | Method to Form CMOS Circuits Using Optimized Sidewalls |
KR100905783B1 (ko) * | 2007-10-31 | 2009-07-02 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
US20090152589A1 (en) * | 2007-12-17 | 2009-06-18 | Titash Rakshit | Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors |
US9543356B2 (en) * | 2009-03-10 | 2017-01-10 | Globalfoundries Inc. | Pixel sensor cell including light shield |
KR101110355B1 (ko) * | 2010-04-05 | 2012-02-14 | 서울대학교산학협력단 | 차단 게이트 라인을 갖는 3차원 스택 어레이 및 그 제조방법 |
US8729627B2 (en) * | 2010-05-14 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
US9263339B2 (en) * | 2010-05-20 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective etching in the formation of epitaxy regions in MOS devices |
KR101776926B1 (ko) * | 2010-09-07 | 2017-09-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8853781B2 (en) * | 2011-12-16 | 2014-10-07 | International Business Machines Corporation | Rare-earth oxide isolated semiconductor fin |
US8742457B2 (en) * | 2011-12-16 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Anti-fuses on semiconductor fins |
US8486770B1 (en) * | 2011-12-30 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming CMOS FinFET device |
US8629038B2 (en) * | 2012-01-05 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with vertical fins and methods for forming the same |
US9564513B2 (en) * | 2014-02-14 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Epitaxy in semiconductor structure and manufacturing method thereof |
US9754875B1 (en) * | 2016-07-20 | 2017-09-05 | International Business Machines Corporation | Designable channel FinFET fuse |
-
2012
- 2012-01-05 US US13/344,423 patent/US8629038B2/en active Active
- 2012-06-12 CN CN201210193763.3A patent/CN103199019B/zh active Active
- 2012-06-25 TW TW101122589A patent/TWI508147B/zh active
-
2013
- 2013-11-14 US US14/080,264 patent/US9196677B2/en active Active
-
2015
- 2015-11-10 US US14/937,238 patent/US9711623B2/en active Active
-
2017
- 2017-07-17 US US15/651,418 patent/US10002947B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050184283A1 (en) * | 2004-02-20 | 2005-08-25 | Shigenobu Maeda | Semiconductor device having a triple gate transistor and method for manufacturing the same |
CN101303975A (zh) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管及其形成方法 |
US20090072276A1 (en) * | 2007-08-24 | 2009-03-19 | Kabushiki Kaisha Toshiba | Semiconductor wafer, semiconductor device and method of fabricating the same |
US20090256208A1 (en) * | 2008-04-11 | 2009-10-15 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
CN102217074A (zh) * | 2008-09-16 | 2011-10-12 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管(finfet) |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104425276A (zh) * | 2013-09-04 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
CN104425275B (zh) * | 2013-09-04 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104425275A (zh) * | 2013-09-04 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104425276B (zh) * | 2013-09-04 | 2017-06-16 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
CN104465375B (zh) * | 2013-09-17 | 2017-09-29 | 中芯国际集成电路制造(上海)有限公司 | P型鳍式场效应晶体管的形成方法 |
CN104465375A (zh) * | 2013-09-17 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | P型鳍式场效应晶体管的形成方法 |
CN105745759A (zh) * | 2013-12-23 | 2016-07-06 | 英特尔公司 | 非同质半导体衬底上的宽带隙晶体管及其制造方法 |
US10580895B2 (en) | 2013-12-23 | 2020-03-03 | Intel Corporation | Wide band gap transistors on non-native semiconductor substrates |
CN105745759B (zh) * | 2013-12-23 | 2020-03-10 | 英特尔公司 | 非同质半导体衬底上的宽带隙晶体管及其制造方法 |
CN105097517A (zh) * | 2014-04-25 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 一种FinFET器件及其制造方法、电子装置 |
CN105097517B (zh) * | 2014-04-25 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | 一种FinFET器件及其制造方法、电子装置 |
CN107004710A (zh) * | 2014-12-23 | 2017-08-01 | 英特尔公司 | 形成具有侧壁衬垫的鳍状物结构的装置和方法 |
CN107636838A (zh) * | 2015-06-27 | 2018-01-26 | 英特尔公司 | 低损害自对准两性finfet尖端掺杂 |
CN107636838B (zh) * | 2015-06-27 | 2022-01-14 | 英特尔公司 | 低损害自对准两性finfet尖端掺杂 |
CN106960846A (zh) * | 2016-01-12 | 2017-07-18 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN106960846B (zh) * | 2016-01-12 | 2020-07-28 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN109427900A (zh) * | 2017-08-21 | 2019-03-05 | 三星电子株式会社 | 包括沟道图案的半导体器件及其制造方法 |
CN109427900B (zh) * | 2017-08-21 | 2024-03-08 | 三星电子株式会社 | 包括沟道图案的半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103199019B (zh) | 2016-12-21 |
TW201330067A (zh) | 2013-07-16 |
US20140070360A1 (en) | 2014-03-13 |
TWI508147B (zh) | 2015-11-11 |
US20160064530A1 (en) | 2016-03-03 |
US9711623B2 (en) | 2017-07-18 |
US8629038B2 (en) | 2014-01-14 |
US9196677B2 (en) | 2015-11-24 |
US20170317191A1 (en) | 2017-11-02 |
US10002947B2 (en) | 2018-06-19 |
US20130175659A1 (en) | 2013-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103199019A (zh) | 具有垂直鳍状件的鳍式场效应晶体管及其形成方法 | |
US11682697B2 (en) | Fin recess last process for FinFET fabrication | |
US11393814B2 (en) | Method for forming semiconductor device with helmet structure between two semiconductor fins | |
US10083872B2 (en) | Methods for forming Fin field-effect transistors | |
US8377779B1 (en) | Methods of manufacturing semiconductor devices and transistors | |
US10886269B2 (en) | Semiconductor device and manufacturing method thereof | |
US9954104B2 (en) | Multiwidth finFET with channel cladding | |
KR101808915B1 (ko) | 핀 구조물을 포함하는 반도체 디바이스 및 그 제조 방법 | |
CN103854989B (zh) | 具有相同鳍型场效晶体管栅极高度的结构及其形成方法 | |
US20190067111A1 (en) | Fin field effect transistor (finfet) device structure with dummy fin structure and method for forming the same | |
TWI645459B (zh) | 半導體結構及其製造方法 | |
US10236383B2 (en) | Method for fabricating semiconductor device | |
US10043675B2 (en) | Semiconductor device and method for fabricating the same | |
CN107644816B (zh) | FinFET半导体器件及其制造方法 | |
CN102468215B (zh) | 沟槽隔离结构及其形成方法 | |
WO2017096780A1 (zh) | 具有高质量外延层的半导体器件及其制造方法 | |
US9093273B2 (en) | Multiple-threshold voltage devices and method of forming same | |
US20240194675A1 (en) | Semiconductor device with helmet structure between two semiconductor fins | |
CN104658895A (zh) | 剖面改善的牺牲栅主体形成方法及半导体器件制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |