CN102904708A - Method for automatically switching fractional-order chaotic system by four systems based on Lu-type system and analog circuit - Google Patents

Abstract

The invention discloses a method for automatically switching a fractional-order chaotic system by four systems based on a Lu-type system and an analog circuit. The analog circuit comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U5, an operational amplifier U8, a multiplier U4, a multiplier U9, a multiplier U10, a voltage comparator U7 and an analog switch U6. By the analog circuit, the fractional-order chaotic system can be automatically switched by four Lu-type subsystems. The analog circuit is more complex than automatically switched chaotic systems formed by two or three sub-chaotic systems and fractional-order chaotic systems that are not switched, has higher randomness, can be a new choice for a signal source for confidential communication, and has brighter application prospect in confidential communication.

Description

Fractional order four systems automatically switched chaotic system method and analog circuit based on L ü type system

Technical field

The present invention relates to the method based on the fractional order four systems automatically switched chaotic system of L ü type system, specifically, relate to method and analog circuit based on the fractional order four systems automatically switched chaotic system of L ü type system.

Background technology

At present, oneself has several different methods to realize integer rank and chaotic systems with fractional order and circuit with analog circuit, but the method for the chaos circuit that realize to automatically switch with analog circuit is fewer, and own disclosed automatically switched chaotic system and circuit are that 2 the sub-chaos systems in integer rank switch, also there are not the method for a plurality of sub-chaos systems automatic switchovers and disclosing of circuit, the invention provides a kind of method and analog circuit of chaos system of L ü type fractional order four systems automatic switchover, quantity and the type of automatically switched chaotic system have been enriched, improved the randomness of chaos system, good application prospect has been arranged in secure communication.

Summary of the invention

The technical problem to be solved in the present invention provides method and the analog circuit based on the fractional order four systems automatically switched chaotic system of L ü type system.

The present invention adopts following technological means to realize goal of the invention:

1, based on the method for the fractional order four systems automatically switched chaotic system of L ü type system, it is characterized in that being, may further comprise the steps:

(1) according to L ü type chaos system I be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\left|x\right|-\mathrm{bz}\end{array}---\right.\mathrm{Ia}=36,b=3,c=20$

(2) according to L ü type chaos system II be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\left|y\right|-\mathrm{bz}\end{array}\right.---\mathrm{IIa}=36,b=3,c=20$

(3) according to chaos system structure sign function III and IV be:

$\mathrm{sign}\left(x\right)=\left\{\begin{array}{cc}1& x\&GreaterEqual;0\\ -1& x<0\end{array}---\mathrm{III}\right.$

$\mathrm{sign}\left(y\right)=\left\{\begin{array}{cc}1& y\&GreaterEqual;0\\ -1& y<0\end{array}---\mathrm{IV}\right.$

(4) according to L ü type chaos system V be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xsign}\left(y\right)-\mathrm{bz}\end{array}---\mathrm{Va}=36,b=3,c=20\right.$

(5) according to L ü type chaos system VI be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{ysign}\left(x\right)-\mathrm{bz}\end{array}---\mathrm{VI}=36,b=3,c=20\right.$

(6) according to chaos system structure choice function VII be:

$f\left(\mathrm{xy}\right)=\left\{\begin{array}{cc}\left|x\right|& x\&GreaterEqual;0,y\&GreaterEqual;0\\ \mathrm{xsign}\left(y\right)& x\&GreaterEqual;0,y<0\\ \mathrm{ysign}\left(x\right)& x<0,y\&GreaterEqual;0\\ \left|y\right|& x<0,y<0\end{array}---\mathrm{VII}\right.$

(7) according to the I of system, II, V, VI and L ü type four systems automatically switched chaotic system IX of choice function VII structure

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=f\left(\mathrm{xy}\right)-\mathrm{bz}\end{array}---\right.\mathrm{IX}=36,b=3,c=20$

(8) according to L ü type fractional order four systems automatically switched chaotic system X of the IX of system structure

$\left\{\begin{array}{c}{d}^{q}x/d{t}^q=a(y-x)\\ d^{q}y/d{t}^q=-\mathrm{xz}+\mathrm{cy}\\ d^{q}z/d{t}^q=f\left(\mathrm{xy}\right)-\mathrm{bz}\end{array}---X0<q<1,a=36,b=3,c=20\right.$

(9) according to chaos system X constructing analog Circuits System, utilize voltage comparator U7 to obtain the high-low level of two simulations, x 〉=0 or x＜0 and y＞=0 or y＜0, control inputs as analog switch U6, according to x 〉=0, y＞=0, x〉0, y＜0, x＜0, y＞=0 and x＜0, y＜0 four kind of different situations, realize the difference output of f (xy), thereby realize the chaos system IX that four systems automaticallyes switch, realize chaos system X by fractional order integration again, operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U5, operational amplifier U8 adopts LF347, multiplier U4, multiplier U9, multiplier U10 adopts AD633JN, and analog switch U6 adopts ADG409, and voltage comparator U7 adopts LM139;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 1st pin of U4, connects the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin links to each other with the 2nd pin by potentiometer R23, connects the 9th pin of U1 by the R24 of resistance, connect the 2nd pin of U1 by potentiometer R12, connect the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connects first the in parallel of Rc31 and capacitor C 31, connects the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, and the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;

Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;

The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;

The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects positive 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;

The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s3, and the 13rd pin connects the 7th pin of U2;

The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;

The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.

2, fractional order four systems automatic switchover analog circuit based on L ü type system, it is characterized in that being, by operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U5, operational amplifier U8 and multiplier U4, multiplier U9, multiplier U10 and voltage comparator U7 and analog switch U6 form, described operational amplifier U1 connects voltage comparator U7, operational amplifier U5, operational amplifier U8, multiplier U4, described operational amplifier U2 concatenation operation amplifier U1, operational amplifier U5, voltage comparator U7, operational amplifier U8, described operational amplifier U3 concatenation operation amplifier U2, multiplier U4, described operational amplifier U5 connecting analog switch U6, described voltage comparator U7 connecting analog switch U6, described operational amplifier U8 concatenation operation amplifier U5, multiplier U9, multiplier U10, described multiplier U9 connecting analog switch U6, described multiplier U10 connecting analog switch U6;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 1st pin of U4, connects the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin links to each other with the 2nd pin by potentiometer R23, connects the 9th pin of U1 by the R24 of resistance, connect the 2nd pin of U1 by potentiometer R12, connect the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connects first the in parallel of Rc31 and capacitor C 31, connects the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, and the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;

Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;

The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;

The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects positive 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;

The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s3, and the 13rd pin connects the 7th pin of U2;

The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;

The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.

Description of drawings

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 is operational amplifier U1 peripheral circuit structural representation.

Fig. 3 is operational amplifier U2 and multiplier U4 peripheral circuit structural representation.

Fig. 4 is operational amplifier U5 peripheral circuit structural representation.

Fig. 5 is operational amplifier U8, multiplier U9 and multiplier U10 peripheral circuit structural representation.

Fig. 6 is the peripheral circuit structural representation of operational amplifier U3, voltage comparator U7 and analog switch U6.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment the present invention is done further to describe in detail.Referring to Fig. 1-Fig. 6, at first construct L ü type fractional order four systems automatically switched chaotic system, the system that this preferred embodiment is selected

(1) according to L ü type chaos system I be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\left|x\right|-\mathrm{bz}\end{array}---\right.\mathrm{Ia}=36,b=3,c=20$

(2) according to L ü type chaos system II be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\left|y\right|-\mathrm{bz}\end{array}\right.---\mathrm{IIa}=36,b=3,c=20$

(3) according to chaos system structure sign function III and IV be:

$\mathrm{sign}\left(x\right)=\left\{\begin{array}{cc}1& x\&GreaterEqual;0\\ -1& x<0\end{array}---\mathrm{III}\right.$

$\mathrm{sign}\left(y\right)=\left\{\begin{array}{cc}1& y\&GreaterEqual;0\\ -1& y<0\end{array}---\mathrm{IV}\right.$

(4) according to L ü type chaos system V be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xsign}\left(y\right)-\mathrm{bz}\end{array}---\mathrm{Va}=36,b=3,c=20\right.$

(5) according to L ü type chaos system VI be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{ysign}\left(x\right)-\mathrm{bz}\end{array}---\mathrm{VI}=36,b=3,c=20\right.$

(6) according to chaos system structure choice function VII be:

$f\left(\mathrm{xy}\right)=\left\{\begin{array}{cc}\left|x\right|& x\&GreaterEqual;0,y\&GreaterEqual;0\\ \mathrm{xsign}\left(y\right)& x\&GreaterEqual;0,y<0\\ \mathrm{ysign}\left(x\right)& x<0,y\&GreaterEqual;0\\ \left|y\right|& x<0,y<0\end{array}---\mathrm{VII}\right.$

(7) according to the I of system, II, V, VI and L ü type four systems automatically switched chaotic system IX of choice function VII structure

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=f\left(\mathrm{xy}\right)-\mathrm{bz}\end{array}---\mathrm{IXa}=36,b=3,c=20\right.$

(8) according to L ü type fractional order four systems automatically switched chaotic system X of the IX of system structure

$\left\{\begin{array}{c}{d}^{q}x/d{t}^q=a(y-x)\\ d^{q}y/d{t}^q=-\mathrm{xz}+\mathrm{cy}\\ d^{q}z/d{t}^q=f\left(\mathrm{xy}\right)-\mathrm{bz}\end{array}---X0<q<1,a=36,b=3,c=20\right.$

(9) according to chaos system X constructing analog Circuits System, utilize voltage comparator U7 to obtain the high-low level of two simulations, x 〉=0 or x＜0 and y＞=0 or y＜0, control inputs as analog switch U6, according to x 〉=0, y＞=0, x〉0, y＜0, x＜0, y＞=0 and x＜0, y＜0 four kind of different situations, realize the difference output of f (xy), thereby realize the chaos system IX that four systems automaticallyes switch, realize chaos system X by fractional order integration again, operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U5, operational amplifier U8 adopts LF347, multiplier U4, multiplier U9, multiplier U10 adopts AD633JN, and analog switch U6 adopts ADG409, and voltage comparator U7 adopts LM139;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 1st pin of U4, connects the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin links to each other with the 2nd pin by potentiometer R23, connects the 9th pin of U1 by the R24 of resistance, connect the 2nd pin of U1 by potentiometer R12, connect the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connects first the in parallel of Rc31 and capacitor C 31, connects the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, and the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;

Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;

The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;

The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects positive 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;

The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s3, and the 13rd pin connects the 7th pin of U2;

The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;

The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.

Certainly, above-mentioned explanation is not the restriction to invention, and the present invention also is not limited only to above-mentioned giving an example, and the variation that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement also belong to protection scope of the present invention.

Claims (2)

1. based on the method for the fractional order four systems automatically switched chaotic system of L ü type system, it is characterized in that being, may further comprise the steps:

(1) according to L-type chaos system I be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\left|x\right|-\mathrm{bz}\end{array}---\right.\mathrm{Ia}=36,b=3,c=20$

(2) according to L ü type chaos system II be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\left|y\right|-\mathrm{bz}\end{array}\right.---\mathrm{IIa}=36,b=3,c=20$

(3) according to chaos system structure sign function III and IV be:

$\mathrm{sign}\left(x\right)=\left\{\begin{array}{cc}1& x\&GreaterEqual;0\\ -1& x<0\end{array}---\mathrm{III}\right.$

$\mathrm{sign}\left(y\right)=\left\{\begin{array}{cc}1& y\&GreaterEqual;0\\ -1& y<0\end{array}---\mathrm{IV}\right.$

(4) according to L ü type chaos system V be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xsign}\left(y\right)-\mathrm{bz}\end{array}---\mathrm{Va}=36,b=3,c=20\right.$

(5) according to L ü type chaos system VI be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{ysign}\left(x\right)-\mathrm{bz}\end{array}---\mathrm{VI}=36,b=3,c=20\right.$

(6) according to chaos system structure choice function VII be:

$f\left(\mathrm{xy}\right)=\left\{\begin{array}{cc}\left|x\right|& x\&GreaterEqual;0,y\&GreaterEqual;0\\ \mathrm{xsign}\left(y\right)& x\&GreaterEqual;0,y<0\\ \mathrm{ysign}\left(x\right)& x<0,y\&GreaterEqual;0\\ \left|y\right|& x<0,y<0\end{array}---\mathrm{VII}\right.$

(7) according to the I of system, II, V, VI and L ü type four systems automatically switched chaotic system IX of choice function VII structure

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=-\mathrm{xz}+\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=f\left(\mathrm{xy}\right)-\mathrm{bz}\end{array}---\right.\mathrm{IX}=36,b=3,c=20$

(8) according to L ü type fractional order four systems automatically switched chaotic system X of the IX of system structure

$\left\{\begin{array}{c}{d}^{q}x/d{t}^q=a(y-x)\\ d^{q}y/d{t}^q=-\mathrm{xz}+\mathrm{cy}\\ d^{q}z/d{t}^q=f\left(\mathrm{xy}\right)-\mathrm{bz}\end{array}---X0<q<1,a=36,b=3,c=20\right.$

(9) according to chaos system X constructing analog Circuits System, utilize voltage comparator U7 to obtain the high-low level of two simulations, x 〉=0 or x＜0 and y=0 or y＜0, control inputs as analog switch U6, according to x 〉=0, y 〉=0, x〉0, y＜0, x＜0, y 〉=0 and x＜0, y＜0 four kind of different situations, realize the difference output of f (xy), thereby realize the chaos system IX that four systems automaticallyes switch, realize chaos system X by fractional order integration again, operational amplifier U1, operational amplifier U2, operational amplifier U 3, operational amplifier U5, operational amplifier U8 adopts LF347, multiplier U4, multiplier U9, multiplier U10 adopts AD633JN, and analog switch U6 adopts ADG409, and voltage comparator U7 adopts LM139;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 1st pin of U4, connects the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin links to each other with the 2nd pin by potentiometer R23, connects the 9th pin of U1 by the R24 of resistance, connect the 2nd pin of U1 by potentiometer R12, connect the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connects first the in parallel of Rc31 and capacitor C 31, connects the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, and the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;

Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a 1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a 3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;

The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R 31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;

The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects positive 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;

The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s 1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s 2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s 3, and the 13rd pin connects the 7th pin of U2;

The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;

The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.

2. based on the fractional order four systems automatic switchover analog circuit of L ü type system, it is characterized in that being, by operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U5, operational amplifier U8 and multiplier U4, multiplier U9, multiplier U10 and voltage comparator U7 and analog switch U6 form, described operational amplifier U1 connects voltage comparator U7, operational amplifier U5, operational amplifier U8, multiplier U4, described operational amplifier U2 concatenation operation amplifier U1, operational amplifier U5, voltage comparator U7, operational amplifier U8, described operational amplifier U3 concatenation operation amplifier U2, multiplier U4, described operational amplifier U5 connecting analog switch U6, described voltage comparator U7 connecting analog switch U6, described operational amplifier U8 concatenation operation amplifier U5, multiplier U9, multiplier U10, described multiplier U9 connecting analog switch U6, described multiplier U10 connecting analog switch U6;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 1st pin of U4, connects the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin links to each other with the 2nd pin by potentiometer R23, connects the 9th pin of U1 by the R24 of resistance, connect the 2nd pin of U1 by potentiometer R12, connect the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connects first the in parallel of Rc31 and capacitor C 31, connects the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, and the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;

Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a 1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;

The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R 31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;

The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects the 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;

The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s 1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s 2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s3, and the 13rd pin connects the 7th pin of U2;

The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;

The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.

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