CN104202146A - Yang-Chen system based automatic switching hyper-chaos system construction method and analog circuit - Google Patents

Abstract

The invention relates to a two-system automatic switching hyper-chaos system and circuit, particularly to a Yang-Chen system based automatic switching hyper-chaos system construction method and circuit. Disadvantages in the prior art comprises that, the existing four-directional hyper-chaos system is formed based on a three-dimensional chaos system through increase of a one-dimensional variable in one time and feedback of the increased variable to the original three-dimensional chaos system; the existing automatic switching chaos system is generally a three-dimensional chaos system; a construction method and circuit is not provided for the four-dimensional hyper-chaos system having an automatic switching function. According to the Yang-Chen system based automatic switching hyper-chaos system construction method, a two-system automatic switching hyper-chaos system is formed based on the three-dimensional Yang-Chen system through increase of the one-dimensional variable in twice and feedback of the increased variable to a second equation of the three-dimensional Yang-Chen system, a new method for constructing the two-system automatic switching hyper-chaos system is provided, the construction method is achieved through a simulation circuit, and a new selective scheme is provided for application of the two-system automatic switching hyper-chaos system into the engineering fields such as the communication field.

Description

Automatic switchover hyperchaotic system building method and analog circuit based on Yang-Chen system

Technical field

The present invention relates to a hyperchaos switched system and analog circuit, particularly 2 system automatic switchover hyperchaotic system building method and analog circuits based on Yang-Chen system.

Background technology

Existing hyperchaotic system is generally on the basis of three-dimensional chaotic system, by once increasing one dimension variable, and increased variable feedback on original three-dimensional chaotic system, form four-dimensional hyperchaotic system, and existing automatically switched chaotic system is generally three-dimensional chaotic system, building method and the circuit with the four-dimensional hyperchaotic system of automatic switching function also do not propose, and this is the deficiencies in the prior art parts.The present invention is on the basis of three-dimensional Yang-Chen chaos system, by twice increase one dimension variable, and increased variable feedback to second equation of three-dimensional Yang-Chen chaos system, thereby 2 system automatic switchover hyperchaotic system are formed, the new method of a kind of structure 2 system automatic switchover hyperchaotic system has been proposed, and realize with analog circuit, for being applied to the engineering fields such as communication, 2 system automatic switchover hyperchaotic system provide a kind of new selection scheme.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of 2 system automatic switchover hyperchaotic system and analog circuits based on Yang-Chen system, and the present invention adopts following technological means to realize goal of the invention:

1, the automatic switchover hyperchaotic system building method based on Yang-Chen system, is characterized in that, comprises the following steps:

(1) three-dimensional Yang-Chen chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\end{array}\right.a=35,b=3,c=35---i$

(2) on the basis of three-dimensional Yang-Chen chaos system i, increase a differential equation dw/dt=-kx, and w is fed back on second equation of system i, obtain chaos system ii

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{kx}\end{array}\right.a=35,b=3,c=35,k=8---\mathrm{ii}$

(3) on the basis of three-dimensional Yang-Chen chaos system i, increase a differential equation dw/dt=-ky, and w is fed back on second equation of system i, obtain chaos system iii

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{ky}\end{array}\right.a=35,b=3,c=35,k=8---\mathrm{iii}$

(4) by ii and a kind of automatic hyperchaotic system iv based on Yang-Chen system of iii structure be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cy}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{kf}\left(x\right)\end{array}\right.a=35,b=3,c=35,k=8,f\left(x\right)=\left\{\begin{array}{cc}x,& x>0\\ y,& x\≤0\end{array}\right.---\mathrm{iv}$

(5) according to the automatic hyperchaotic system constructing analog circuit based on Yang-Chen system, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form anti-phase adder and inverting integrator, utilize multiplier U4 and multiplier U5 to realize multiplying, utilize operational amplifier U3 and resistance R 15, R16 forms comparator, obtain a comparative level, as the input control signal of analog switch U6, utilize analog switch U6 to realize the selection output of analog signal, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and multiplier U5 adopt AD633JN, described analog switch U6 adopts ADG888,

Described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3, multiplier U4, multiplier U5 and analog switch U6, described operational amplifier U2 connects multiplier U4, multiplier U5, analog switch U6 and operational amplifier U1, described operational amplifier U3 concatenation operation amplifier U1 and analog switch U6, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described analog switch U6 concatenation operation amplifier U1;

The 1st pin of described operational amplifier U1 joins by resistance R 7 and the 2nd pin, join by resistance R 8 and the 6th pin, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 2 and the 7th pin, the 7th pin meets output y, join by resistance R 2 and the 13rd pin, connect the 3rd pin of multiplier U5, connect the 12nd pin of analog switch U6, the 8th pin output x, join by resistance R 6 and the 2nd pin, join by capacitor C 1 and the 9th pin, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U5, connect the 2nd pin of operational amplifier U3, connect the 10th pin of analog switch U6, join by resistance R 4 and the 9th pin, the 13rd pin joins by resistance R 3 and the 14th pin, the 14th pin joins by resistance R 5 and the 9th pin,

The 1st, 2 pins of described operational amplifier U2 are unsettled, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 4 and the 7th pin, the 7th pin output w, join by resistance R 1 and the 2nd pin of operational amplifier U1, the 8th pin meets output z, connect the 3rd pin of multiplier U4, join by resistance R 13 and the 9th pin, the 9th pin joins by capacitor C 3 and the 8th pin, the 13rd pin joins by resistance R 11 and the 14th pin, and the 14th pin joins by resistance R 12 and the 9th pin;

The 1st pin of described operational amplifier U3 is by the series connection ground connection of resistance R 15 and R16, join by resistance R 15 and the 9th pin of analog switch U6, the 8th pin of the 2nd pin and operational amplifier U1 joins, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, and the the the 6th, 7,8,9,13,14 pins are unsettled;

The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described multiplier U5 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects operational amplifier U2 the 13rd pin by resistance R 10, and the 8th pin meets VCC.

The 1st pin of described analog switch U6 meets VCC, 2nd, 3,4,5,6,7,8,13,14,15 pins are unsettled, the 8th pin of the 10th pin and operational amplifier U1 joins, the 11st pin joins by resistance R 14 and the 6th pin of operational amplifier U2, the 7th pin of the 12nd pin and operational amplifier U1 joins, the 16th pin ground connection.

2, the analog circuit of the automatic hyperchaotic system based on Yang-Chen system, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form anti-phase adder and inverting integrator, utilize multiplier U4 and multiplier U5 to realize multiplying, utilize operational amplifier U3 and resistance R 17, R18 forms comparator, obtain a comparative level, as the input control signal of analog switch U6, utilize analog switch U6 to realize the selection output of analog signal, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and multiplier U5 adopt AD633JN, described analog switch U6 adopts ADG888,

Described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3, multiplier U4, multiplier U5 and analog switch U6, described operational amplifier U2 connects multiplier U4, multiplier U5, analog switch U6 and operational amplifier U1, described operational amplifier U3 concatenation operation amplifier U1 and analog switch U6, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described analog switch U6 concatenation operation amplifier U1;

The 1st pin of described operational amplifier U1 joins by resistance R 7 and the 2nd pin, join by resistance R 8 and the 6th pin, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 2 and the 7th pin, the 7th pin meets output y, join by resistance R 2 and the 13rd pin, connect the 3rd pin of multiplier U5, connect the 12nd pin of analog switch U6, the 8th pin output x, join by resistance R 6 and the 2nd pin, join by capacitor C 1 and the 9th pin, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U5, connect the 2nd pin of operational amplifier U3, connect the 10th pin of analog switch U6, join by resistance R 4 and the 9th pin, the 13rd pin joins by resistance R 3 and the 14th pin, the 14th pin joins by resistance R 5 and the 9th pin,

The 1st, 2 pins of described operational amplifier U2 are unsettled, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 4 and the 7th pin, the 7th pin output w, join by resistance R 1 and the 2nd pin of operational amplifier U1, the 8th pin meets output z, connect the 3rd pin of multiplier U4, join by resistance R 13 and the 9th pin, the 9th pin joins by capacitor C 3 and the 8th pin, the 13rd pin joins by resistance R 11 and the 14th pin, and the 14th pin joins by resistance R 12 and the 9th pin;

The 1st pin of described operational amplifier U3 is by the series connection ground connection of resistance R 15 and R16, join by resistance R 15 and the 9th pin of analog switch U6, the 8th pin of the 2nd pin and operational amplifier U1 joins, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, and the the the 6th, 7,8,9,13,14 pins are unsettled;

The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described multiplier U5 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects operational amplifier U2 the 13rd pin by resistance R 10, and the 8th pin meets VCC.

The 1st pin of described analog switch U6 meets VCC, 2nd, 3,4,5,6,7,8,13,14,15 pins are unsettled, the 8th pin of the 10th pin and operational amplifier U1 joins, the 11st pin joins by resistance R 14 and the 6th pin of operational amplifier U2, the 7th pin of the 12nd pin and operational amplifier U1 joins, the 16th pin ground connection.

Beneficial effect

The present invention is on the basis of three-dimensional Yang-Chen chaos system, by twice increase one dimension variable, and increased variable feedback to second equation of three-dimensional L ü chaos system, thereby 2 system automatic switchover hyperchaotic system are formed, the new method of a kind of structure 2 system automatic switchover hyperchaotic system has been proposed, and realize with analog circuit, for being applied to the engineering fields such as communication, 2 system automatic switchover hyperchaotic system provide a kind of new selection scheme.

Brief description of the drawings

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 and Fig. 3 are the actual connection layout of circuit of the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, referring to Fig. 1-Fig. 3.

1, the automatic switchover hyperchaotic system building method based on Yang-Chen system, is characterized in that, comprises the following steps:

(1) three-dimensional Yang-Chen chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\end{array}\right.a=35,b=3,c=35---i$

(2) on the basis of three-dimensional Yang-Chen chaos system i, increase a differential equation dw/dt=-kx, and w is fed back on second equation of system i, obtain chaos system ii

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{kx}\end{array}\right.a=35,b=3,c=35,k=8---\mathrm{ii}$

(3) on the basis of three-dimensional Yang-Chen chaos system i, increase a differential equation dw/dt=-ky, and w is fed back on second equation of system i, obtain chaos system iii

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{ky}\end{array}\right.a=35,b=3,c=35,k=8---\mathrm{iii}$

(4) by ii and a kind of automatic hyperchaotic system iv based on Yang-Chen system of iii structure be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cy}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{kf}\left(x\right)\end{array}\right.a=35,b=3,c=35,k=8,f\left(x\right)=\left\{\begin{array}{cc}x,& x>0\\ y,& x\≤0\end{array}\right.---\mathrm{iv}$

(5) according to the automatic hyperchaotic system constructing analog circuit based on Yang-Chen system, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form anti-phase adder and inverting integrator, utilize multiplier U4 and multiplier U5 to realize multiplying, utilize operational amplifier U3 and resistance R 15, R16 forms comparator, obtain a comparative level, as the input control signal of analog switch U6, utilize analog switch U6 to realize the selection output of analog signal, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and multiplier U5 adopt AD633JN, described analog switch U6 adopts ADG888,

Described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3, multiplier U4, multiplier U5 and analog switch U6, described operational amplifier U2 connects multiplier U4, multiplier U5, analog switch U6 and operational amplifier U1, described operational amplifier U3 concatenation operation amplifier U1 and analog switch U6, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described analog switch U6 concatenation operation amplifier U1;

The 1st pin of described operational amplifier U1 joins by resistance R 7 and the 2nd pin, join by resistance R 8 and the 6th pin, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 2 and the 7th pin, the 7th pin meets output y, join by resistance R 2 and the 13rd pin, connect the 3rd pin of multiplier U5, connect the 12nd pin of analog switch U6, the 8th pin output x, join by resistance R 6 and the 2nd pin, join by capacitor C 1 and the 9th pin, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U5, connect the 2nd pin of operational amplifier U3, connect the 10th pin of analog switch U6, join by resistance R 4 and the 9th pin, the 13rd pin joins by resistance R 3 and the 14th pin, the 14th pin joins by resistance R 5 and the 9th pin,

The 1st, 2 pins of described operational amplifier U2 are unsettled, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 4 and the 7th pin, the 7th pin output w, join by resistance R 1 and the 2nd pin of operational amplifier U1, the 8th pin meets output z, connect the 3rd pin of multiplier U4, join by resistance R 13 and the 9th pin, the 9th pin joins by capacitor C 3 and the 8th pin, the 13rd pin joins by resistance R 11 and the 14th pin, and the 14th pin joins by resistance R 12 and the 9th pin;

The 1st pin of described operational amplifier U3 is by the series connection ground connection of resistance R 15 and R16, join by resistance R 15 and the 9th pin of analog switch U6, the 8th pin of the 2nd pin and operational amplifier U1 joins, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, and the the the 6th, 7,8,9,13,14 pins are unsettled;

The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described multiplier U5 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects operational amplifier U2 the 13rd pin by resistance R 10, and the 8th pin meets VCC.

The 1st pin of described analog switch U6 meets VCC, 2nd, 3,4,5,6,7,8,13,14,15 pins are unsettled, the 8th pin of the 10th pin and operational amplifier U1 joins, the 11st pin joins by resistance R 14 and the 6th pin of operational amplifier U2, the 7th pin of the 12nd pin and operational amplifier U1 joins, the 16th pin ground connection.

2, the analog circuit of the automatic hyperchaotic system based on Yang-Chen system, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form anti-phase adder and inverting integrator, utilize multiplier U4 and multiplier U5 to realize multiplying, utilize operational amplifier U3 and resistance R 17, R18 forms comparator, obtain a comparative level, as the input control signal of analog switch U6, utilize analog switch U6 to realize the selection output of analog signal, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and multiplier U5 adopt AD633JN, described analog switch U6 adopts ADG888,

Described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3, multiplier U4, multiplier U5 and analog switch U6, described operational amplifier U2 connects multiplier U4, multiplier U5, analog switch U6 and operational amplifier U1, described operational amplifier U3 concatenation operation amplifier U1 and analog switch U6, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described analog switch U6 concatenation operation amplifier U1;

The 1st pin of described operational amplifier U1 joins by resistance R 7 and the 2nd pin, join by resistance R 8 and the 6th pin, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 2 and the 7th pin, the 7th pin meets output y, join by resistance R 2 and the 13rd pin, connect the 3rd pin of multiplier U5, connect the 12nd pin of analog switch U6, the 8th pin output x, join by resistance R 6 and the 2nd pin, join by capacitor C 1 and the 9th pin, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U5, connect the 2nd pin of operational amplifier U3, connect the 10th pin of analog switch U6, join by resistance R 4 and the 9th pin, the 13rd pin joins by resistance R 3 and the 14th pin, the 14th pin joins by resistance R 5 and the 9th pin,

The 1st, 2 pins of described operational amplifier U2 are unsettled, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 4 and the 7th pin, the 7th pin output w, join by resistance R 1 and the 2nd pin of operational amplifier U1, the 8th pin meets output z, connect the 3rd pin of multiplier U4, join by resistance R 13 and the 9th pin, the 9th pin joins by capacitor C 3 and the 8th pin, the 13rd pin joins by resistance R 11 and the 14th pin, and the 14th pin joins by resistance R 12 and the 9th pin;

The 1st pin of described operational amplifier U3 is by the series connection ground connection of resistance R 15 and R16, join by resistance R 15 and the 9th pin of analog switch U6, the 8th pin of the 2nd pin and operational amplifier U1 joins, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, and the the the 6th, 7,8,9,13,14 pins are unsettled;

The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described multiplier U5 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects operational amplifier U2 the 13rd pin by resistance R 10, and the 8th pin meets VCC.

The 1st pin of described analog switch U6 meets VCC, 2nd, 3,4,5,6,7,8,13,14,15 pins are unsettled, the 8th pin of the 10th pin and operational amplifier U1 joins, the 11st pin joins by resistance R 14 and the 6th pin of operational amplifier U2, the 7th pin of the 12nd pin and operational amplifier U1 joins, the 16th pin ground connection.

Resistance R 1=R15=100k Ω in circuit, R3=R5=R7=R8=R11=R12=10k Ω, R2=R4=R6=2.85k Ω, R9=R10=1k Ω, R13=33.3k Ω, R14=12.5k Ω, R16=80k Ω, C1=C2=C3=C4=10nF.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art make in essential scope of the present invention, also belong to protection scope of the present invention.

Claims (2)

1. the automatic switchover hyperchaotic system building method based on Yang-Chen system, is characterized in that, comprises the following steps:

(1) three-dimensional Yang-Chen chaos system i is:

$\begin{array}{ccc}\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\end{array}\right.& i& a=35,b=3,c=35\end{array}$

(2) on the basis of three-dimensional Yang-Chen chaos system i, increase a differential equation dw/dt=-kx, and w is fed back on second equation of system i, obtain chaos system ii

$\begin{array}{ccc}\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{kx}\end{array}\right.& \mathrm{ii}& a=35,b=3,c=35,k=8\end{array}$

(3) on the basis of three-dimensional Yang-Chen chaos system i, increase a differential equation dw/dt=-ky, and w is fed back on second equation of system i, obtain chaos system iii

$\begin{array}{ccc}\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{ky}\end{array}\right.& \mathrm{iii}& a=35,b=3,c=35,k=8\end{array}$

(4) by ii and a kind of automatic hyperchaotic system iv based on Yang-Chen system of iii structure be:

$\begin{array}{cccc}\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cy}-\mathrm{xz}+w\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{kf}\left(x\right)\end{array}\right.& \mathrm{iv}& a=35,b=3,c=35,k=8& f\left(x\right)=\left\{\begin{array}{c}x,x>0\\ y,x\≤0\end{array}\right.\end{array}$

(5) according to the automatic hyperchaotic system constructing analog circuit based on Yang-Chen system, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form anti-phase adder and inverting integrator, utilize multiplier U4 and multiplier U5 to realize multiplying, utilize operational amplifier U3 and resistance R 15, R16 forms comparator, obtain a comparative level, as the input control signal of analog switch U6, utilize analog switch U6 to realize the selection output of analog signal, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and multiplier U5 adopt AD633JN, described analog switch U6 adopts ADG888,

Described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3, multiplier U4, multiplier U5 and analog switch U6, described operational amplifier U2 connects multiplier U4, multiplier U5, analog switch U6 and operational amplifier U1, described operational amplifier U3 concatenation operation amplifier U1 and analog switch U6, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described analog switch U6 concatenation operation amplifier U1;

The 1st pin of described operational amplifier U1 joins by resistance R 7 and the 2nd pin, join by resistance R 8 and the 6th pin, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 2 and the 7th pin, the 7th pin meets output y, join by resistance R 2 and the 13rd pin, connect the 3rd pin of multiplier U5, connect the 12nd pin of analog switch U6, the 8th pin output x, join by resistance R 6 and the 2nd pin, join by capacitor C 1 and the 9th pin, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U5, connect the 2nd pin of operational amplifier U3, connect the 10th pin of analog switch U6, join by resistance R 4 and the 9th pin, the 13rd pin joins by resistance R 3 and the 14th pin, the 14th pin joins by resistance R 5 and the 9th pin,

The 1st, 2 pins of described operational amplifier U2 are unsettled, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 4 and the 7th pin, the 7th pin output w, join by resistance R 1 and the 2nd pin of operational amplifier U1, the 8th pin meets output z, connect the 3rd pin of multiplier U4, join by resistance R 13 and the 9th pin, the 9th pin joins by capacitor C 3 and the 8th pin, the 13rd pin joins by resistance R 11 and the 14th pin, and the 14th pin joins by resistance R 12 and the 9th pin;

The 1st pin of described operational amplifier U3 is by the series connection ground connection of resistance R 15 and R16, join by resistance R 15 and the 9th pin of analog switch U6, the 8th pin of the 2nd pin and operational amplifier U1 joins, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, and the the the 6th, 7,8,9,13,14 pins are unsettled;

The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described multiplier U5 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects operational amplifier U2 the 13rd pin by resistance R 10, and the 8th pin meets VCC.

The 1st pin of described analog switch U6 meets VCC, 2nd, 3,4,5,6,7,8,13,14,15 pins are unsettled, the 8th pin of the 10th pin and operational amplifier U1 joins, the 11st pin joins by resistance R 14 and the 6th pin of operational amplifier U2, the 7th pin of the 12nd pin and operational amplifier U1 joins, the 16th pin ground connection.

2. the analog circuit of the automatic hyperchaotic system based on Yang-Chen system, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form anti-phase adder and inverting integrator, utilize multiplier U4 and multiplier U5 to realize multiplying, utilize operational amplifier U3 and resistance R 17, R18 forms comparator, obtain a comparative level, as the input control signal of analog switch U6, utilize analog switch U6 to realize the selection output of analog signal, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and multiplier U5 adopt AD633JN, described analog switch U6 adopts ADG888,

Described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3, multiplier U4, multiplier U5 and analog switch U6, described operational amplifier U2 connects multiplier U4, multiplier U5, analog switch U6 and operational amplifier U1, described operational amplifier U3 concatenation operation amplifier U1 and analog switch U6, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described multiplier U4 concatenation operation amplifier U1 and operational amplifier U2, described analog switch U6 concatenation operation amplifier U1;

The 1st pin of described operational amplifier U1 joins by resistance R 7 and the 2nd pin, join by resistance R 8 and the 6th pin, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 2 and the 7th pin, the 7th pin meets output y, join by resistance R 2 and the 13rd pin, connect the 3rd pin of multiplier U5, connect the 12nd pin of analog switch U6, the 8th pin output x, join by resistance R 6 and the 2nd pin, join by capacitor C 1 and the 9th pin, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U5, connect the 2nd pin of operational amplifier U3, connect the 10th pin of analog switch U6, join by resistance R 4 and the 9th pin, the 13rd pin joins by resistance R 3 and the 14th pin, the 14th pin joins by resistance R 5 and the 9th pin,

The 1st, 2 pins of described operational amplifier U2 are unsettled, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin joins by capacitor C 4 and the 7th pin, the 7th pin output w, join by resistance R 1 and the 2nd pin of operational amplifier U1, the 8th pin meets output z, connect the 3rd pin of multiplier U4, join by resistance R 13 and the 9th pin, the 9th pin joins by capacitor C 3 and the 8th pin, the 13rd pin joins by resistance R 11 and the 14th pin, and the 14th pin joins by resistance R 12 and the 9th pin;

The 1st pin of described operational amplifier U3 is by the series connection ground connection of resistance R 15 and R16, join by resistance R 15 and the 9th pin of analog switch U6, the 8th pin of the 2nd pin and operational amplifier U1 joins, 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, and the the the 6th, 7,8,9,13,14 pins are unsettled;

The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described multiplier U5 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects operational amplifier U2 the 13rd pin by resistance R 10, and the 8th pin meets VCC.

The 1st pin of described analog switch U6 meets VCC, 2nd, 3,4,5,6,7,8,13,14,15 pins are unsettled, the 8th pin of the 10th pin and operational amplifier U1 joins, the 11st pin joins by resistance R 14 and the 6th pin of operational amplifier U2, the 7th pin of the 12nd pin and operational amplifier U1 joins, the 16th pin ground connection.