CN103780371B - Lv chaotic system switching method and circuit containing x<2> with different fractional orders - Google Patents
Lv chaotic system switching method and circuit containing x<2> with different fractional orders Download PDFInfo
- Publication number
- CN103780371B CN103780371B CN201410063139.0A CN201410063139A CN103780371B CN 103780371 B CN103780371 B CN 103780371B CN 201410063139 A CN201410063139 A CN 201410063139A CN 103780371 B CN103780371 B CN 103780371B
- Authority
- CN
- China
- Prior art keywords
- pin
- operational amplifier
- resistance
- capacitor
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000000739 chaotic effect Effects 0.000 title abstract description 6
- 239000003990 capacitor Substances 0.000 claims abstract description 109
- 238000013459 approach Methods 0.000 description 2
- 101000726523 Homo sapiens Putative gap junction epsilon-1 protein Proteins 0.000 description 1
- 101000726524 Mus musculus Gap junction epsilon-1 protein Proteins 0.000 description 1
- 102100030593 Putative gap junction epsilon-1 protein Human genes 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 102220414581 c.33A>G Human genes 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007634 remodeling Methods 0.000 description 1
- 102220228145 rs1064794513 Human genes 0.000 description 1
- 102220264750 rs1305455942 Human genes 0.000 description 1
- 102220012898 rs397516346 Human genes 0.000 description 1
- 102220095236 rs876658436 Human genes 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims (2)
- A fractional-order different containing x 2l ü chaos switched system method, it is characterized in that being, comprise the following steps:(1) containing x 2the equation of L ü chaos system i be:(2) 0.9 rank are containing x 2the equation of L ü chaos system ii be:(3) 0.1 rank are containing x 2the equation of L ü chaos system iii be:(4) structure switching function q=f (x), wherein the expression formula iv of f (x) is:(5) by ii, iii and iv construct a kind of fractional-order different containing x 2l ü chaos switched system v be:(6) according to fractional-order different containing x 2l ü chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt the operational amplifier that model is LF347D, described multiplier U3 and multiplier U4 adopt the multiplier that model is AD633JN, described analog switch U5 adopts the analog switch that model is ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, by resistance R 7 and the 6th pin of operational amplifier U1, join, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, by resistance R 4, connect the 2nd pin of operational amplifier U1, the 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, meet the 1st of multiplier U4, 3 pins, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, by resistance R 6, connect the 9th pin of operational amplifier U1,The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, by R13, meet the 8th of analog switch U5, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, by resistance R 12, connect the 9th pin of operational amplifier U2,The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;The 1st, 3 pins of described multiplier U4 connect the 8th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
- A fractional-order different containing x 2l ü chaos switched system circuit, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt the operational amplifier that model is LF347D, described multiplier U3 and multiplier U4 adopt the multiplier that model is AD633JN, described analog switch U5 adopts the analog switch that model is ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, by resistance R 7 and the 6th pin of operational amplifier U1, join, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, by resistance R 4, connect the 2nd pin of operational amplifier U1, the 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, meet the 1st of multiplier U4, 3 pins, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, by resistance R 6, connect the 9th pin of operational amplifier U1,The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, by R13, meet the 8th of analog switch U5, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, by resistance R 12, connect the 9th pin of operational amplifier U2,The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;The 1st, 3 pins of described multiplier U4 connect the 8th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410063139.0A CN103780371B (en) | 2014-02-22 | 2014-02-22 | Lv chaotic system switching method and circuit containing x<2> with different fractional orders |
PCT/CN2014/000400 WO2015123793A1 (en) | 2014-02-22 | 2014-04-14 | Lü CHAOTIC SYSTEM SWITCHING METHOD AND CIRCUIT CONTAINING x2 WITH DIFFERENTFRACTIONAL ORDERS |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410063139.0A CN103780371B (en) | 2014-02-22 | 2014-02-22 | Lv chaotic system switching method and circuit containing x<2> with different fractional orders |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103780371A CN103780371A (en) | 2014-05-07 |
CN103780371B true CN103780371B (en) | 2014-12-10 |
Family
ID=50572246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410063139.0A Active CN103780371B (en) | 2014-02-22 | 2014-02-22 | Lv chaotic system switching method and circuit containing x<2> with different fractional orders |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN103780371B (en) |
WO (1) | WO2015123793A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104270241A (en) * | 2014-09-19 | 2015-01-07 | 胡春华 | 0.3-orderLu chaotic system circuit obtaining method based on chain type fractional order integral circuit module |
CN104468075B (en) * | 2014-11-11 | 2015-08-19 | 国家电网公司 | 0.3 rank mixed type fractional order integration circuit module and based on it containing x side L ü chaos system circuit realiration |
CN104393984B (en) * | 2014-11-11 | 2015-09-30 | 国家电网公司 | A kind of 0.6 rank mixed type fractional order integration circuit arrangement |
CN104468084B (en) * | 2014-12-14 | 2015-12-30 | 国家电网公司 | A kind of 0.8 T-shaped fractional order integration circuit module in rank |
CN104486062B (en) * | 2014-12-14 | 2015-09-16 | 国网山东省电力公司泰安供电公司 | Based on the Liu chaos system circuit of the 0.4 T-shaped fractional order integration circuit module in rank |
CN104468086B (en) * | 2014-12-14 | 2016-02-10 | 国网新疆电力公司电力科学研究院 | A kind of 0.3 T-shaped fractional order integration circuit arrangement in rank |
CN105262581A (en) * | 2015-09-09 | 2016-01-20 | 胡春华 | Lu-system-based adaptive synchronization method and circuit for hyperchaotic system capable of automatically switching two systems |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102946308A (en) * | 2012-11-19 | 2013-02-27 | 湖南大学 | Novel fractional order hyperchaos circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102497263B (en) * | 2011-11-18 | 2014-06-04 | 滨州学院 | Method for realizing integer order and fractional order automatic switching chaotic system and analog circuit |
CN102385659B (en) * | 2011-12-13 | 2012-11-28 | 滨州学院 | Method for realizing fractional-order three-system automatic-switchover chaotic system and analog circuit |
CN102904708B (en) * | 2012-09-27 | 2014-09-10 | 滨州学院 | Method for automatically switching fractional-order chaotic system by four systems based on Lu-type system and analog circuit |
CN103368723B (en) * | 2013-07-03 | 2017-02-15 | 淄博职业学院 | Fractional order four-system automatic switching chaotic system method and analog circuit |
CN103532698B (en) * | 2013-10-25 | 2016-08-17 | 南京森林警察学院 | The method realizing Sliding mode synchronization secret communication based on four-dimensional automatically switched chaotic system |
-
2014
- 2014-02-22 CN CN201410063139.0A patent/CN103780371B/en active Active
- 2014-04-14 WO PCT/CN2014/000400 patent/WO2015123793A1/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102946308A (en) * | 2012-11-19 | 2013-02-27 | 湖南大学 | Novel fractional order hyperchaos circuit |
Also Published As
Publication number | Publication date |
---|---|
WO2015123793A1 (en) | 2015-08-27 |
CN103780371A (en) | 2014-05-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103780371B (en) | Lv chaotic system switching method and circuit containing x<2> with different fractional orders | |
CN103856317A (en) | Method and circuit for switching classic Lorenz type chaotic system with different fractional orders | |
CN103780373A (en) | Classic chen chaotic system switching method and circuit with different fractional orders | |
CN104202143B (en) | Based on the four-dimension of five chaos systems the simplest without the analog circuit of balance point hyperchaotic system | |
CN203872185U (en) | Lorenz-type chaotic switching system circuit with square of y and different fractional orders | |
CN203813801U (en) | Liu chaotic switching system circuit including xy with different fractional orders | |
CN104202140A (en) | Four-dimensional balance point-free hyperchaotic system based on five-simplest chaotic system, and analogue circuit | |
CN103684746B (en) | Construction method of four-dimensional hyperchaotic system without balance points and simulation circuit | |
CN103731256B (en) | Three-dimensional non-balance-point chaotic system and artificial circuit implementation method | |
CN203896361U (en) | Switching circuit of Lyv chaotic system with different fractional orders and containing x power | |
CN104184575A (en) | Rikitake-system-based four-dimensional non-balance-point hyperchaotic system and simulation circuit | |
CN104539414A (en) | Simplest five-item chaotic system and circuit implementation method thereof | |
CN103812639A (en) | Method and circuit for switching classical Liu (line interface unit) chaos system with different fraction orders | |
CN103812640A (en) | Method and circuit for switching Liu (line interface unit) chaos system with different fraction orders and xy | |
CN105553640A (en) | Construction method for balance-point-free four-dimensional hyper-chaotic system based on Rikitake system | |
CN104092532B (en) | Balance-point-free hyper-chaos system based on three-dimensional chaos system, and analogue circuit | |
CN103780374A (en) | Chen chaotic system switching method and circuit containing x<2> with different fractional orders | |
CN203872189U (en) | Liu chaotic switching system circuit with xy and different fractional orders | |
CN103856319A (en) | Method and circuit for switching Lorenz type chaotic system provided with different fractional orders and x2 | |
CN103780370A (en) | Zhang chaotic system switching method and circuit with different fractional orders | |
CN103997400B (en) | Method and circuit for different-fractional-order y<2>-containing Liu chaotic switching system | |
CN203933652U (en) | The classical l ü chaos switched system circuit that a kind of fractional-order is different | |
CN103856318A (en) | Method and circuit for switching Qi type chaotic system provided with different fractional orders and y2 | |
CN103780372A (en) | Chen chaotic system switching method and circuit containing y<2> with different fractional orders | |
CN103916232A (en) | Switching method and circuit of Lu chaotic system with different fractional orders and y<2> |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: GUANGDONG HUABO ENTERPRISE MANAGEMENT CONSULTING C Free format text: FORMER OWNER: BINZHOU COLLEGE Effective date: 20150528 Free format text: FORMER OWNER: WANG ZHONGLIN Effective date: 20150528 |
|
C41 | Transfer of patent application or patent right or utility model | ||
C53 | Correction of patent for invention or patent application | ||
CB03 | Change of inventor or designer information |
Inventor after: Hu Lichun Inventor before: Wang Zhonglin |
|
COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: WANG ZHONGLIN TO: HU LICHUN Free format text: CORRECT: ADDRESS; FROM: 256603 BINZHOU, SHANDONG PROVINCE TO: 510640 GUANGZHOU, GUANGDONG PROVINCE |
|
TR01 | Transfer of patent right |
Effective date of registration: 20150528 Address after: 510640 Guangdong city of Guangzhou province Tianhe District gold Yinglu No. 1 was 1106 room two Patentee after: Guangdong Huabo Enterprise Management Consulting Co., Ltd. Address before: 256603 the Yellow River Road, Shandong, No. five, No. 391, Binzhou Patentee before: Binzhou College Patentee before: Wang Zhonglin |
|
C41 | Transfer of patent application or patent right or utility model | ||
CB03 | Change of inventor or designer information |
Inventor after: Li Kailin Inventor after: Li Zhiqiang Inventor after: Yu Xinmei Inventor after: Quan Jun Inventor before: Hu Lichun |
|
COR | Change of bibliographic data | ||
TR01 | Transfer of patent right |
Effective date of registration: 20151118 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: Aksu electric company of Guo Wang Xinjiang power company Address before: 510640 Guangdong city of Guangzhou province Tianhe District gold Yinglu No. 1 was 1106 room two Patentee before: Guangdong Huabo Enterprise Management Consulting Co., Ltd. |