CN203933652U - The classical l ü chaos switched system circuit that a kind of fractional-order is different - Google Patents
The classical l ü chaos switched system circuit that a kind of fractional-order is different Download PDFInfo
- Publication number
- CN203933652U CN203933652U CN201420112698.1U CN201420112698U CN203933652U CN 203933652 U CN203933652 U CN 203933652U CN 201420112698 U CN201420112698 U CN 201420112698U CN 203933652 U CN203933652 U CN 203933652U
- Authority
- CN
- China
- Prior art keywords
- pin
- operational amplifier
- resistance
- multiplier
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
Abstract
The utility model provides a kind of fractional-order different classical L ü chaos switched system circuit, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2, the novel commutation circuit of a novel chaos system has been proposed, the type that this switches increase chaos system and this chaos system are applied to engineering practice provides a kind of new approaches.
Description
Technical field
The utility model relates to a chaos system and circuit is realized, the particularly different classical L ü chaos switched system circuit of a kind of fractional-order.
Background technology
At present, the main circuit of the switching chaos system that oneself has to comprise different linear terms in chaos system or nonlinear terms between switching, and fractional order form based on these 2 kinds of switch modes, commutation circuit about the chaotic systems with fractional order of different orders is not also suggested, the utility model proposes the different classical L ü chaos switched system circuit of a kind of fractional-order, the utility model proposes the novel commutation circuit of a novel chaos system, the type that this switches increase chaos system and this chaos system are applied to engineering practice provides a kind of new approaches.
Summary of the invention
The technical problems to be solved in the utility model is to provide the different classical L ü chaos switched system circuit of a kind of fractional-order, and the utility model adopts following technological means to realize goal of the invention:
The classical L ü chaos switched system circuit that fractional-order is different, is characterized in that being, comprises the following steps:
(1) equation of L ü chaos system i is:
The equation of (2) 0.9 rank L ü chaos system ii is:
The equation of (3) 0.1 rank L ü chaos system iii is:
(4) structure switching function q=f (x), wherein the expression formula iv of f (x) is:
(5) constructing the different L ü chaos switched system v of a kind of fractional-order by ii, iii and iv is:
(6) the L ü chaos switched system v constructing analog Circuits System different according to fractional-order, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,
The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, connect the 2nd pin of operational amplifier U1 by resistance R 4, connect the 3rd pin of multiplier U4, the 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,
The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,
The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;
The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, the 8th pin meets VCC;
The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
The beneficial effects of the utility model are: proposed the novel commutation circuit of a novel chaos system, the type that this switches increase chaos system and this chaos system are applied to engineering practice provides a kind of new approaches.
Brief description of the drawings
Fig. 1 is the circuit connection structure schematic diagram of the utility model preferred embodiment.
Fig. 2 and Fig. 3 are the actual connection layout of circuit of the present utility model.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, the utility model is further described in detail, referring to Fig. 1-Fig. 3.
The classical L ü chaos switched system circuit that fractional-order is different, is characterized in that being, comprises the following steps:
(1) equation of L ü chaos system i is:
The equation of (2) 0.9 rank L ü chaos system ii is:
The equation of (3) 0.1 rank L ü chaos system iii is:
(4) structure switching function q=f (x), wherein the expression formula iv of f (x) is:
(5) constructing the different L ü chaos switched system v of a kind of fractional-order by ii, iii and iv is:
(6) the L ü chaos switched system v constructing analog Circuits System different according to fractional-order, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,
The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, connect the 2nd pin of operational amplifier U1 by resistance R 4, connect the 3rd pin of multiplier U4, the 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,
The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,
The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;
The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, the 8th pin meets VCC;
The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
Resistance R 1=R3=R6=R7=R10=R12=10k Ω in circuit, R8=R9=1k Ω, R4=4.5k Ω, R2=R5=2.7k Ω, R11=33.3k Ω, R13=100k Ω, R14=80k Ω, Rx11=Ry11=Rz11=62.84M Ω, Rx12=Ry12=Rz12=250k Ω, Rx13=Ry13=Rz13=2.5k Ω, Rx21=Ry21=Rz21=0.636M Ω, Rx22=Ry22=Rz22=0.3815M Ω, Rx23=Ry23=Rz23=0.5672M Ω, Cx11=Cy11=Cz11=1.2 μ F, Cx12=Cy12=Cz13=1.8 μ F, Cx13=Cy13=Cz13=1.1 μ F, Cx21=Cy21=Cz21=15.75 μ F, Cx22=Cy22=Cz22=0.1575 μ F, Cx23=Cy23=Cz23=633.5nF.
Claims (1)
1. the classical L ü chaos switched system circuit that fractional-order is different, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,
The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, connect the 2nd pin of operational amplifier U1 by resistance R 4, connect the 3rd pin of multiplier U4, the 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, connect the 1st pin of multiplier U4, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,
The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,
The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;
The 1st pin of described multiplier U4 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, the 8th pin meets VCC;
The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420112698.1U CN203933652U (en) | 2014-03-13 | 2014-03-13 | The classical l ü chaos switched system circuit that a kind of fractional-order is different |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420112698.1U CN203933652U (en) | 2014-03-13 | 2014-03-13 | The classical l ü chaos switched system circuit that a kind of fractional-order is different |
Publications (1)
Publication Number | Publication Date |
---|---|
CN203933652U true CN203933652U (en) | 2014-11-05 |
Family
ID=51829402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201420112698.1U Expired - Fee Related CN203933652U (en) | 2014-03-13 | 2014-03-13 | The classical l ü chaos switched system circuit that a kind of fractional-order is different |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN203933652U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105721137A (en) * | 2014-12-14 | 2016-06-29 | 胡春华 | 0.7-order Lu chaotic system circuit based on T type fractional order integral circuit |
-
2014
- 2014-03-13 CN CN201420112698.1U patent/CN203933652U/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105721137A (en) * | 2014-12-14 | 2016-06-29 | 胡春华 | 0.7-order Lu chaotic system circuit based on T type fractional order integral circuit |
CN105721137B (en) * | 2014-12-14 | 2019-02-22 | 重庆荣凯川仪仪表有限公司 | The 0.7 rank L ü chaos system circuit based on T-type fractional order integration circuit module |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103780371B (en) | Lv chaotic system switching method and circuit containing x<2> with different fractional orders | |
CN103856317A (en) | Method and circuit for switching classic Lorenz type chaotic system with different fractional orders | |
CN103780373A (en) | Classic chen chaotic system switching method and circuit with different fractional orders | |
CN203872185U (en) | Lorenz-type chaotic switching system circuit with square of y and different fractional orders | |
CN203813801U (en) | Liu chaotic switching system circuit including xy with different fractional orders | |
CN203896361U (en) | Switching circuit of Lyv chaotic system with different fractional orders and containing x power | |
CN104202140A (en) | Four-dimensional balance point-free hyperchaotic system based on five-simplest chaotic system, and analogue circuit | |
CN103812639A (en) | Method and circuit for switching classical Liu (line interface unit) chaos system with different fraction orders | |
CN103812640A (en) | Method and circuit for switching Liu (line interface unit) chaos system with different fraction orders and xy | |
CN103731256B (en) | Three-dimensional non-balance-point chaotic system and artificial circuit implementation method | |
CN105553640A (en) | Construction method for balance-point-free four-dimensional hyper-chaotic system based on Rikitake system | |
CN104092532B (en) | Balance-point-free hyper-chaos system based on three-dimensional chaos system, and analogue circuit | |
CN103780374A (en) | Chen chaotic system switching method and circuit containing x<2> with different fractional orders | |
CN203872189U (en) | Liu chaotic switching system circuit with xy and different fractional orders | |
CN203933652U (en) | The classical l ü chaos switched system circuit that a kind of fractional-order is different | |
CN203872188U (en) | Lyu chaotic switching system circuit with square of y and different fractional orders | |
CN103856319A (en) | Method and circuit for switching Lorenz type chaotic system provided with different fractional orders and x2 | |
CN203872186U (en) | Qi chaotic switching system circuit with square of x and different fractional orders | |
CN103997400B (en) | Method and circuit for different-fractional-order y<2>-containing Liu chaotic switching system | |
CN103916232A (en) | Switching method and circuit of Lu chaotic system with different fractional orders and y<2> | |
CN203872184U (en) | Classical Qi chaotic switching system circuit with different fractional orders | |
CN203872187U (en) | Chen chaotic switching system circuit with square of y and different fractional orders | |
CN103780370A (en) | Zhang chaotic system switching method and circuit with different fractional orders | |
CN103856318A (en) | Method and circuit for switching Qi type chaotic system provided with different fractional orders and y2 | |
CN103780372A (en) | Chen chaotic system switching method and circuit containing y<2> with different fractional orders |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141105 Termination date: 20150313 |
|
EXPY | Termination of patent right or utility model |