CN203872187U

CN203872187U - Chen chaotic switching system circuit with square of y and different fractional orders

Info

Publication number: CN203872187U
Application number: CN201420120242.XU
Authority: CN
Inventors: 胡春华
Original assignee: Binzhou University
Current assignee: Binzhou University
Priority date: 2014-03-17
Filing date: 2014-03-17
Publication date: 2014-10-08
Anticipated expiration: 2024-03-17

Abstract

The utility model provides a Chen chaotic switching system circuit with the square of y and different fractional orders. The circuit uses an operational amplifier U1, an operational amplifier U2, resistors and capacitors to form inverting adders and fractional-order inverting integrators of different orders, uses a multiplier U3 and a multiplier U4 to realize multiplication, and uses an analog switch U5 to achieve selective output of an analog signal. The operational amplifier U1 and the operational amplifier U2 use LF347D. The multiplier U3 and the multiplier U4 use AD633JN. The analog switch U5 uses ADG888. The operational amplifier U1 is connected to the multiplier U3, the multiplier U4 and the analog switch U5. The operational amplifier U2 is connected to the multiplier U3 and the analog switch U5. The multiplier U3 is connected to the operational amplifier U1. The multiplier U4 is connected to the operational amplifier U2. The analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2. The novel switching circuit of a novel chaotic system is provided, so that a novel idea is provided for increase of types of chaotic system switching and application of the chaotic system to engineering practice.

Description

The chen chaos switched system circuit containing y side that a kind of fractional-order is different

Technical field

The utility model relates to a chaos system and circuit is realized, particularly the different chen chaos switched system circuit containing y side of a kind of fractional-order.

Background technology

At present, the main circuit of the switching chaos system that oneself has to comprise different linear terms in chaos system or nonlinear terms between switching, and the fractional order form based on these 2 kinds of switch modes, commutation circuit about the chaotic systems with fractional order of different orders is not also suggested, the utility model proposes the different chen chaos switched system circuit containing y side of a kind of fractional-order, the utility model proposes the novel commutation circuit of a novel chaos system, the type that this switches increase chaos system and this chaos system are applied to engineering practice provides a kind of new approaches.

Summary of the invention

The technical problems to be solved in the utility model is to provide the different chen chaos switched system circuit containing y side of a kind of fractional-order, and the utility model adopts following technological means to realize goal of the invention:

The chen chaos switched system circuit containing y side that fractional-order is different, is characterized in that being,

(1) constructing the different chen chaos switched system containing y side of a kind of fractional-order is:

\{\begin{matrix} d^{q} x / d t^{q} = a (y - x) \\ d^{q} y / d t^{q} = (c - a) x + cy - xz & a = 35, b = 3, c = 28, q = f (x) = \{\begin{matrix} 0.9 & x > 0 \\ 0.1 & x \leq 0 \end{matrix} \\ d^{q} z / {dt}^{q} = y^{2} - bz \end{matrix}

(2) the chen chaos switched system constructing analog Circuits System containing y side different according to fractional-order, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, by resistance R 8 and the 6th pin of operational amplifier U1, join, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, by resistance R 5, connect the 2nd pin of operational amplifier U1, meet the 1st of multiplier U4, 3 pins, the 8th pin of operational amplifier U1 connects the 9th pin of operational amplifier U1 by resistance R 6, by resistance R 4, connect the 6th pin of operational amplifier U1, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, by resistance R 7, connect the 9th pin of operational amplifier U1,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 14 and R15, by R14, meet the 8th of analog switch U5, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 12, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 11, by resistance R 13, connect the 9th pin of operational amplifier U2,

The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 9, the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U4 connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 10, and the 8th pin meets VCC;

The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

The beneficial effects of the utility model are: proposed the novel commutation circuit of a novel chaos system, the type that this switches increase chaos system and this chaos system are applied to engineering practice provides a kind of new approaches.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the utility model preferred embodiment.

Fig. 2 and Fig. 3 are the actual connection layout of circuit of the present utility model.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the utility model is further described in detail, referring to Fig. 1-Fig. 3.

\{\begin{matrix} d^{q} x / d t^{q} = a (y - x) \\ d^{q} y / d t^{q} = (c - a) x + cy - xz & a = 35, b = 3, c = 28, q = f (x) = \{\begin{matrix} 0.9 & x > 0 \\ 0.1 & x \leq 0 \end{matrix} \\ d^{q} z / {dt}^{q} = y^{2} - bz \end{matrix}

Resistance R 1=R7=R3=R8=R11=R13=10k Ω in circuit, R2=R6=2.86k Ω, R4=14.3k Ω, R5=3.57k Ω, R9=R10=1k Ω, R12=33.3k Ω, R14=100k Ω, R15=80k Ω, Rx11=Ry11=Rz11=62.84M Ω, Rx12=Ry12=Rz12=250k Ω, Rx13=Ry13=Rz13=2.5k Ω, Rx21=Ry21=Rz21=0.636M Ω, Rx22=Ry22=Rz22=0.3815M Ω, Rx23=Ry23=Rz23=0.5672M Ω, Cx11=Cy11=Cz11=1.2 μ F, Cx12=Cy12=Cz13=1.8 μ F, Cx13=Cy13=Cz13=1.1 μ F, Cx21=Cy21=Cz21=15.75 μ F, Cx22=Cy22=Cz22=0.1575 μ F, Cx23=Cy23=Cz23=633.5nF.

Claims

1. the different chen chaos switched system circuit containing y side of fractional-order, is characterized in that being,