CN102497263B - Method for realizing integer order and fractional order automatic switching chaotic system and analog circuit - Google Patents

Abstract

The invention discloses a construction of an integer order and fractional order automatic switching chaotic system and an analog circuit realization method. The construction comprises an automatic switching system which is formed by an integer order chaotic system and a fractional order chaotic system, and the automatic switching system is realized by utilizing an analog circuit. According to the invention, automatic switching of the integer order chaotic system and the fractional order chaotic system is realized by utilizing the analog circuit, the integer order and fractional order automatic switching chaotic system is more complex than the integer order chaotic system, the fractional order chaotic system and the automatic switching system, and superiority of the above three systems are concentrated. The system provided by the invention has an important meaning in secret communication based on chaos and signal detection and has good application prospect.

Description

A kind of method and analog circuit of realizing integer rank and fractional order automatically switched chaotic system

Technical field

The present invention relates to a kind of method of utilizing analog circuit to realize integer rank and fractional order automatically switched chaotic system, specifically, relate to a kind of method and analog circuit of realizing integer rank and fractional order automatically switched chaotic system.

Background technology

Realize with analog circuit in the method document of integer rank chaos system and have more report, realize with analog circuit in the method document of chaotic systems with fractional order and also have report, method and the circuit document of realizing automatically switched chaotic system also have report, but automatically switched chaotic system method and the circuit of realizing integer rank and fractional order with analog circuit have no report, because the chaos system that integer rank and fractional order automatically switch is than integer rank chaos system, chaotic systems with fractional order and automatic switchover system are all complicated, concentrate three's superiority, therefore, the method for designing of a kind of integer rank and fractional order automatically switched chaotic system is proposed, and realize this chaos system with analog circuit, application for this chaos system has great importance.

Summary of the invention

The technical problem to be solved in the present invention is to provide method and the analog circuit of a kind of integer rank and fractional order automatically switched chaotic system.

The present invention adopts following technological means to realize goal of the invention:

1, a method that realizes integer rank and fractional order automatically switched chaotic system, is characterized in that being, comprises the following steps:

(1) according to integer rank chaos system i be:

$\left\{\begin{array}{ccc}\mathrm{dx}/\mathrm{dt}=a(y-x)& & \\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}& i& a=20,b=14,c=10.6,h=2.8\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{hz}& & \end{array}\right.$

(2) according to chaotic systems with fractional order ii be:

$\left\{\begin{array}{cccc}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)& & & \\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}+\mathrm{cy}-\mathrm{cz}& \mathrm{ii}& 0<q<1& a=20,b=14,c=10.6,h=2.8\\ d^{q}z/{\mathrm{dt}}^q=x^2-\mathrm{hz}& & & \end{array}\right.$

(3) chaos system i and ii are formed new integer rank and fractional order automatically switched chaotic system iv by choice function system iii of structure:

$f\left(x\right)=\left\{\begin{array}{cc}q=1& x\&GreaterEqual;0\\ q=0.9& x<0\end{array}\right.---\mathrm{iii}$

$\left\{\begin{array}{ccc}{d}^{f\left(x\right)}x/{\mathrm{dt}}^{f\left(x\right)}=a(y-x)& & \\ d^{f\left(x\right)}y/{\mathrm{dt}}^{f\left(x\right)}=\mathrm{bx}-\mathrm{cy}-\mathrm{xz}& \mathrm{iv}& a=20,b=14,c=10.6,h=2.8\\ d^{f\left(x\right)}z/{\mathrm{dt}}^{f\left(x\right)}=x^2-\mathrm{hz}& & \end{array}\right.$

According to chaos system iii and iv constructing analog Circuits System, utilize voltage comparator U6 to obtain the low and high level of simulation, x>=0 and x<0, as the input of choice function, utilize analog switch U7 and U8 to realize the alternately output of integer rank integration and fractional order integration, utilize operational amplifier U1, U2, U3 and multiplier U4, U5 obtains the analog circuit of integer rank and mark automatically switched chaotic system, described operational amplifier U1, U2, U3 adopts LF347, multiplier U4, U5 adopts AD633JN, voltage comparator U6 adopts LM339, analog switch U7, U8 adopts CD4052,

Described operational amplifier U1 connects voltage comparator U6, analog switch U7, U8, multiplier U4, U5, described voltage comparator U6 connecting analog switch U7, U8, described multiplier U4 concatenation operation amplifier U2, described operational amplifier U2 connecting analog switch U7, described multiplier U5 concatenation operation amplifier U3, described operational amplifier U3 connecting analog switch U8;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin of U1, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc11 of the 6th pin and capacitor C 11 in parallel, connecting resistance Rc12 and capacitor C 12 is in parallel again, again after connecting resistance Rc13 and capacitor C 13 in parallel, join with the 4th pin of U7, join by capacitor C 10 and the 5th pin of U7, the 9th pin of the 7th pin and U6 joins, join with the 1st pin of U4, join with the 8th pin of U7, with the 1st of U5, 3 pins join, join by resistance R 22 and the 2nd pin of U2, the 8th pin joins by resistance R 25 and the 9th pin of U1, the 9th pin joins by the 2nd pin of resistance R 24 and potentiometer R12 and U1, the 2nd pin by resistance R 24 and potentiometer R23 and U2 joins, join by resistance R 24 and the 9th pin of U7, the 13rd pin joins by resistance R 13 and the 7th pin of U1, join with the 1st pin of U4, join with the 8th pin of U7, the 1st pin with U5, the 3rd pin joins, join by resistance R 14 and the 14th pin of U1, the 14th pin joins by the 2nd pin of potentiometer R11 and U1,

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin of U2, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc21 of the 6th pin and capacitor C 21 in parallel, connecting resistance Rc22 and capacitor C 22 is in parallel again, again after connecting resistance Rc23 and capacitor C 23 in parallel, join with the 13rd pin of U7, join by capacitor C 20 and the 12nd pin of U7, the 9th pin of the 7th pin and U7 joins, the 8th pin of the 8th pin and U8 joins, the first connecting resistance Rc33 of the 9th pin is in parallel with capacitor C 33, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc31 and capacitor C 31 in parallel, join with the 4th pin of U8, join by capacitor C 30 and the 5th pin of U8, the 13rd pin joins by resistance R 33 and the 8th pin of U8, join by resistance R 34 and the 14th pin of U2, the 14th pin connects the 3rd pin of U4, the 2nd pin by potentiometer R32 and U3 joins,

The 1st pin of described operational amplifier U3 joins by resistance R z and the 2nd pin, join by resistance R 31 and the 9th pin of U2, the 2nd pin of U3 connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin was connected resistance R 21 and connect the 2nd pin of U2, and the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 2nd pin of U3 by resistance R 31, and the 8th pin meets VCC;

The the the the the the 1st, 2,4,5,6,7,10,11,13 pins of described voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins by resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, and the 14th pin joins by the 1st pin of diode D1 and U7, the 1st pin of U8, meets VCC by resistance R 01;

The 1st pin of described analog switch U7 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, after the first connecting resistance Rc13 of the 4th pin and capacitor C 13 in parallel, connecting resistance Rc12 is in parallel with capacitor C 12 again, again after connecting resistance Rc11 and capacitor C 11 in parallel, connect 6 pins of U1, the 5th pin connects 6 pins of U1 by capacitor C 10, the 6th, 7 pins are unsettled, the 8th pin connects 7 pins of U1, the 9th pin connects 7 pins of U2, the 10th, 11 pins are unsettled, the 12nd pin connects 6 pins of U2 by C20, after the first connecting resistance Rc23 of the 13rd pin and capacitor C 23 in parallel, connecting resistance Rc22 is in parallel with capacitor C 22 again, again after connecting resistance Rc21 and capacitor C 21 in parallel, connect 6 pins of U2, the 14th pin meets VCC, the 15th, 16 pin ground connection,

The 1st pin of described analog switch U8 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, the first connecting resistance Rc31 of the 4th pin is in parallel with capacitor C 31, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc33 and capacitor C 33 in parallel, connect 9 pins of U2, the 5th pin connects 9 pins of U2 by capacitor C 30,6th, 7 pins are unsettled, and the 8th pin connects 8 pins of U2, and the the the 9th, 10,11,12,13 pins are unsettled, the 14th pin meets VCC, the 15th, 16 pin ground connection.

2, a kind of circuit of realizing integer rank and fractional order automatically switched chaotic system, it is characterized in that being, by operational amplifier U1, U2, U3 and multiplier U4, U5 and voltage comparator U6 and analog switch U7, U8 composition, described operational amplifier U1 connects voltage comparator U6, analog switch U7, U8, multiplier U4, U5, described voltage comparator U6 connecting analog switch U7, U8, described multiplier U4 concatenation operation amplifier U2, described operational amplifier U2 connecting analog switch U7, described multiplier U5 concatenation operation amplifier U3, described operational amplifier U3 connecting analog switch U8,

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin of U1, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc11 of the 6th pin and capacitor C 11 in parallel, connecting resistance Rc12 and capacitor C 12 is in parallel again, again after connecting resistance Rc13 and capacitor C 13 in parallel, join with the 4th pin of U7, join by capacitor C 10 and the 5th pin of U7, the 9th pin of the 7th pin and U6 joins, join with the 1st pin of U4, join with the 8th pin of U7, with the 1st of U5, 3 pins join, join by resistance R 22 and the 2nd pin of U2, the 8th pin joins by resistance R 25 and the 9th pin of U1, the 9th pin joins by the 2nd pin of resistance R 24 and potentiometer R12 and U1, the 2nd pin by resistance R 24 and potentiometer R23 and U2 joins, join by resistance R 24 and the 9th pin of U7, the 13rd pin joins by resistance R 13 and the 7th pin of U1, join with the 1st pin of U4, join with the 8th pin of U7, the 1st pin with U5, the 3rd pin joins, join by resistance R 14 and the 14th pin of U1, the 14th pin joins by the 2nd pin of potentiometer R11 and U1,

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin of U2, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc21 of the 6th pin and capacitor C 21 in parallel, connecting resistance Rc22 and capacitor C 22 is in parallel again, again after connecting resistance Rc23 and capacitor C 23 in parallel, join with the 13rd pin of U7, join by capacitor C 20 and the 12nd pin of U7, the 9th pin of the 7th pin and U7 joins, the 8th pin of the 8th pin and U8 joins, the first connecting resistance Rc33 of the 9th pin is in parallel with capacitor C 33, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc31 and capacitor C 31 in parallel, join with the 4th pin of U8, join by capacitor C 30 and the 5th pin of U8, the 13rd pin joins by resistance R 33 and the 8th pin of U8, join by resistance R 34 and the 14th pin of U2, the 14th pin connects the 3rd pin of U4, the 2nd pin by potentiometer R32 and U3 joins,

The 1st pin of described operational amplifier U3 joins by resistance R z and the 2nd pin, join by resistance R 31 and the 9th pin of U2, the 2nd pin of U3 connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin was connected resistance R 21 and connect the 2nd pin of U2, and the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 2nd pin of U3 by resistance R 31, and the 8th pin meets VCC;

The the the the the the 1st, 2,4,5,6,7,10,11,13 pins of described voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins by resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, and the 14th pin joins by the 1st pin of diode D1 and U7, the 1st pin of U8, meets VCC by resistance R 01;

The 1st pin of described analog switch U7 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, after the first connecting resistance Rc13 of the 4th pin and capacitor C 13 in parallel, connecting resistance Rc12 is in parallel with capacitor C 12 again, again after connecting resistance Rc11 and capacitor C 11 in parallel, connect 6 pins of U1, the 5th pin connects 6 pins of U1 by capacitor C 10, the 6th, 7 pins are unsettled, the 8th pin connects 7 pins of U1, the 9th pin connects 7 pins of U2, the 10th, 11 pins are unsettled, the 12nd pin connects 6 pins of U2 by C20, after the first connecting resistance Rc23 of the 13rd pin and capacitor C 23 in parallel, connecting resistance Rc22 is in parallel with capacitor C 22 again, again after connecting resistance Rc21 and capacitor C 21 in parallel, connect 6 pins of U2, the 14th pin meets VCC, the 15th, 16 pin ground connection,

The 1st pin of described analog switch U8 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, the first connecting resistance Rc31 of the 4th pin is in parallel with capacitor C 31, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc33 and capacitor C 33 in parallel, connect 9 pins of U2, the 5th pin connects 9 pins of U2 by capacitor C 30,6th, 7 pins are unsettled, and the 8th pin connects 8 pins of U2, and the the the 9th, 10,11,12,13 pins are unsettled, the 14th pin meets VCC, the 15th, 16 pin ground connection.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 is operational amplifier U1 peripheral circuit structural representation.

Fig. 3 is operational amplifier U2 and multiplier U4 peripheral circuit structural representation.

Fig. 4 is operational amplifier U3 and multiplier U5 peripheral circuit structural representation.

Fig. 5 is voltage comparator U6 peripheral circuit structural representation.

Fig. 6 is the peripheral circuit structural representation of analog switch U7.

Fig. 7 is analog switch U8 peripheral circuit structural representation.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail.

Referring to Fig. 1-Fig. 7, first construct integer rank and fractional order automatically switched chaotic system, the integer rank chaos system i that this preferred embodiment is selected is:

$\left\{\begin{array}{ccc}\mathrm{dx}/\mathrm{dt}=a(y-x)& & \\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}& i& a=20,b=14,c=10.6,h=2.8\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{hz}& & \end{array}\right.$

The chaotic systems with fractional order ii selecting is:

$\left\{\begin{array}{cccc}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)& & & \\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}+\mathrm{cy}-\mathrm{cz}& \mathrm{ii}& 0<q<1& a=20,b=14,c=10.6,h=2.8\\ d^{q}z/{\mathrm{dt}}^q=x^2-\mathrm{hz}& & & \end{array}\right.$

Construct a choice function system iii, chaos system i and ii formed to new integer rank and fractional order automatically switched chaotic system iv:

$f\left(x\right)=\left\{\begin{array}{cc}q=1& x\&GreaterEqual;0\\ q=0.9& x<0\end{array}\right.---\mathrm{iii}$

$\left\{\begin{array}{ccc}{d}^{f\left(x\right)}x/{\mathrm{dt}}^{f\left(x\right)}=a(y-x)& & \\ d^{f\left(x\right)}y/{\mathrm{dt}}^{f\left(x\right)}=\mathrm{bx}-\mathrm{cy}-\mathrm{xz}& \mathrm{iv}& a=20,b=14,c=10.6,h=2.8\\ d^{f\left(x\right)}z/{\mathrm{dt}}^{f\left(x\right)}=x^2-\mathrm{hz}& & \end{array}\right.$

According to chaos system iii and iv constructing analog Circuits System, utilize voltage comparator U6 to obtain the low and high level of simulation, x>=0 and x<0, as the input of choice function, utilize analog switch U7 and U8 to realize the alternately output of integer rank integration and fractional order integration, utilize operational amplifier U1, U2, U3 and multiplier U4, U5 obtains the analog circuit of integer rank and mark automatically switched chaotic system, described operational amplifier U1, U2, U3 adopts LF347, multiplier U4, U5 adopts AD633JN, voltage comparator U6 adopts LM339, analog switch U7, U8 adopts CD4052,

Described operational amplifier U1 connects voltage comparator U6, analog switch U7, U8, multiplier U4, U5, described voltage comparator U6 connecting analog switch U7, U8, described multiplier U4 concatenation operation amplifier U2, described operational amplifier U2 connecting analog switch U7, described multiplier U5 concatenation operation amplifier U3, described operational amplifier U3 connecting analog switch U8;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin of U1, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc11 of the 6th pin and capacitor C 11 in parallel, connecting resistance Rc12 and capacitor C 12 is in parallel again, again after connecting resistance Rc13 and capacitor C 13 in parallel, join with the 4th pin of U7, join by capacitor C 10 and the 5th pin of U7, the 9th pin of the 7th pin and U6 joins, join with the 1st pin of U4, join with the 8th pin of U7, with the 1st of U5, 3 pins join, join by resistance R 22 and the 2nd pin of U2, the 8th pin joins by resistance R 25 and the 9th pin of U1, the 9th pin joins by the 2nd pin of resistance R 24 and potentiometer R12 and U1, the 2nd pin by resistance R 24 and potentiometer R23 and U2 joins, join by resistance R 24 and the 9th pin of U7, the 13rd pin joins by resistance R 13 and the 7th pin of U1, join with the 1st pin of U4, join with the 8th pin of U7, the 1st pin with U5, the 3rd pin joins, join by resistance R 14 and the 14th pin of U1, the 14th pin joins by the 2nd pin of potentiometer R11 and U1,

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin of U2, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc21 of the 6th pin and capacitor C 21 in parallel, connecting resistance Rc22 and capacitor C 22 is in parallel again, again after connecting resistance Rc23 and capacitor C 23 in parallel, join with the 13rd pin of U7, join by capacitor C 20 and the 12nd pin of U7, the 9th pin of the 7th pin and U7 joins, the 8th pin of the 8th pin and U8 joins, the first connecting resistance Rc33 of the 9th pin is in parallel with capacitor C 33, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc31 and capacitor C 31 in parallel, join with the 4th pin of U8, join by capacitor C 30 and the 5th pin of U8, the 13rd pin joins by resistance R 33 and the 8th pin of U8, join by resistance R 34 and the 14th pin of U2, the 14th pin connects the 3rd pin of U4, the 2nd pin by potentiometer R32 and U3 joins,

The 1st pin of described operational amplifier U3 joins by resistance R z and the 2nd pin, join by resistance R 31 and the 9th pin of U2, the 2nd pin of U3 connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin was connected resistance R 21 and connect the 2nd pin of U2, and the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 2nd pin of U3 by resistance R 31, and the 8th pin meets VCC;

The the the the the the 1st, 2,4,5,6,7,10,11,13 pins of described voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins by resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, and the 14th pin joins by the 1st pin of diode D1 and U7, the 1st pin of U8, meets VCC by resistance R 01;

The 1st pin of described analog switch U7 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, after the first connecting resistance Rc13 of the 4th pin and capacitor C 13 in parallel, connecting resistance Rc12 is in parallel with capacitor C 12 again, again after connecting resistance Rc11 and capacitor C 11 in parallel, connect 6 pins of U1, the 5th pin connects 6 pins of U1 by capacitor C 10, the 6th, 7 pins are unsettled, the 8th pin connects 7 pins of U1, the 9th pin connects 7 pins of U2, the 10th, 11 pins are unsettled, the 12nd pin connects 6 pins of U2 by C20, after the first connecting resistance Rc23 of the 13rd pin and capacitor C 23 in parallel, connecting resistance Rc22 is in parallel with capacitor C 22 again, again after connecting resistance Rc21 and capacitor C 21 in parallel, connect 6 pins of U2, the 14th pin meets VCC, the 15th, 16 pin ground connection,

The 1st pin of described analog switch U8 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, the first connecting resistance Rc31 of the 4th pin is in parallel with capacitor C 31, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc33 and capacitor C 33 in parallel, connect 9 pins of U2, the 5th pin connects 9 pins of U2 by capacitor C 30,6th, 7 pins are unsettled, and the 8th pin connects 8 pins of U2, and the the the 9th, 10,11,12,13 pins are unsettled, the 14th pin meets VCC, the 15th, 16 pin ground connection.

Certainly, above-mentioned explanation is the restriction to invention not, and the present invention is also not limited only to above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art make in essential scope of the present invention, also belong to protection scope of the present invention.

Claims (2)

1. a method that realizes integer rank and fractional order automatically switched chaotic system, is characterized in that being, comprises the following steps:

(1) according to integer rank chaos system i be:

$\left\{\begin{array}{ccc}\mathrm{dx}/\mathrm{dt}=a(y-x)& & \\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}& i& a=20,b=14,c=10.6,h=2.8\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{hz}& & \end{array}\right.$

(2) according to chaotic systems with fractional order ii be:

$\left\{\begin{array}{cccc}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)& & & \\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}+\mathrm{cy}-\mathrm{cz}& \mathrm{ii}& 0<q<1& a=20,b=14,c=10.6,h=2.8\\ d^{q}z/{\mathrm{dt}}^q=x^2-\mathrm{hz}& & & \end{array}\right.$

(3) chaos system i and ii are formed new integer rank and fractional order automatically switched chaotic system iv by choice function system iii of structure:

$f\left(x\right)=\left\{\begin{array}{cc}q=1& x\&GreaterEqual;0\\ q=0.9& x<0\end{array}\right.---\mathrm{iii}$

$\left\{\begin{array}{ccc}{d}^{f\left(x\right)}x/{\mathrm{dt}}^{f\left(x\right)}=a(y-x)& & \\ d^{f\left(x\right)}y/{\mathrm{dt}}^{f\left(x\right)}=\mathrm{bx}-\mathrm{cy}-\mathrm{xz}& \mathrm{iv}& a=20,b=14,c=10.6,h=2.8\\ d^{f\left(x\right)}z/{\mathrm{dt}}^{f\left(x\right)}=x^2-\mathrm{hz}& & \end{array}\right.$

(4) according to chaos system iii and iv constructing analog Circuits System, utilize voltage comparator U6 to obtain the low and high level of simulation, x>=0 and x<0, as the input of choice function, utilize analog switch U7 and U8 to realize the alternately output of integer rank integration and fractional order integration, utilize operational amplifier U1, U2, U3 and multiplier U4, U5 obtains the analog circuit of integer rank and mark automatically switched chaotic system, described operational amplifier U1, U2, U3 adopts LF347, multiplier U4, U5 adopts AD633JN, voltage comparator U6 adopts LM339, analog switch U7, U8 adopts CD4052,

Described operational amplifier U1 connects voltage comparator U6, analog switch U7, U8, multiplier U4, U5, described voltage comparator U6 connecting analog switch U7, U8, described multiplier U4 concatenation operation amplifier U2, described operational amplifier U2 connecting analog switch U7, described multiplier U5 concatenation operation amplifier U3, described operational amplifier U3 connecting analog switch U8;

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin of U1, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc11 of the 6th pin and capacitor C 11 in parallel, connecting resistance Rc12 and capacitor C 12 is in parallel again, again after connecting resistance Rc13 and capacitor C 13 in parallel, join with the 4th pin of U7, join by capacitor C 10 and the 5th pin of U7, the 9th pin of the 7th pin and U6 joins, join with the 1st pin of U4, join with the 8th pin of U7, with the 1st of U5, 3 pins join, join by resistance R 22 and the 2nd pin of U2, the 8th pin joins by resistance R 25 and the 9th pin of U1, the 9th pin joins by the 2nd pin of resistance R 24 and potentiometer R12 and U1, the 2nd pin by resistance R 24 and potentiometer R23 and U2 joins, join by resistance R 24 and the 9th pin of U7, the 13rd pin joins by resistance R 13 and the 7th pin of U1, join with the 1st pin of U4, join with the 8th pin of U7, the 1st pin with U5, the 3rd pin joins, join by resistance R 14 and the 14th pin of U1, the 14th pin joins by the 2nd pin of potentiometer R11 and U1,

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin of U2, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc21 of the 6th pin and capacitor C 21 in parallel, connecting resistance Rc22 and capacitor C 22 is in parallel again, again after connecting resistance Rc23 and capacitor C 23 in parallel, join with the 13rd pin of U7, join by capacitor C 20 and the 12nd pin of U7, the 9th pin of the 7th pin and U7 joins, the 8th pin of the 8th pin and U8 joins, the first connecting resistance Rc33 of the 9th pin is in parallel with capacitor C 33, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc31 and capacitor C 31 in parallel, join with the 4th pin of U8, join by capacitor C 30 and the 5th pin of U8, the 13rd pin joins by resistance R 33 and the 8th pin of U8, join by resistance R 34 and the 14th pin of U2, the 14th pin connects the 3rd pin of U4, the 2nd pin by potentiometer R32 and U3 joins,

The 1st pin of described operational amplifier U3 joins by resistance R z and the 2nd pin, join by resistance R 31 and the 9th pin of U2, the 2nd pin of U3 connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 2nd pin of U2 by resistance R 21, and the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 2nd pin of U3 by resistance R 31, and the 8th pin meets VCC;

The the the the the the 1st, 2,4,5,6,7,10,11,13 pins of described voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins by resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, and the 14th pin joins by the 1st pin of diode D1 and U7, the 1st pin of U8, meets VCC by resistance R 01;

The 1st pin of described analog switch U7 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, after the first connecting resistance Rc13 of the 4th pin and capacitor C 13 in parallel, connecting resistance Rc12 is in parallel with capacitor C 12 again, again after connecting resistance Rc11 and capacitor C 11 in parallel, connect 6 pins of U1, the 5th pin connects 6 pins of U1 by capacitor C 10, the 6th, 7 pins are unsettled, the 8th pin connects 7 pins of U1, the 9th pin connects 7 pins of U2, the 10th, 11 pins are unsettled, the 12nd pin connects 6 pins of U2 by C20, after the first connecting resistance Rc23 of the 13rd pin and capacitor C 23 in parallel, connecting resistance Rc22 is in parallel with capacitor C 22 again, again after connecting resistance Rc21 and capacitor C 21 in parallel, connect 6 pins of U2, the 14th pin meets VCC, the 15th, 16 pin ground connection,

The 1st pin of described analog switch U8 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, the first connecting resistance Rc31 of the 4th pin is in parallel with capacitor C 31, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc33 and capacitor C 33 in parallel, connect 9 pins of U2, the 5th pin connects 9 pins of U2 by capacitor C 30,6th, 7 pins are unsettled, and the 8th pin connects 8 pins of U2, and the the the 9th, 10,11,12,13 pins are unsettled, the 14th pin meets VCC, the 15th, 16 pin ground connection.

2. realize the circuit of integer rank and fractional order automatically switched chaotic system for one kind, it is characterized in that being, by operational amplifier U1, U2, U3 and multiplier U4, U5 and voltage comparator U6 and analog switch U7, U8 composition, described operational amplifier U1 connects voltage comparator U6, analog switch U7, U8, multiplier U4, U5, described voltage comparator U6 connecting analog switch U7, U8, described multiplier U4 concatenation operation amplifier U2, described operational amplifier U2 connecting analog switch U7, described multiplier U5 concatenation operation amplifier U3, described operational amplifier U3 connecting analog switch U8,

The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin of U1, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc11 of the 6th pin and capacitor C 11 in parallel, connecting resistance Rc12 and capacitor C 12 is in parallel again, again after connecting resistance Rc13 and capacitor C 13 in parallel, join with the 4th pin of U7, join by capacitor C 10 and the 5th pin of U7, the 9th pin of the 7th pin and U6 joins, join with the 1st pin of U4, join with the 8th pin of U7, with the 1st of U5, 3 pins join, join by resistance R 22 and the 2nd pin of U2, the 8th pin joins by resistance R 25 and the 9th pin of U1, the 9th pin joins by the 2nd pin of resistance R 24 and potentiometer R12 and U1, the 2nd pin by resistance R 24 and potentiometer R23 and U2 joins, join by resistance R 24 and the 9th pin of U7, the 13rd pin joins by resistance R 13 and the 7th pin of U1, join with the 1st pin of U4, join with the 8th pin of U7, the 1st pin with U5, the 3rd pin joins, join by resistance R 14 and the 14th pin of U1, the 14th pin joins by the 2nd pin of potentiometer R11 and U1,

The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin of U2, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, after the first connecting resistance Rc21 of the 6th pin and capacitor C 21 in parallel, connecting resistance Rc22 and capacitor C 22 is in parallel again, again after connecting resistance Rc23 and capacitor C 23 in parallel, join with the 13rd pin of U7, join by capacitor C 20 and the 12nd pin of U7, the 9th pin of the 7th pin and U7 joins, the 8th pin of the 8th pin and U8 joins, the first connecting resistance Rc33 of the 9th pin is in parallel with capacitor C 33, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc31 and capacitor C 31 in parallel, join with the 4th pin of U8, join by capacitor C 30 and the 5th pin of U8, the 13rd pin joins by resistance R 33 and the 8th pin of U8, join by resistance R 34 and the 14th pin of U2, the 14th pin connects the 3rd pin of U4, the 2nd pin by potentiometer R32 and U3 joins,

The 1st pin of described operational amplifier U3 joins by resistance R z and the 2nd pin, join by resistance R 31 and the 9th pin of U2, the 2nd pin of U3 connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin was connected resistance R 21 and connect the 2nd pin of U2, and the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 2nd pin of U3 by resistance R 31, and the 8th pin meets VCC;

The the the the the the 1st, 2,4,5,6,7,10,11,13 pins of described voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins by resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, and the 14th pin joins by the 1st pin of diode D1 and U7, the 1st pin of U8, meets VCC by resistance R 01;

The 1st pin of described analog switch U7 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, after the first connecting resistance Rc13 of the 4th pin and capacitor C 13 in parallel, connecting resistance Rc12 is in parallel with capacitor C 12 again, again after connecting resistance Rc11 and capacitor C 11 in parallel, connect 6 pins of U1, the 5th pin connects 6 pins of U1 by capacitor C 10, the 6th, 7 pins are unsettled, the 8th pin connects 7 pins of U1, the 9th pin connects 7 pins of U2, the 10th, 11 pins are unsettled, the 12nd pin connects 6 pins of U2 by C20, after the first connecting resistance Rc23 of the 13rd pin and capacitor C 23 in parallel, connecting resistance Rc22 is in parallel with capacitor C 22 again, again after connecting resistance Rc21 and capacitor C 21 in parallel, connect 6 pins of U2, the 14th pin meets VCC, the 15th, 16 pin ground connection,

The 1st pin of described analog switch U8 connects the 8th pin of U6 by resistance R 02, the 2nd pin meets VCC, the 3rd pin meets VEE, the first connecting resistance Rc31 of the 4th pin is in parallel with capacitor C 31, connecting resistance Rc32 and capacitor C 32 is in parallel again, again after connecting resistance Rc33 and capacitor C 33 in parallel, connect 9 pins of U2, the 5th pin connects 9 pins of U2 by capacitor C 30,6th, 7 pins are unsettled, and the 8th pin connects 8 pins of U2, and the the the 9th, 10,11,12,13 pins are unsettled, the 14th pin meets VCC, the 15th, 16 pin ground connection.

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