CN202818324U - Fractional order four-system automatic switching analog circuit for Liu-type systems - Google Patents

Fractional order four-system automatic switching analog circuit for Liu-type systems Download PDF

Info

Publication number
CN202818324U
CN202818324U CN 201220512586 CN201220512586U CN202818324U CN 202818324 U CN202818324 U CN 202818324U CN 201220512586 CN201220512586 CN 201220512586 CN 201220512586 U CN201220512586 U CN 201220512586U CN 202818324 U CN202818324 U CN 202818324U
Authority
CN
China
Prior art keywords
pin
connects
resistance
operational amplifier
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201220512586
Other languages
Chinese (zh)
Inventor
王春梅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Binzhou University
Original Assignee
Binzhou University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Binzhou University filed Critical Binzhou University
Priority to CN 201220512586 priority Critical patent/CN202818324U/en
Application granted granted Critical
Publication of CN202818324U publication Critical patent/CN202818324U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Amplifiers (AREA)

Abstract

本实用新型提出了一种实现Liu型系统的分数阶四个系统自动切换模拟电路,所述实现Liu型系统的分数阶四个系统自动切换模拟电路由运算放大器U1、运算放大器U2、运算放大器U3、运算放大器U5、运算放大器U8与乘法器U4、乘法器U9、乘法器U10及电压比较器U7和模拟开关U6组成,所述运算放大器U1连接电压比较器U7,运算放大器U5、运算放大器U8,乘法器U4,运算放大器U2,所述运算放大器U2连接运算放大器U1、运算放大器U5、电压比较器U7、运算放大器U8,所述运算放大器U3连接运算放大器U2,乘法器U4,所述运算放大器U5连接模拟开关U6,所述电压比较器U7连接模拟开关U6,所述运算放大器U8连接运算放大器U5、乘法器U9、乘法器U10,所述乘法器U9连接模拟开关U6,所述乘法器U10连接模拟开关U6,本实用新型利用模拟电路实现了四个Liu型子系统自动切换的分数阶混沌系统,比2个子混沌系统组成的自动切换的混沌系统和不切换的分数阶混沌系统更复杂,随机性更强,可以成为保密通信的信号源一种新的选择,在保密通信中具有更好的应用前景。

Figure 201220512586

The utility model proposes an analog circuit for automatically switching four fractional-order systems of a Liu-type system, wherein the analog circuit for automatically switching four systems of a fractional order for realizing a Liu-type system is composed of an operational amplifier U1, an operational amplifier U2, and an operational amplifier U3 , operational amplifier U5, operational amplifier U8 and multiplier U4, multiplier U9, multiplier U10 and voltage comparator U7 and analog switch U6 form, described operational amplifier U1 connects voltage comparator U7, operational amplifier U5, operational amplifier U8, Multiplier U4, operational amplifier U2, described operational amplifier U2 connects operational amplifier U1, operational amplifier U5, voltage comparator U7, operational amplifier U8, described operational amplifier U3 connects operational amplifier U2, multiplier U4, described operational amplifier U5 Connect the analog switch U6, the voltage comparator U7 is connected to the analog switch U6, the operational amplifier U8 is connected to the operational amplifier U5, the multiplier U9, and the multiplier U10, the multiplier U9 is connected to the analog switch U6, and the multiplier U10 is connected to The analog switch U6, the utility model utilizes the analog circuit to realize the fractional-order chaotic system of automatic switching of four Liu-type subsystems, which is more complex than the automatic switching chaotic system composed of two sub-chaotic systems and the non-switching fractional-order chaotic system, random It is stronger and can become a new choice of signal source for secure communication, and has a better application prospect in secure communication.

Figure 201220512586

Description

Realize the fractional order four systems automatic switchover analog circuit of Liu type system
Technical field
The utility model relates to fractional order four systems automatic switchover analog circuit, specifically, relates to the fractional order four systems automatic switchover analog circuit of realizing Liu type system.
Background technology
At present, oneself has several different methods to realize integer rank and chaotic systems with fractional order and circuit with analog circuit, but the method for the chaos circuit that realize to automatically switch with analog circuit is fewer, and own disclosed automatically switched chaotic system and circuit are that 2 the sub-chaos systems in integer rank switch, also there are not the method for a plurality of sub-chaos systems automatic switchovers and disclosing of circuit, the utility model provides the fractional order four systems automatic switchover analog circuit of a kind of Liu of realization type system, quantity and the type of automatically switched chaotic system have been enriched, improved the randomness of chaos system, good application prospect has been arranged in secure communication.
The utility model content
The technical problems to be solved in the utility model provides the fractional order four systems automatic switchover analog circuit of realizing Liu type system, and the utility model adopts following technological means to realize the utility model purpose:
Realize the fractional order four systems automatic switchover analog circuit of Liu type system, it is characterized in that being, by operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U5, operational amplifier U8 and multiplier U4, multiplier U9, multiplier U10 and voltage comparator U7 and analog switch U6 form, described operational amplifier U1 connects voltage comparator U7, operational amplifier U5, operational amplifier U8, multiplier U4, operational amplifier U2, described operational amplifier U2 concatenation operation amplifier U1, operational amplifier U5, voltage comparator U7, operational amplifier U8, described operational amplifier U3 concatenation operation amplifier U2, multiplier U4, described operational amplifier U5 connecting analog switch U6, described voltage comparator U7 connecting analog switch U6, described operational amplifier U8 concatenation operation amplifier U5, multiplier U9, multiplier U10, described multiplier U9 connecting analog switch U6, described multiplier U10 connecting analog switch U6;
The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 2nd pin of U2 by potentiometer R23, connect the 1st pin of U4, connect the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, and the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;
The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin connects the 9th pin of U1 by the R24 of resistance, connects the 2nd pin of U1 by potentiometer R12, connects the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connect first the in parallel of Rc31 and capacitor C 31, connect the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;
Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;
The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;
The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;
The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;
The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects positive 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;
The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s3, and the 13rd pin connects the 7th pin of U2;
The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;
The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.
Description of drawings
Fig. 1 is the circuit connection structure schematic diagram of the utility model preferred embodiment.
Fig. 2 is operational amplifier U1 peripheral circuit structural representation.
Fig. 3 is operational amplifier U2 and multiplier U4 peripheral circuit structural representation.
Fig. 4 is operational amplifier U5 peripheral circuit structural representation.
Fig. 5 is operational amplifier U8, multiplier U9 and multiplier U10 peripheral circuit structural representation.
Fig. 6 is the peripheral circuit structural representation of operational amplifier U3, voltage comparator U7 and analog switch U6.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment the utility model is done further to describe in detail.
Referring to Fig. 1-Fig. 6, at first construct Liu type fractional order four systems automatically switched chaotic system, the system that this preferred embodiment is selected
(1) according to Liu type chaos system I be:
dx / dt = a ( y - x ) dy / dt = bx - cxz dz / dt = h | x | - dz - - - I a = 10 , b = 40 , c = 10 , d = 2.5 , h = 4
(2) according to Liu type chaos system II be:
dx / dt = a ( y - x ) dy / dt = bx - cxz dz / dt = h | y | - dz - - - II a = 10 , b = 40 , c = 10 , d = 2.5 , h = 4
(3) according to chaos system structure sign function III and IV be:
sign ( x ) = 1 x &GreaterEqual; 0 - 1 x < 0 - - - III
sign ( y ) = 1 y &GreaterEqual; 0 - 1 y < 0 - - - IV
(4) according to Liu type chaos system V be:
dx / dt = a ( y - x ) dy / dt = bx - cxz dz / dt = hxsign ( y ) - dz - - - V a = 10 , b = 40 , c = 10 , d = 2.5 , h = 4
(5) according to Liu type chaos system VI be:
dx / dt = a ( y - x ) dy / dt = bx - cxz dz / dt = hysign ( x ) - dz - - - VI a = 10 , b = 40 , c = 10 , d = 2.5 , h = 4
(6) according to chaos system structure choice function VII be:
f ( xy ) = | x | x &GreaterEqual; 0 , y &GreaterEqual; 0 xsign ( y ) x &GreaterEqual; 0 , y < 0 ysign ( x ) x < 0 , y &GreaterEqual; 0 | y | x < 0 , y < 0 - - - VII
(7) according to the I of system, II, V, VI and Liu type four systems automatically switched chaotic system IX of choice function VII structure
dx / dt = a ( y - x ) dy / dt = bx - cxz dz / dt = hf ( xy ) - dz - - - IX a = 10 , b = 40 , c = 10 , d = 2.5 , h = 4
(8) according to Liu type fractional order four systems automatically switched chaotic system X of the IX of system structure
d q x / d t q = a ( y - x ) d q y / dt q = bx - cxz d q z / d t q = hf ( xy ) - dz - - - X 0 < q < 1 , a = 10 , b = 40 , c = 10 , d = 2.5 , h = 4
(9) according to chaos system X constructing analog Circuits System, utilize voltage comparator U7 to obtain the high-low level of two simulations, x 〉=0 or x<0 and y>=0 or y<0, control inputs as analog switch U6, according to x 〉=0, y>=0, x〉0, y<0, x<0, y>=0 and x<0, y<0 four kind of different situations, realize the difference output of f (xy), thereby realize the chaos system IX that four systems automaticallyes switch, realize chaos system X by fractional order integration again, operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U5, operational amplifier U8 adopts LF347, multiplier U4, multiplier U9, multiplier U10 adopts AD633JN, and analog switch U6 adopts ADG409, and voltage comparator U7 adopts LM139;
The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 2nd pin of U2 by potentiometer R23, connect the 1st pin of U4, connect the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, and the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;
The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin connects the 9th pin of U1 by the R24 of resistance, connects the 2nd pin of U1 by potentiometer R12, connects the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connect first the in parallel of Rc31 and capacitor C 31, connect the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;
Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;
The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;
The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;
The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;
The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects positive 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;
The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s3, and the 13rd pin connects the 7th pin of U2;
The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;
The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.
Certainly; above-mentioned explanation is not the restriction to utility model; the utility model also is not limited only to above-mentioned giving an example, and the variation that those skilled in the art make in essential scope of the present utility model, remodeling, interpolation or replacement also belong to protection range of the present utility model.

Claims (1)

1. realize the fractional order four systems automatic switchover analog circuit of Liu type system, it is characterized in that being, by operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U5, operational amplifier U8 and multiplier U4, multiplier U9, multiplier U10 and voltage comparator U7 and analog switch U6 form, described operational amplifier U1 connects voltage comparator U7, operational amplifier U5, operational amplifier U8, multiplier U4, operational amplifier U2, described operational amplifier U2 concatenation operation amplifier U1, operational amplifier U5, voltage comparator U7, operational amplifier U8, described operational amplifier U3 concatenation operation amplifier U2, multiplier U4, described operational amplifier U5 connecting analog switch U6, described voltage comparator U7 connecting analog switch U6, described operational amplifier U8 concatenation operation amplifier U5, multiplier U9, multiplier U10, described multiplier U9 connecting analog switch U6, described multiplier U10 connecting analog switch U6;
The 1st pin of described operational amplifier U1 joins by resistance R x and the 2nd pin, join by resistance R 1 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc11 of the 6th pin elder generation is in parallel with capacitor C 11, connecting resistance Rc12 and capacitor C 12 is in parallel again, connect the 7th pin behind connecting resistance Rc13 and capacitor C 13 in parallel again, the 7th pin connects the 13rd pin by resistance R 13, connects the 2nd pin of U2 by potentiometer R23, connect the 1st pin of U4, connect the 2nd pin of U5 by resistance R a1, connect the 5th pin of U7, connect the 2nd pin of U8, connect the 1st pin of U9, the 8th pin connects the 9th pin by resistance R 25, and the 13rd pin connects the 14th pin by resistance R 14, and the 14th pin connects the 2nd pin by potentiometer R11;
The 1st pin of described operational amplifier U2 joins by resistance R y and the 2nd pin, join by resistance R 2 and the 6th pin, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the connecting resistance Rc21 of the 6th pin elder generation is in parallel with capacitor C 21, connect again the in parallel of Rc22 and capacitor C 22, connect the 7th pin after connecing again Rc23 and capacitor C 23 in parallel, the 7th pin connects the 9th pin of U1 by the R24 of resistance, connects the 2nd pin of U1 by potentiometer R12, connects the 11st pin of U5 by Ra6, connect the 11st pin of U7, connect the 13rd pin of U8, connect the 1st pin of U10, the 8th pin connects the 13rd pin by resistance R 33, connect first the in parallel of Rc31 and capacitor C 31, connect the in parallel of Rc32 and capacitor C 32 again, connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 in parallel again, the 13rd pin connects the 14th pin by resistance R 34, the 14th pin connects the 2nd pin of U3 by potentiometer R32, connects the 3rd pin of U4;
Described operational amplifier U3 the 1st pin joins by resistance R z and the 2nd pin, join by the 9th pin of resistance R 3 with U2, U3 the 2nd pin connects 14 pins of U2 by R32, the 3rd pin ground connection, the 4th pin meets VCC, the 5th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled, and the 11st pin meets VEE;
The 1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;
The 1st pin of described operational amplifier U5 connects the 2nd pin by diode D3, the 2nd pin connects the 7th pin of U1 by resistance R a1, series connection the 1st pin by resistance R a2 and diode D4, series connection the 6th pin by resistance R a1 and resistance R a5, connect the 6th pin by resistance R a3, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin connects the 7th pin by resistance R a4, the 7th pin connects the 6th pin of U6, the 8th pin connects the 4th pin of U6, connects the 9th pin by resistance R a9, and the 9th pin is by series connection the 14th pin of resistance R a8 and diode D6, the 13rd pin is by series connection the 14th pin of resistance R a7 and diode D6, and the 14th pin connects the 13rd pin by diode D5;
The 2nd pin of the 1st pin U7 of described analog switch U6, the 2nd pin, the 14th pin connect positive 14V power supply, and the 3rd pin connects negative 14V power supply, the 4th pin connects the 7th pin of U10, and the 5th pin connects the 8th pin of U5, and the 6th pin connects the 7th pin of U9, the 7th pin connects the 7th pin of U5, and the 8th pin connects the 2nd pin of U3, the 9th pin by potentiometer R31, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin is unsettled, the 15th pin ground connection, the 16th pin connect the 13rd pin of U7;
The 1st pin of described voltage comparator U7, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 14th pin are unsettled, the 2nd pin connects positive 14V power supply by resistance R 01, series connection ground connection by diode D1 and resistance R 02, the 13rd pin connects positive 14V power supply by resistance R 03, by the series connection ground connection of diode D2 and resistance R 03;
The 1st pin of described operational amplifier U8 connects the 6th pin by resistance R s 1, the 2nd pin connects the 7th pin of U1, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin connects the 7th pin by resistance R s2, the 7th pin connects the 3rd pin of U10, the 8th pin connects the 3rd pin of U9, and the 9th pin connects the 14th pin by resistance R s3, and the 13rd pin connects the 7th pin of U2;
The 1st pin of described multiplier U9 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 6th pin of U6, and the 8th pin meets VCC;
The 1st pin of described multiplier U10 connects the 7th pin of U2, and the 3rd pin connects the 7th pin of U8, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 4th pin the 8th pin that the 7th pin meets U6 meets VCC.
CN 201220512586 2012-10-08 2012-10-08 Fractional order four-system automatic switching analog circuit for Liu-type systems Expired - Fee Related CN202818324U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201220512586 CN202818324U (en) 2012-10-08 2012-10-08 Fractional order four-system automatic switching analog circuit for Liu-type systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201220512586 CN202818324U (en) 2012-10-08 2012-10-08 Fractional order four-system automatic switching analog circuit for Liu-type systems

Publications (1)

Publication Number Publication Date
CN202818324U true CN202818324U (en) 2013-03-20

Family

ID=47877128

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201220512586 Expired - Fee Related CN202818324U (en) 2012-10-08 2012-10-08 Fractional order four-system automatic switching analog circuit for Liu-type systems

Country Status (1)

Country Link
CN (1) CN202818324U (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103368723A (en) * 2013-07-03 2013-10-23 淄博职业学院 Fractional order four-system automatic switching chaotic system method and analog circuit
WO2014048053A1 (en) * 2012-09-27 2014-04-03 Wang Zhonglin Analog circuit and method for fractional-order four-system automatic switching chaotic system based on lorenz type system
WO2014048054A1 (en) * 2012-09-27 2014-04-03 Wang Zhonglin Analog circuit and method for fractional-order four-system automatic switching chaotic system based on liu type system
CN103812640A (en) * 2014-02-22 2014-05-21 滨州学院 Method and circuit for switching Liu (line interface unit) chaos system with different fraction orders and xy
CN104393982A (en) * 2014-11-11 2015-03-04 韩敬伟 0.9-order xy-containing Liu chaotic system circuit based on hybrid fractional order integrating circuit module
CN104468076A (en) * 2014-11-11 2015-03-25 王晓红 0.8-order Liu chaotic system circuit realizing method based on chain type fractional order integral circuit module

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014048053A1 (en) * 2012-09-27 2014-04-03 Wang Zhonglin Analog circuit and method for fractional-order four-system automatic switching chaotic system based on lorenz type system
WO2014048054A1 (en) * 2012-09-27 2014-04-03 Wang Zhonglin Analog circuit and method for fractional-order four-system automatic switching chaotic system based on liu type system
CN103368723A (en) * 2013-07-03 2013-10-23 淄博职业学院 Fractional order four-system automatic switching chaotic system method and analog circuit
CN103368723B (en) * 2013-07-03 2017-02-15 淄博职业学院 Fractional order four-system automatic switching chaotic system method and analog circuit
CN103812640A (en) * 2014-02-22 2014-05-21 滨州学院 Method and circuit for switching Liu (line interface unit) chaos system with different fraction orders and xy
CN104393982A (en) * 2014-11-11 2015-03-04 韩敬伟 0.9-order xy-containing Liu chaotic system circuit based on hybrid fractional order integrating circuit module
CN104468076A (en) * 2014-11-11 2015-03-25 王晓红 0.8-order Liu chaotic system circuit realizing method based on chain type fractional order integral circuit module

Similar Documents

Publication Publication Date Title
CN202818324U (en) Fractional order four-system automatic switching analog circuit for Liu-type systems
CN102904709A (en) Chaotic system method and analog circuit for automatic switching of four systems of fractional order based on Chen type system
CN202818326U (en) Fractional order four-system automatic switching analog circuit for Chen-type systems
CN102904708B (en) Method for automatically switching fractional-order chaotic system by four systems based on Lu-type system and analog circuit
CN102916802B (en) Fractional-order automatic switching chaotic system method for four Lorenz type systems and analog circuit
CN102957531B (en) Method for realizing automatic switching of seven Lorenz type chaotic systems and analog circuit
CN102385659A (en) Method for realizing fractional-order three-system automatic-switchover chaotic system and analog circuit
CN102932133A (en) Method for fractional-order four-system automatic switching chaotic system based on Liu type system, and simulation circuit
CN202475442U (en) Circuit for realizing integral order and fractional order automatic switching chaotic system
CN103368723B (en) Fractional order four-system automatic switching chaotic system method and analog circuit
CN102970128A (en) Method for achieving automatic switching of seven Chen type chaotic systems and analog circuit
CN202818325U (en) Fractional order four-system automatic switching analog circuit for Lorenz-type systems
CN102497263A (en) Method for realizing integer order and fractional order automatic switching chaotic system and analog circuit
CN104202143B (en) Based on the four-dimension of five chaos systems the simplest without the analog circuit of balance point hyperchaotic system
CN101931526A (en) A method and analog circuit for realizing automatic switching of chaotic system
CN104202140A (en) Four-dimensional balance point-free hyperchaotic system based on five-simplest chaotic system, and analogue circuit
CN104836658B (en) A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated
CN202841154U (en) Realize the automatic switching analog circuit of fractional order four systems of Lü type system
CN101355417A (en) Third-order autonomous chaotic system
CN202043091U (en) Analog Circuit Realizing Automatic Switching of Chaotic System
Xu et al. Hall algebras of odd periodic triangulated categories
CN102427349A (en) PWM (Pulse-Width Modulation) circuit adopting FPGA (Field Programmable Gate Array)
CN105634725A (en) Ultimate boundary estimation facilitating Lorenz-type hyperchaotic system construction method with different variable
CN104283670B (en) Four system automatic switchover hyperchaotic system building method and analog circuits based on L ü system
Deane Improved modelling of pumped hydro energy storage

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130320

Termination date: 20131008