CN105634725A - Ultimate boundary estimation facilitating Lorenz-type hyperchaotic system construction method with different variable - Google Patents

Abstract

The invention provides an ultimate boundary estimation facilitating Lorenz-type hyperchaotic system construction method with a different variable. By using an operational amplifier U1, an operational amplifier U2, resistors and capacitors, add and integral operations are realized; by using an operational amplifier U3 and resistors, an inverting operation is realized; and a multiplication operation is realized through a multiplier U4 and a multiplier U5. The operational amplifier U1 is connected with the operational amplifier U2, the operational amplifier U3 and the multiplier U5; the operational amplifier U2 is connected with the operational amplifier U3 and the multiplier U4; the operational amplifiers U1, U2 and U3 adopt LF347BN; and the multiplier U4 and U5 adopt AD633JN. On the basis of a Lorenz-type chaotic system, the ultimate boundary estimation facilitating Lorenz-type hyperchaotic system construction method with a different variable and a circuit construction method are designed, and an analog circuit is also designed to realize the chaotic system, thus to provide a new hyperchaotic system signal source for chaos synchronization and control.

Description

The Lorenz type hyperchaotic system construction process being beneficial to ultimate boundary estimation of a kind of different variable

Technical field

The present invention relates to a kind of chaos system and circuit, in particular to the Lorenz type hyperchaotic system construction process being beneficial to ultimate boundary estimation and the circuit of a kind of different variable.

Background technology

The control in chaos is estimated on the border of hyperchaotic system, engineer applied aspect is synchronously waited to have important meaning, currently, the method constructing four dimension ultra-chaos is mainly on the basis of three-dimensional chaotic system, increase by a dimension and form four-dimensional hyperchaotic system, but the hyperchaotic system formed is not easy to carry out ultimate boundary estimation, the feature that the hyperchaotic system that can carry out ultimate boundary estimation has is: the characteristic element of Jacobian matrix principal diagonal is all negative value, the hyperchaotic system of the present invention's structure has the advantages that the characteristic element of Jacobian matrix principal diagonal is all negative value, ultimate boundary estimation can be carried out, this is for the control of super chaos, synchronous etc. have important job applications prospect.

Summary of the invention

The technical problem to be solved in the present invention is to provide the Lorenz type hyperchaotic system construction process being beneficial to ultimate boundary estimation and the circuit of a kind of different variable:

1. the Lorenz type hyperchaotic system construction process being beneficial to ultimate boundary estimation of a different variable, it is characterised in that, comprise the following steps:

(1) Lorenz type chaos system i is:

$\begin{array}{cc}\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=bx-xz-cy\\ dz/dt=xy-dz\end{array}\right.& a=12,b=23,c=1,d=2.1\end{array}---i$

In formula, x, y, z are state variables, and a, b, c, d are system parameter;

(2) the variable w of a reform is built₁:

dw₁/ dt=-kx-rw₁K=5, r=0.1ii

W in formula₁For state variables, k, r are system parameter;

(3) the variable w of a reform is built₂:

dw₂/ dt=-ky-rw₂K=5, r=0.1iii

W in formula₂For state variables, k, r are system parameter;

(4) constructing one selects function iv that ii and iii forms a dimension switching variable w:

$f\left(x\right)=\left\{\begin{array}{cc}-x& x\&GreaterEqual;0\\ -y& x<0\end{array}\right.---iv$

Dw/dt=kf (x)-rwk=5, r=0.1v

In formula, w is state variables, and f (x) is switching function, and k, r are system parameter;

(5) using variable w as a dimension system variable, being added in the second party journey of Lorenz type chaos system i, obtaining a kind of Lorenz type hyperchaotic system vi being beneficial to ultimate boundary estimation is:

$\begin{array}{cc}\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=bx-xz-cy+w\\ dz/dt=xy-dz\\ dw/dt=kf\left(x\right)-rw\end{array}\right.& a=12,b=23,c=1,d=2.1,k=5,r=0.1\end{array}---vi$

In formula, x, y, z, w are state variables, and f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;

(6) based on the circuit of system vi structure, operational amplifier U1, operational amplifier U2 and resistance, electric capacity is utilized to realize addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, operational amplifier U6 and selector switch U7 realizes switching functional operation, described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector switch U7 adopts ADG409;

Described operational amplifier U1 connects operational amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, described operational amplifier U3 connects operational amplifier U1, operational amplifier U2, operational amplifier U6, selector switch U7 and multiplier U4, described multiplier U4 connects operational amplifier U1, and described multiplier U5 connects operational amplifier U2; Described operational amplifier U6 connects selector switch U7, and described selector switch U7 connects operational amplifier U2;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 is connected with the 2nd pin of operational amplifier U1 by resistance Ry4, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 4th pin of selector switch U7, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 connects with the 5th pin of selector switch U7, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;

1st pin of described operational amplifier U6 is connected with the 1st pin of selector switch U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.

2nd pin of described selector switch U7 and the 14th pin rank VCC, 3rd pin of selector switch U7 meets VEE, 15th pin of selector switch U7 and the 16th pin ground connection, 8th pin of selector switch U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector switch U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.

2. the Lorenz type hyperchaotic system circuit being beneficial to ultimate boundary estimation of a different variable, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, operational amplifier U6 and selector switch U7 realizes switching functional operation, operational amplifier U1 connects operational amplifier U3 and U6, operational amplifier U1 connects multiplier U4 and U5 and selector switch U7, described operational amplifier U1, U2, U3 and U6 adopts LF347BN, described multiplier U4 and U5 adopts AD633JN, described selector switch U7 adopts ADG409,

Described operational amplifier U1 connects operational amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, described operational amplifier U3 connects operational amplifier U1, operational amplifier U2, operational amplifier U6, selector switch U7 and multiplier U4, described multiplier U4 connects operational amplifier U1, and described multiplier U5 connects operational amplifier U2; Described operational amplifier U6 connects selector switch U7, and described selector switch U7 connects operational amplifier U2;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 is connected with the 2nd pin of operational amplifier U1 by resistance Ry4, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 4th pin of selector switch U7, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 connects with the 5th pin of selector switch U7, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;

1st pin of described operational amplifier U6 is connected with the 1st pin of selector switch U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.

2nd pin of described selector switch U7 and the 14th pin rank VCC, 3rd pin of selector switch U7 meets VEE, 15th pin of selector switch U7 and the 16th pin ground connection, 8th pin of selector switch U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector switch U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.

Useful effect: the present invention is on the basis of Lorenz type chaos system, devise the Lorenz type hyperchaotic system construction process being beneficial to ultimate boundary estimation of a kind of different variable and design a mimic channel and carry out realizing this chaos system, for the synchronous of chaos and control provide new hyperchaotic system signal source.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 is the actual interface chart of circuit of multiplier U4 and operational amplifier U1.

Fig. 3 is the actual interface chart of circuit of operational amplifier U3.

Fig. 4 is the actual interface chart of circuit of multiplier U5 and operational amplifier U2.

Fig. 5 is the actual interface chart of circuit of selector switch U7 and operational amplifier U6.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 5.

1. the Lorenz type hyperchaotic system construction process being beneficial to ultimate boundary estimation of a different variable, it is characterised in that, comprise the following steps:

(1) Lorenz type chaos system i is:

$\begin{array}{cc}\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=bx-xz-cy\\ dz/dt=xy-dz\end{array}\right.& a=12,b=23,c=1,d=2.1\end{array}---i$

In formula, x, y, z are state variables, and a, b, c, d are system parameter;

(2) the variable w of a reform is built₁:

dw₁/ dt=-kx-rw₁K=5, r=0.1ii

W in formula₁For state variables, k, r are system parameter;

(3) the variable w of a reform is built₂:

dw₂/ dt=-ky-rw₂K=5, r=0.1iii

W in formula₂For state variables, k, r are system parameter;

(4) constructing one selects function iv that ii and iii forms a dimension switching variable w:

$f\left(x\right)=\left\{\begin{array}{cc}-x& x\&GreaterEqual;0\\ -y& x<0\end{array}\right.---iv$

Dw/dt=kf (x)-rwk=5, r=0.1v

In formula, w is state variables, and f (x) is switching function, and k, r are system parameter;

(5) using variable w as a dimension system variable, being added in the second party journey of Lorenz type chaos system i, obtaining a kind of Lorenz type hyperchaotic system vi being beneficial to ultimate boundary estimation is:

$\begin{array}{cc}\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=bx-xz-cy+w\\ dz/dt=xy-dz\\ dw/dt=kf\left(x\right)-rw\end{array}\right.& a=12,b=23,c=1,d=2.1,k=5,r=0.1\end{array}---vi$

In formula, x, y, z, w are state variables, and f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;

(6) based on the circuit of system vi structure, operational amplifier U1, operational amplifier U2 and resistance, electric capacity is utilized to realize addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, operational amplifier U6 and selector switch U7 realizes switching functional operation, described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector switch U7 adopts ADG409;

Described operational amplifier U1 connects operational amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, described operational amplifier U3 connects operational amplifier U1, operational amplifier U2, operational amplifier U6, selector switch U7 and multiplier U4, described multiplier U4 connects operational amplifier U1, and described multiplier U5 connects operational amplifier U2; Described operational amplifier U6 connects selector switch U7, and described selector switch U7 connects operational amplifier U2;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 is connected with the 2nd pin of operational amplifier U1 by resistance Ry4, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 4th pin of selector switch U7, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 connects with the 5th pin of selector switch U7, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;

1st pin of described operational amplifier U6 is connected with the 1st pin of selector switch U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.

2nd pin of described selector switch U7 and the 14th pin rank VCC, 3rd pin of selector switch U7 meets VEE, 15th pin of selector switch U7 and the 16th pin ground connection, 8th pin of selector switch U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector switch U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.

2. the Lorenz type hyperchaotic system circuit being beneficial to ultimate boundary estimation of a different variable, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, operational amplifier U6 and selector switch U7 realizes switching functional operation, operational amplifier U1 connects operational amplifier U3 and U6, operational amplifier U1 connects multiplier U4 and U5 and selector switch U7, described operational amplifier U1, U2, U3 and U6 adopts LF347BN, described multiplier U4 and U5 adopts AD633JN, described selector switch U7 adopts ADG409,

Described operational amplifier U1 connects operational amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, described operational amplifier U3 connects operational amplifier U1, operational amplifier U2, operational amplifier U6, selector switch U7 and multiplier U4, described multiplier U4 connects operational amplifier U1, and described multiplier U5 connects operational amplifier U2; Described operational amplifier U6 connects selector switch U7, and described selector switch U7 connects operational amplifier U2;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 is connected with the 2nd pin of operational amplifier U1 by resistance Ry4, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 4th pin of selector switch U7, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 connects with the 5th pin of selector switch U7, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;

1st pin of described operational amplifier U6 is connected with the 1st pin of selector switch U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.

2nd pin of described selector switch U7 and the 14th pin rank VCC, 3rd pin of selector switch U7 meets VEE, 15th pin of selector switch U7 and the 16th pin ground connection, 8th pin of selector switch U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector switch U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and change, remodeling, interpolation or the replacement that those skilled in the art make in the essential scope of the present invention, also belongs to protection scope of the present invention.

Claims (1)

1. the Lorenz type hyperchaotic system construction process being beneficial to ultimate boundary estimation of a different variable, it is characterised in that, comprise the following steps:

(1) Lorenz type chaos system i is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=bx-xz-cy\\ dz/dt=xy-dz\end{array}& a=12,b=23,c=1,d=2.1\end{array}\right.---i$

In formula, x, y, z are state variables, and a, b, c, d are system parameter;

(2) the variable w of a reform is built₁:

dw₁/ dt=-kx-rw₁K=5, r=0.1ii

W in formula₁For state variables, k, r are system parameter;

(3) the variable w of a reform is built₂:

dw₂/ dt=-ky-rw₂K=5, r=0.1iii

W in formula₂For state variables, k, r are system parameter;

(4) constructing one selects function iv that ii and iii forms a dimension switching variable w:

$f\left(x\right)=\left\{\begin{array}{cc}-x& x\&GreaterEqual;0\\ -y& x<0\end{array}\right.---iv$

Dw/dt=kf (x)-rwk=5, r=0.1v

In formula, w is state variables, and f (x) is switching function, and k, r are system parameter;

(5) using variable w as a dimension system variable, being added in the second party journey of Lorenz type chaos system i, obtaining a kind of Lorenz type hyperchaotic system vi being beneficial to ultimate boundary estimation is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=bx-xz-cy+w\\ dz/dt=xy-dz\\ dw/dt=kf\left(x\right)-rw\end{array}& a=12,b=23,c=1,d=2.1,k=5,r=0.1\end{array}\right.---vi$

In formula, x, y, z, w are state variables, and f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;

(6) based on the circuit of system vi structure, operational amplifier U1, operational amplifier U2 and resistance, electric capacity is utilized to realize addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, operational amplifier U6 and selector switch U7 realizes switching functional operation, described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector switch U7 adopts ADG409;

Described operational amplifier U1 connects operational amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, described operational amplifier U3 connects operational amplifier U1, operational amplifier U2, operational amplifier U6, selector switch U7 and multiplier U4, described multiplier U4 connects operational amplifier U1, and described multiplier U5 connects operational amplifier U2; Described operational amplifier U6 connects selector switch U7, and described selector switch U7 connects operational amplifier U2;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 is connected with the 2nd pin of operational amplifier U1 by resistance Ry4, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 4th pin of selector switch U7, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 connects with the 5th pin of selector switch U7, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;

1st pin of described operational amplifier U6 is connected with the 1st pin of selector switch U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;

2nd pin of described selector switch U7 and the 14th pin rank VCC, 3rd pin of selector switch U7 meets VEE, 15th pin of selector switch U7 and the 16th pin ground connection, 8th pin of selector switch U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector switch U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.