CN104486061A - Construction method and circuit of classic Lorenz hyper-chaos system based on memristor - Google Patents

Abstract

The invention relates to a construction method and a circuit of a classic Lorenz hyper-chaos system based on a memristor. The method comprises the following steps: utilizing an operation amplifier U1, an operation amplifier U2, an operation amplifier U3, a resistor and a capacitor to realize addition, phase inversion and integral operation; utilizing a multiplying unit U4 and a multiplying unit U5 to realize multiplication operation in the system; utilizing an operation amplifier U6, a multiplying unit U7 and a multiplying unit U8 to realize a memristor model mentioned in the invention, wherein the operation amplifier U1 is connected with the operation amplifier U2, the operation amplifier U6, the multiplying unit U4, the multiplying unit U5 and the multiplying unit U8; the operation amplifier U2 is connected with the operation amplifier U3 and the multiplying unit U4; the operation amplifier U3 is connected with the multiplying unit U5; the operation amplifier U6 is connected with the multiplying unit U7 and the multiplying unit U8; the multiplying unit U7 is connected with the multiplying unit U8. The method disclosed by the invention is used for forming a four-dimensional hyper-chaos system by adding one dimension with one memristor element based on the classic Lorenz hyper-chaos system and provides a new method for applying the memristor to the hyper-chaos system.

Description

Based on construction method and the circuit of the classical Lorenz hyperchaotic system of memristor

Technical field

The present invention relates to a kind of chaos system and circuit realiration, particularly a kind of construction method of the classical Lorenz hyperchaotic system based on memristor and circuit.

Background technology

Current, construct the method for four dimension ultra-chaos mainly on the basis of three-dimensional chaotic system, increase one dimension and form four-dimensional hyperchaotic system, memristor was as the newfound physical component in HP Lab in 2008, the Cai Shi diode in cai's circuit can be replaced to form four dimensional chaos system, will form hyperchaos in cai's circuit then needs 2 to recall resistance element, therefore five dimensions or five are needed to tie up above system, having, the circuit system realizing hyperchaos in the four-dimensional system recalling resistance element is also fewer, the method that memristor is applied to four-dimensional hyperchaotic system is not also suggested, this is the deficiencies in the prior art parts.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of construction method and circuit of the classical Lorenz hyperchaotic system based on memristor:

1., based on the construction method of the classical Lorenz hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) classical Lorenz chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-y-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{cz}\end{array}\right.,a=10,b=30,c=8/3---i$

In formula, x, y, z are state variable;

(2) memristor that the present invention adopts is magnetic control memristor model ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) must recall the magnetic control memristor model differentiate of ii and lead device model iii and be:

represent that magnetic control is recalled and led, m, n be greater than zero parameter;

(4) magnetic control recalled lead device model iii as unidimensional system variable, be added on the second equation of classical Lorenz chaos system, obtain a kind of classical Lorenz hyperchaotic system iv based on memristor:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-y-\mathrm{xz}-\mathrm{kxW}\left(u\right)\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{cz}\\ \mathrm{du}/\mathrm{dt}=-x\end{array}\right.---\mathrm{iv}$

In formula, x, y, z, u are state variable, parameter value a=10, b=30, c=8/3, m=8, n=0.006, k=1;

(5) based on the circuit of system iv structure, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity is utilized to realize addition, anti-phase and integral operation, utilize the multiplying that multiplier U4 and multiplier U5 realizes in system, utilize the memristor model that operational amplifier U6 and multiplier U7, multiplier U8 and electric capacity realize in the present invention, described operational amplifier U1, U2 and U3 adopt LF347BN, described multiplier U4, U5, U7 and U8 adopt AD633JN, and described operational amplifier U6 adopts LF353N;

1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 1st pin directly connects the 1st pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and the 8th pin connects the 13rd pin by resistance Ry2, is connect the 13rd pin of operational amplifier U1 by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 3rd pin of U5, and the 13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4;

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, 1st pin of the 3rd pin concatenation operation amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of the 1st pin concatenation operation amplifier U1 of described multiplier U5,2nd pin, the 4th pin, the 6th pin ground connection, 8th pin of the 3rd pin concatenation operation amplifier U2,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1.

2. magnetic control is recalled and is led device and realized by operational amplifier U6 and multiplier U7 and multiplier U8 according to claim 1, described operational amplifier U6 concatenation operation amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, multiplier U8 concatenation operation amplifier U2;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, by the 7th pin of resistance R8 concatenation operation amplifier U1,7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,7th pin of the 1st pin direct concatenation operation amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.

3. based on the classical Lorenz hyperchaotic system circuit of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, utilize the memristor model that operational amplifier U6 and multiplier U7 and multiplier U8 realizes in the present invention, operational amplifier U1 concatenation operation amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, multiplier U5, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N,

1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 1st pin directly connects the 1st pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and the 8th pin connects the 13rd pin by resistance Ry2, is connect the 13rd pin of operational amplifier U1 by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 3rd pin of U5, and the 13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4;

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, 1st pin of the 3rd pin concatenation operation amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of the 1st pin concatenation operation amplifier U1 of described multiplier U5,2nd pin, the 4th pin, the 6th pin ground connection, 8th pin of the 3rd pin concatenation operation amplifier U2,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, by the 7th pin of resistance R8 concatenation operation amplifier U1,7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,7th pin of the 1st pin direct concatenation operation amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.

Beneficial effect: the present invention, on the basis of the Lorenz chaos system of classics, utilizes one to recall resistance element increase one dimension and forms four-dimensional hyperchaotic system, propose the new method that memristor is applied to hyperchaotic system.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 realizes in the present invention recalling the actual connection layout of the circuit of leading device.

Fig. 3 is the actual connection layout of circuit of operational amplifier U1.

Fig. 4 is the actual connection layout of circuit of multiplier U4 and operational amplifier U2.

Fig. 5 is the actual connection layout of circuit of multiplier U5 and operational amplifier U3.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 5.

1., based on the construction method of the classical Lorenz hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) classical Lorenz chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-y-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{cz}\end{array}\right.,a=10,b=30,c=8/3---i$

In formula, x, y, z are state variable;

(2) memristor that the present invention adopts is magnetic control memristor model ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) must recall the magnetic control memristor model differentiate of ii and lead device model iii and be:

represent that magnetic control is recalled and led, m, n be greater than zero parameter;

(4) magnetic control recalled lead device model iii as unidimensional system variable, be added on the second equation of classical Lorenz chaos system, obtain a kind of classical Lorenz hyperchaotic system iv based on memristor:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-y-\mathrm{xz}-\mathrm{kxW}\left(u\right)\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{cz}\\ \mathrm{du}/\mathrm{dt}=-x\end{array}\right.---\mathrm{iv}$

In formula, x, y, z, u are state variable, parameter value a=10, b=30, c=8/3, m=8, n=0.006, k=1;

(5) based on the circuit of system iv structure, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity is utilized to realize addition, anti-phase and integral operation, utilize the multiplying that multiplier U4 and multiplier U5 realizes in system, utilize the memristor model that operational amplifier U6 and multiplier U7, multiplier U8 and electric capacity realize in the present invention, described operational amplifier U1, U2 and U3 adopt LF347BN, described multiplier U4, U5, U7 and U8 adopt AD633JN, and described operational amplifier U6 adopts LF353N;

1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 1st pin directly connects the 1st pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and the 8th pin connects the 13rd pin by resistance Ry2, is connect the 13rd pin of operational amplifier U1 by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 3rd pin of U5, and the 13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4;

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, 1st pin of the 3rd pin concatenation operation amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of the 1st pin concatenation operation amplifier U1 of described multiplier U5,2nd pin, the 4th pin, the 6th pin ground connection, 8th pin of the 3rd pin concatenation operation amplifier U2,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1.

2. magnetic control is recalled and is led device and realized by operational amplifier U6 and multiplier U7 and multiplier U8 according to claim 1, described operational amplifier U6 concatenation operation amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, multiplier U8 concatenation operation amplifier U2;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, by the 7th pin of resistance R8 concatenation operation amplifier U1,7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,7th pin of the 1st pin direct concatenation operation amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.

3. based on the classical Lorenz hyperchaotic system circuit of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, utilize the memristor model that operational amplifier U6 and multiplier U7 and multiplier U8 realizes in the present invention, operational amplifier U1 concatenation operation amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, multiplier U5, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N,

1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 1st pin directly connects the 1st pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and the 8th pin connects the 13rd pin by resistance Ry2, is connect the 13rd pin of operational amplifier U1 by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 3rd pin of U5, and the 13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4;

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, 1st pin of the 3rd pin concatenation operation amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of the 1st pin concatenation operation amplifier U1 of described multiplier U5,2nd pin, the 4th pin, the 6th pin ground connection, 8th pin of the 3rd pin concatenation operation amplifier U2,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, by the 7th pin of resistance R8 concatenation operation amplifier U1,7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,7th pin of the 1st pin direct concatenation operation amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (3)

1., based on the construction method of the classical Lorenz hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) classical Lorenz chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-y-\mathrm{xz}\\ \mathrm{dx}/\mathrm{dt}=\mathrm{xy}-\mathrm{cz}\end{array}\right.,a=10,b=30,c=8/3---i$

In formula, x, y, z are state variable;

(2) memristor that the present invention adopts is magnetic control memristor model ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) must recall the magnetic control memristor model differentiate of ii and lead device model iii and be:

represent that magnetic control is recalled and led, m, n be greater than zero parameter;

(4) magnetic control recalled lead device model iii as unidimensional system variable, be added on the second equation of classical Lorenz chaos system, obtain a kind of classical Lorenz hyperchaotic system iv based on memristor:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-y-\mathrm{xz}-\mathrm{kxW}\left(u\right)\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{cz}\\ \mathrm{du}/\mathrm{dt}=-x\end{array}\right.---\mathrm{iv}$

In formula, x, y, z, u are state variable, parameter value a=10, b=30, c=8/3, m=8, n=0.006, k=1;

(5) based on the circuit of system iv structure, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity is utilized to realize addition, anti-phase and integral operation, utilize the multiplying that multiplier U4 and multiplier U5 realizes in system, utilize the memristor model that operational amplifier U6 and multiplier U7, multiplier U8 and electric capacity realize in the present invention, described operational amplifier U1, U2 and U3 adopt LF347BN, described multiplier U4, U5, U7 and U8 adopt AD633JN, and described operational amplifier U6 adopts LF353N;

1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 1st pin directly connects the 1st pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and the 8th pin connects the 13rd pin by resistance Ry2, is connect the 13rd pin of operational amplifier U1 by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 3rd pin of U5, and the 13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4;

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, 1st pin of the 3rd pin concatenation operation amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of the 1st pin concatenation operation amplifier U1 of described multiplier U5,2nd pin, the 4th pin, the 6th pin ground connection, 8th pin of the 3rd pin concatenation operation amplifier U2,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1.

2. magnetic control is recalled and is led device and realized by operational amplifier U6 and multiplier U7 and multiplier U8 according to claim 1, described operational amplifier U6 concatenation operation amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, multiplier U8 concatenation operation amplifier U2;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, by the 7th pin of resistance R8 concatenation operation amplifier U1,7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,7th pin of the 1st pin direct concatenation operation amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.

3. based on the classical Lorenz hyperchaotic system circuit of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, utilize the memristor model that operational amplifier U6 and multiplier U7 and multiplier U8 realizes in the present invention, operational amplifier U1 concatenation operation amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, multiplier U5, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N,

1st pin of described operational amplifier U1 connects the 2nd pin by resistance Cx, the 6th pin is connected by resistance R2, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 1st pin directly connects the 1st pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by memristor Ry4, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, the 2nd pin, the 6th pin, the 7th pin are unsettled, 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and the 8th pin connects the 13rd pin by resistance Ry2, is connect the 13rd pin of operational amplifier U1 by resistance Rx2, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 3rd pin of U5, and the 13rd pin connects the 14th pin by resistance Ry, and the 14th pin connects the 9th pin by resistance R4;

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

7th pin of the 1st pin concatenation operation amplifier U1 of described multiplier U4,2nd pin, the 4th pin, the 6th pin ground connection, 1st pin of the 3rd pin concatenation operation amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of the 1st pin concatenation operation amplifier U1 of described multiplier U5,2nd pin, the 4th pin, the 6th pin ground connection, 8th pin of the 3rd pin concatenation operation amplifier U2,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, by the 7th pin of resistance R8 concatenation operation amplifier U1,7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 7th pin of the 3rd pin concatenation operation amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,7th pin of the 1st pin direct concatenation operation amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.