CN104883250A - Lorenz-type hyperchaotic system construction method used for ultimate boundary estimation and circuit thereof - Google Patents

Abstract

The invention provides a Lorenz-type hyperchaotic system construction method used for ultimate boundary estimation and a circuit thereof. An operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used to realize addition and integration operations. An operational amplifier U3 and the resistor are used to realize an anti-phase operation. A multiplier U4 and a multiplier U5 are used to realize a multiplication operation in a system. The operational amplifier U1 is connected to the operational amplifier U2, the operational amplifier U3 and the multiplier U5. The operational amplifier U2 is connected to the operational amplifier U3 and the multiplier U4. The operational amplifiers U1, U2 and U3 adopt LF347BN. The multipliers U4 and U5 adopt AD633JN. In the invention, based on a Lorenz-type chaotic system, the Lorenz-type hyperchaotic system construction method used for the ultimate boundary estimation is constructed and a simulation circuit is designed so as to realize the chaotic system. A new hyperchaotic system signal source is provided for chaotic synchronization and control.

Description

A kind of Lorenz type hyperchaotic system construction method for ultimate boundary estimation and circuit

Technical field

The present invention relates to a kind of chaos system and circuit, particularly a kind of Lorenz type hyperchaotic system construction method for ultimate boundary estimation and circuit.

Background technology

The control in chaos is estimated on the border of hyperchaotic system, the synchronous engineer applied aspect that waits has great importance, current, construct the method for four dimension ultra-chaos mainly on the basis of three-dimensional chaotic system, increase one dimension and form four-dimensional hyperchaotic system, but the hyperchaotic system formed is not easy to carry out ultimate boundary estimation, the feature that the hyperchaotic system that can carry out ultimate boundary estimation has is: the characteristic element of Jacobian matrix leading diagonal is all negative value, the characteristic element that the hyperchaotic system of the present invention's structure has a Jacobian matrix leading diagonal is all the feature of negative value, ultimate boundary estimation can be carried out, this is for the control of hyperchaos, synchronous etc. have important job applications prospect.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of Lorenz type hyperchaotic system construction method for ultimate boundary estimation and circuit:

1., for the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated, it is characterized in that, comprise the following steps:

(1) Lorenz type chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{xz}-\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{dz}\end{array}\right.,a=12,b=23,c=1,d=2.1---i$

In formula, x, y, z are state variable, and a, b, c, d are system parameters;

(2) on chaos system i, one dimension variable w is increased:

dw/dt＝-ky-rw k＝5,r＝0.1 ii

In formula, w is state variable, and k, r are system parameters;

(3) using variable i i as unidimensional system variable, be added on first equation of Lorenz type chaos system i, obtain a kind of be beneficial to ultimate boundary estimate Lorenz type hyperchaotic system iii be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)+w\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{xz}-\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{dz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{ky}-\mathrm{rw}\end{array}\right.,a=12,b=23,c=1,d=2.1,k=5,r=0.1---\mathrm{iii}$

In formula, x, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;

(4) based on the circuit of system iii structure, operational amplifier U1, operational amplifier U2 and resistance, electric capacity is utilized to realize addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1, U2 and U3 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 connects and exports y, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 8th pin of operational amplifier U1 connects and exports x, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects and exports w, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U1 by resistance Rx3, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 8th pin of operational amplifier U2 connects and exports z, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC.

2. the Lorenz type hyperchaotic system circuit estimated for ultimate boundary, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3 and multiplier U5, described operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4 and U5 adopts AD633JN,

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 connects and exports y, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 8th pin of operational amplifier U1 connects and exports x, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects and exports w, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U1 by resistance Rx3, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 8th pin of operational amplifier U2 connects and exports z, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC.

Beneficial effect: the present invention is on the basis of Lorenz type chaos system, construct a kind of Lorenz type hyperchaotic system construction method for ultimate boundary estimation and design an analog circuit and carry out realizing this chaos system, for the synchronous of chaos and control provide new hyperchaotic system signal source.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 is the actual connection layout of circuit of multiplier U4 and operational amplifier U1.

Fig. 3 is the actual connection layout of circuit of multiplier U5 and operational amplifier U2.

Fig. 4 is the actual connection layout of circuit of operational amplifier U3.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 4.

1., for the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated, it is characterized in that, comprise the following steps:

(1) Lorenz type chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{xz}-\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{dz}\end{array}\right.,a=12,b=23,c=1,d=2.1---i$

In formula, x, y, z are state variable, and a, b, c, d are system parameters;

(2) on chaos system i, one dimension variable w is increased:

dw/dt＝-ky-rw k＝5,r＝0.1 ii

In formula, w is state variable, and k, r are system parameters;

(3) using variable i i as unidimensional system variable, be added on first equation of Lorenz type chaos system i, obtain a kind of be beneficial to ultimate boundary estimate Lorenz type hyperchaotic system iii be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)+w\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{xz}-\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{dz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{ky}-\mathrm{rw}\end{array}\right.,a=12,b=23,c=1,d=2.1,k=5,r=0.1---\mathrm{iii}$

In formula, x, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;

(4) based on the circuit of system iii structure, operational amplifier U1, operational amplifier U2 and resistance, electric capacity is utilized to realize addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1, U2 and U3 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 connects and exports y, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 8th pin of operational amplifier U1 connects and exports x, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects and exports w, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U1 by resistance Rx3, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 8th pin of operational amplifier U2 connects and exports z, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC.

2. the Lorenz type hyperchaotic system circuit estimated for ultimate boundary, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3 and multiplier U5, described operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4 and U5 adopts AD633JN,

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 connects and exports y, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 8th pin of operational amplifier U1 connects and exports x, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects and exports w, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U1 by resistance Rx3, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 8th pin of operational amplifier U2 connects and exports z, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1., for the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated, it is characterized in that, comprise the following steps:

(1) Lorenz type chaos system i is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{xz}-\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{dz}\end{array}\right.,a=12,b=23,c=1,d=2.1---i$

In formula, x, y, z are state variable, and a, b, c, d are system parameters;

(2) on chaos system i, one dimension variable w is increased:

dw/dt＝-ky-rw k＝5,r＝0.1 ii

In formula, w is state variable, and k, r are system parameters;

(3) using variable i i as unidimensional system variable, be added on first equation of Lorenz type chaos system i, obtain a kind of be beneficial to ultimate boundary estimate Lorenz type hyperchaotic system iii be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)+w\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{xz}-\mathrm{cy}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{dz}\\ \mathrm{dw}/\mathrm{dt}=-\mathrm{ky}-\mathrm{rw}\end{array}\right.,a=12,b=23,c=1,d=2.1,k=5,r=0.1---\mathrm{iii}$

In formula, x, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;

(4) based on the circuit of system iii structure, operational amplifier U1, operational amplifier U2 and resistance, electric capacity is utilized to realize addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1, U2 and U3 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN;

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 connects and exports y, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 8th pin of operational amplifier U1 connects and exports x, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects and exports w, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U1 by resistance Rx3, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 8th pin of operational amplifier U2 connects and exports z, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC.

2. the Lorenz type hyperchaotic system circuit estimated for ultimate boundary, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3 and multiplier U5, described operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4 and U5 adopts AD633JN,

1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 connects and exports y, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 8th pin of operational amplifier U1 connects and exports x, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,

1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects and exports w, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U1 by resistance Rx3, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 8th pin of operational amplifier U2 connects and exports z, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,

1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,

2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;

2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC.