CN105207769A - Memristor-based four-wing hyper-chaotic system self-adaptive synchronization method and circuit - Google Patents

Abstract

The invention relates to a chaotic system synchronization method and circuit, and particularly relates to a memristor-based four-wing hyper-chaotic system self-adaptive synchronization method and circuit. Acting as a newly discovered physical element of the Hewlett-Packard laboratories in 2008, a memristor can replace a chua's diode in a chua's circuit to form a chaotic system and can also act as an element to be additionally arranged in a three-dimensional chaotic system, such as a Lorenz system, a Chen system and a Lorenz system so as to form a hyper-chaotic system. A chaotic or hyper-chaotic formation method and circuit with the memristor acting the element are put forward at present, while the hyper-chaotic system synchronization method by means of the memristor acting as the element is not put forward, which is the defect in the prior art. A four-wing hyper-chaotic system is put forward by means of the memristor, based on which the chaotic system self-adaptive synchronization method is also put forward.

Description

A kind of adaptive synchronicity method of four wing hyperchaotic system based on memristor and circuit

Technical field

The present invention relates to a Synchronization of Chaotic Systems and circuit, particularly a kind of adaptive synchronicity method of four wing hyperchaotic system based on memristor and circuit.

Background technology

Memristor was as the newfound physical component in HP Lab in 2008, the Cai Shi diode in cai's circuit can be replaced to form chaos system, also three-dimensional chaotic system can be increased to as Lorenz system as element, in Chen system and Lu system, form hyperchaotic system, at present, memristor as element formed chaos or hyperchaos Method and circuits oneself be suggested, but the synchronous method utilizing memristor to form hyperchaotic system as an element does not still propose, this is the deficiencies in the prior art parts, the present invention utilizes memristor to propose four wing hyperchaotic system, and propose the adaptive synchronicity method of this chaos system on this basis.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of adaptive synchronicity method and circuit of four wing hyperchaotic system based on memristor, and the present invention adopts following technological means to realize goal of the invention:

1., based on an adaptive synchronicity method for four wing hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) three-dimensional chaotic system i is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=ax+byz\\ dy/dt=cy+dxz\\ dz/dt=ez+fxy\end{array}& a=0.35,b=-10,c=-0.6,d=0.3,e=-1.6,f=2\end{array}\right.---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on second equation of three-dimensional chaotic system i, and on the 3rd equation of system i increase a nonlinear terms xz, obtain a kind of four wing hyperchaotic system iv with memristor:

$\left\{\begin{array}{c}dx/dt=ax+byz\\ dy/dy=cy+dxz-kyW\left(u\right)\\ dz/dt=ez+fxy+gxz\\ du/dt=y\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(5) with described in iv based on four wing hyperchaotic system of memristor for drive system v:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt={\mathrm{ax}}_1+{\mathrm{by}}_1{z}_1\\ {\mathrm{dy}}_1/dt={\mathrm{cy}}_1+{\mathrm{dx}}_1{z}_1-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dz}}_1/dt={\mathrm{ez}}_1+{\mathrm{fx}}_1{y}_1+{\mathrm{gx}}_1{z}_1\\ {\mathrm{du}}_1/dt=y_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(6) with described in iv based on four wing hyperchaotic system of memristor for responding system vi:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt={\mathrm{ax}}_2+{\mathrm{by}}_2{z}_2+v_1\\ {\mathrm{dy}}_2/dt={\mathrm{cy}}_2+{\mathrm{dx}}_2{z}_2-{\mathrm{ky}}_{2}W\left(u_2\right)+v_2\\ {\mathrm{dz}}_2/dt={\mathrm{ez}}_2+{\mathrm{fx}}_2{y}_2+{\mathrm{gx}}_2{z}_2+v_3\\ {\mathrm{du}}_2/dt=y_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(7) error system e is defined ₁=(x ₂-x ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=-e_1\∫e_1^{2}dt\\ v_2=0\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt={\mathrm{ax}}_1+{\mathrm{by}}_1{z}_1\\ {\mathrm{dy}}_1/dt={\mathrm{cy}}_1+{\mathrm{dx}}_1{z}_1-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dz}}_1/dt={\mathrm{ez}}_1+{\mathrm{fx}}_1{y}_1+{\mathrm{gx}}_1{z}_1\\ {\mathrm{du}}_1/dt=y_1\\ {\mathrm{dx}}_2/dt={\mathrm{ax}}_2+{\mathrm{by}}_2{z}_2-(x_2-x_1)\∫{(x_2-x_1)}^{2}dt\\ {\mathrm{dy}}_2/dt={\mathrm{cy}}_2+{\mathrm{dx}}_2{z}_2-{\mathrm{ky}}_{2}W\left(u_2\right)\\ {\mathrm{dz}}_2/dt={\mathrm{ez}}_2+{\mathrm{fx}}_2{y}_2+{\mathrm{gx}}_2{z}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=y_2\end{array}\right.---ix$

2. the adaptive synchronicity circuit based on four wing hyperchaotic system of memristor, it is characterized in that: the adaptive synchronicity of a kind of four wing hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises four wing chaos system I circuit and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, four wing chaos system II circuit and memristor II circuit, and driving system circuit drives responding system circuit by signal;

Four wing chaos system I circuit are by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase output of the anti-phase adder input termination first via of the first via, the input of multiplier (A11) connects the anti-phase output on the second tunnel and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder of the output termination first via of multiplier (A11), the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the homophase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the in-phase input end on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3), the input of multiplier (A12) connects the in-phase input end of the first via and the integration output of memristor I respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A12),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, second road homophase of input termination four wing chaos system I circuit exports, and output connects the input of the second anti-phase adder in tunnel of four wing chaos system I circuit by 2 multipliers;

Four wing chaos system II circuit are by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase output of the anti-phase adder input termination first via of the first via, the input of multiplier (A1) connects the anti-phase output on the second tunnel and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder of the output termination first via of multiplier (A1), the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A5) connects the homophase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A5), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A6) connects the in-phase input end of the first via and the in-phase input end on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A6), the input of multiplier (A4) connects the in-phase input end of the first via and the integration output of memristor II respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A4),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination four wing chaos system II circuit exports, and output connects the input of the anti-phase adder of the first via of four wing chaos system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end of four wing chaos system I circuit first via and the reversed-phase output on four wing chaos system II circuit second tunnels, and multiplier (A9) exports the anti-phase adder input connecing four wing chaos system II circuit first via;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on four wing chaos system I circuit the 3rd tunnels and the reversed-phase output on four wing chaos system II circuit the 3rd tunnels, and multiplier (A10) exports the anti-phase adder input connecing four wing chaos system II circuit the 3rd tunnels.

Beneficial effect: the present invention utilizes memristor to propose four wing hyperchaotic system, and proposes the adaptive synchronicity method of this chaos system on this basis.

Accompanying drawing explanation

Fig. 1 is the electrical block diagram of the preferred embodiment of the present invention.

Fig. 2 is four wing chaos system I circuit diagrams in the present invention.

Fig. 3 is the circuit diagram of memristor I in the present invention.

Fig. 4 is four wing chaos system system II circuit diagrams in the present invention.

Fig. 5 is the circuit diagram of memristor II in the present invention.

Fig. 6 is the circuit diagram of middle controller 1 of the present invention.

Fig. 7 is the circuit diagram of middle controller 2 of the present invention.

Fig. 8 is the synchronous circuit design sketch of x1 and x2 in the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 8.

1., based on an adaptive synchronicity method for four wing hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) three-dimensional chaotic system i is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=ax+byz\\ dy/dt=cy+dxz\\ dz/dt=ez+fxy\end{array}& a=0.35,b=-10,c=-0.6,d=0.3,e=-1.6,f=2\end{array}\right.---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on second equation of three-dimensional chaotic system i, and on the 3rd equation of system i increase a nonlinear terms xz, obtain a kind of four wing hyperchaotic system iv with memristor:

$\left\{\begin{array}{c}dx/dt=ax+byz\\ dy/dt=cy+dxz-kyW\left(u\right)\\ dz/dt=ez+fxy+gxz\\ du/dt=y\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(5) with described in iv based on four wing hyperchaotic system of memristor for drive system v:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt={\mathrm{ax}}_1+{\mathrm{by}}_1{z}_1\\ {\mathrm{dy}}_1/dt={\mathrm{cy}}_1+{\mathrm{dx}}_1{z}_1-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dz}}_1/dt={\mathrm{ez}}_1+{\mathrm{fx}}_1{y}_1+{\mathrm{gx}}_1{z}_1\\ {\mathrm{du}}_1/dt=y_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(6) with described in iv based on four wing hyperchaotic system of memristor for responding system vi:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt={\mathrm{ax}}_2+{\mathrm{by}}_2{z}_2+v_1\\ {\mathrm{dy}}_2/dt={\mathrm{cy}}_2+{\mathrm{dx}}_2{z}_2-{\mathrm{ky}}_{2}W\left(u_2\right)+v_2\\ {\mathrm{dz}}_2/dt={\mathrm{ez}}_2+{\mathrm{fx}}_2{y}_2+{\mathrm{gx}}_2{z}_2+v_3\\ {\mathrm{du}}_2/dt=y_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(7) error system e is defined ₁=(x ₂-x ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=-e_1\∫e_1^{2}dt\\ v_2=0\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt={\mathrm{ax}}_1+{\mathrm{by}}_1{z}_1\\ {\mathrm{dy}}_1/dt={\mathrm{cy}}_1+{\mathrm{dx}}_1{z}_1-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dz}}_1/dt={\mathrm{ez}}_1+{\mathrm{fx}}_1{y}_1+{\mathrm{gx}}_1{z}_1\\ {\mathrm{du}}_1/dt=y_1\\ {\mathrm{dx}}_2/dt={\mathrm{ax}}_2+{\mathrm{by}}_2{z}_2-(x_2-x_1)\∫{(x_2-x_1)}^{2}dt\\ {\mathrm{dy}}_2/dt={\mathrm{cy}}_2+{\mathrm{dx}}_2{z}_2-{\mathrm{ky}}_{2}W\left(u_2\right)\\ {\mathrm{dz}}_2/dt={\mathrm{ez}}_2+{\mathrm{fx}}_2{y}_2+{\mathrm{gx}}_2{z}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=y_2\end{array}\right.---ix$

2. the adaptive synchronicity circuit based on four wing hyperchaotic system of memristor, it is characterized in that: the adaptive synchronicity of a kind of four wing hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises four wing chaos system I circuit and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, four wing chaos system II circuit and memristor II circuit, and driving system circuit drives responding system circuit by signal;

Four wing chaos system I circuit are by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase output of the anti-phase adder input termination first via of the first via, the input of multiplier (A11) connects the anti-phase output on the second tunnel and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder of the output termination first via of multiplier (A11), the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the homophase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the in-phase input end on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3), the input of multiplier (A12) connects the in-phase input end of the first via and the integration output of memristor I respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A12),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, second road homophase of input termination four wing chaos system I circuit exports, and output connects the input of the second anti-phase adder in tunnel of four wing chaos system I circuit by 2 multipliers;

Four wing chaos system II circuit are by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase output of the anti-phase adder input termination first via of the first via, the input of multiplier (A1) connects the anti-phase output on the second tunnel and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder of the output termination first via of multiplier (A1), the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A5) connects the homophase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A5), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A6) connects the in-phase input end of the first via and the in-phase input end on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A6), the input of multiplier (A4) connects the in-phase input end of the first via and the integration output of memristor II respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A4),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination four wing chaos system II circuit exports, and output connects the input of the anti-phase adder of the first via of four wing chaos system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end of four wing chaos system I circuit first via and the reversed-phase output on four wing chaos system II circuit second tunnels, and multiplier (A9) exports the anti-phase adder input connecing four wing chaos system II circuit first via;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on four wing chaos system I circuit the 3rd tunnels and the reversed-phase output on four wing chaos system II circuit the 3rd tunnels, and multiplier (A10) exports the anti-phase adder input connecing four wing chaos system II circuit the 3rd tunnels.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1., based on an adaptive synchronicity method for four wing hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) three-dimensional chaotic system i is:

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on second equation of three-dimensional chaotic system i, and on the 3rd equation of system i increase a nonlinear terms xz, obtain a kind of four wing hyperchaotic system iv with memristor:

In formula, x, y, z, u are state variable, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(5) with described in iv based on four wing hyperchaotic system of memristor for drive system v:

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(6) with described in iv based on four wing hyperchaotic system of memristor for responding system vi:

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=0.35, b=-10, c=-0.6, d=0.3, e=-1.6, f=2, g=-0.1, k=0.2, m=0.1, n=0.01;

(7) error system e is defined ₁=(x ₂-x ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

。

2. the adaptive synchronicity circuit based on four wing hyperchaotic system of memristor, it is characterized in that: the adaptive synchronicity of a kind of four wing hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises four wing chaos system I circuit and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, four wing chaos system II circuit and memristor II circuit, and driving system circuit drives responding system circuit by signal;

Four wing chaos system I circuit are by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase output of the anti-phase adder input termination first via of the first via, the input of multiplier (A11) connects the anti-phase output on the second tunnel and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder of the output termination first via of multiplier (A11), the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the homophase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the in-phase input end on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3), the input of multiplier (A12) connects the in-phase input end of the first via and the integration output of memristor I respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A12),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, second road homophase of input termination four wing chaos system I circuit exports, and output connects the input of the second anti-phase adder in tunnel of four wing chaos system I circuit by 2 multipliers;

Four wing chaos system II circuit are by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase output of the anti-phase adder input termination first via of the first via, the input of multiplier (A1) connects the anti-phase output on the second tunnel and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder of the output termination first via of multiplier (A1), the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A5) connects the homophase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A5), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A6) connects the in-phase input end of the first via and the in-phase input end on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A6), the input of multiplier (A4) connects the in-phase input end of the first via and the integration output of memristor II respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A4),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination four wing chaos system II circuit exports, and output connects the input of the anti-phase adder of the first via of four wing chaos system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end of four wing chaos system I circuit first via and the reversed-phase output on four wing chaos system II circuit second tunnels, and multiplier (A9) exports the anti-phase adder input connecing four wing chaos system II circuit first via;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on four wing chaos system I circuit the 3rd tunnels and the reversed-phase output on four wing chaos system II circuit the 3rd tunnels, and multiplier (A10) exports the anti-phase adder input connecing four wing chaos system II circuit the 3rd tunnels.