CN105187193A - Self-adaptive synchronization method of memristor-based Lu hyperchaotic system with y square and circuit - Google Patents

Abstract

The invention relates to a chaotic system synchronization method and circuit, and particularly relates to a self-adaptive synchronization method of a memristor-based Lu hyperchaotic system with y square and a circuit. The self-adaptive synchronization circuit of the memristor-based Lu hyperchaotic system is composed of a drive system and a response system. The drive system comprises a I circuit of the Lu system with y square and a memristor I circuit. The response system comprises a controller 1 circuit, a controller 2 circuit, a II circuit of the Lu system with y square and a memristor II circuit. The drive system circuit drives the response system circuit through a signal. According to the invention, the memristor is used to propose the Lu hyperchaotic system with y square, and the self-adaptive synchronization method of the chaotic system is proposed on the basis.

Description

A kind of adaptive synchronicity method and circuit containing the Lu hyperchaotic system of y side based on memristor

Technical field

The present invention relates to a Synchronization of Chaotic Systems and circuit, particularly a kind of adaptive synchronicity method and circuit containing the Lu hyperchaotic system of y side based on memristor.

Background technology

Memristor was as the newfound physical component in HP Lab in 2008, the Cai Shi diode in cai's circuit can be replaced to form chaos system, also three-dimensional chaotic system can be increased to as Lorenz system as element, in Chen system and Lu system, form hyperchaotic system, at present, memristor as element formed chaos or hyperchaos Method and circuits oneself be suggested, but the synchronous method utilizing memristor to form hyperchaotic system as an element does not still propose, this is the deficiencies in the prior art parts, the present invention utilizes memristor to propose a kind of Lu hyperchaotic system, and propose the adaptive synchronicity method of this chaos system on this basis.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of the adaptive synchronicity method and the circuit that contain the Lu hyperchaotic system of y side based on memristor, and the present invention adopts following technological means to realize goal of the invention:

1., based on the adaptive synchronicity method of memristor containing the Lu hyperchaotic system of y side, it is characterized in that, comprise the following steps:

(1) the three-dimensional Lu chaos system i containing y side is:

$\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=-cy+xz\\ dz/dt=y^2-bz\end{array}\right.,a=36,b=3,c=20---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of the three-dimensional Lu chaos system i containing y side, obtain and a kind of there is the Lu hyperchaotic system iv of memristor containing y side:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kxW\left(u\right)\\ dy/dt=-cy+xz\\ dz/dt=y^2-bz\\ du/dt=-x\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(5) to contain the Lu hyperchaotic system of y side for drive system v based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={y_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(6) to contain the Lu hyperchaotic system of y side for responding system vi based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt={y_2}^2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-x_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={y_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt={y_2}^2-{\mathrm{bz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-x_2\end{array}\right.---ix$

2. one kind contains the adaptive synchronicity circuit of the Lu hyperchaotic system of y side based on memristor, it is characterized in that: the adaptive synchronicity of a kind of Lu hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Lu system I circuit containing y side and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, containing the Lu system II circuit of y side and memristor II circuit, driving system circuit drives responding system circuit by signal;

Containing the Lu system I circuit of y side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end on the second tunnel and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system I circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system I circuit by 2 multipliers;

Containing the Lu system II circuit of y side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end on the second tunnel and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system II circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit second tunnel and the reversed-phase output on Lu system II circuit second tunnel, and multiplier (A9) exports the anti-phase adder input connecing Lu system II circuit second tunnel;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit the 3rd tunnel and the reversed-phase output on Lu system II circuit the 3rd tunnel, and multiplier (A10) exports the anti-phase adder input connecing Lu system II circuit the 3rd tunnel.

Beneficial effect: the present invention is on the basis of three-dimensional chaotic system, and the present invention utilizes memristor to propose a kind of Lu hyperchaotic system containing y side, and proposes the adaptive synchronicity method of this chaos system on this basis.

Accompanying drawing explanation

Fig. 1 is the electrical block diagram of the preferred embodiment of the present invention.

Fig. 2 is Lu system I circuit diagram in the present invention.

Fig. 3 is the circuit diagram containing the memristor I of y side in the present invention.

Fig. 4 is Lu system II circuit diagram in the present invention.

Fig. 5 is the circuit diagram containing the memristor II of y side in the present invention.

Fig. 6 is the circuit diagram of middle controller 1 of the present invention.

Fig. 7 is the circuit diagram of middle controller 2 of the present invention.

Fig. 8 is the synchronous circuit design sketch of x1 and x2 in the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 8.

1., based on the adaptive synchronicity method of memristor containing the Lu hyperchaotic system of y side, it is characterized in that, comprise the following steps:

(1) three-dimensional Lu chaos system i is:

$\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=-cy+xz\\ dz/dt=y^2-bz\end{array}\right.,a=36,b=3,c=20---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of three-dimensional Lu chaos system i, obtain a kind of Lu hyperchaotic system iv with memristor:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kxW\left(u\right)\\ dy/dt=-cy+xz\\ dz/dt=y^2-bz\\ du/dt=-x\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(5) with described in iv based on the Lu hyperchaotic system of memristor for drive system v:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={y_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(6) with described in iv based on the Lu hyperchaotic system of memristor for responding system vi:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt={y_2}^2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-x_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={y_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt={y_2}^2-{\mathrm{bz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-x_2\end{array}\right.---ix$

2. one kind contains the adaptive synchronicity circuit of the Lu hyperchaotic system of y side based on memristor, it is characterized in that: the adaptive synchronicity of a kind of Lu hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Lu system I circuit containing y side and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, containing the Lu system II circuit of y side and memristor II circuit, driving system circuit drives responding system circuit by signal;

Containing the Lu system I circuit of y side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end on the second tunnel and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system I circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system I circuit by 2 multipliers;

Containing the Lu system II circuit of y side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end on the second tunnel and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system II circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit second tunnel and the reversed-phase output on Lu system II circuit second tunnel, and multiplier (A9) exports the anti-phase adder input connecing Lu system II circuit second tunnel;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit the 3rd tunnel and the reversed-phase output on Lu system II circuit the 3rd tunnel, and multiplier (A10) exports the anti-phase adder input connecing Lu system II circuit the 3rd tunnel.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1., based on the adaptive synchronicity method of memristor containing the Lu hyperchaotic system of y side, it is characterized in that, comprise the following steps:

(1) the three-dimensional Lu chaos system i containing y side is:

$\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=-cy+xz\\ dz/dt=y^2-bz\end{array}\right.,a=36,b=3,c=20---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of the three-dimensional Lu chaos system i containing y side, obtain and a kind of there is the Lu hyperchaotic system iv of memristor containing y side:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kxW\left(u\right)\\ dy/dt=-cy+xz\\ dz/dt=y^2-bz\\ du/dt=-x\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(5) to contain the Lu hyperchaotic system of y side for drive system v based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={y_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(6) to contain the Lu hyperchaotic system of y side for responding system vi based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt={y_2}^2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-x_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={y_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt={y_2}^2-{\mathrm{bz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-x_2\end{array}\right.---ix$

2. one kind contains the adaptive synchronicity circuit of the Lu hyperchaotic system of y side based on memristor, it is characterized in that: the adaptive synchronicity of a kind of Lu hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Lu system I circuit containing y side and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, containing the Lu system II circuit of y side and memristor II circuit, driving system circuit drives responding system circuit by signal;

Containing the Lu system I circuit of y side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end on the second tunnel and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system I circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system I circuit by 2 multipliers;

Containing the Lu system II circuit of y side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end on the second tunnel and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system II circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit second tunnel and the reversed-phase output on Lu system II circuit second tunnel, and multiplier (A9) exports the anti-phase adder input connecing Lu system II circuit second tunnel;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit the 3rd tunnel and the reversed-phase output on Lu system II circuit the 3rd tunnel, and multiplier (A10) exports the anti-phase adder input connecing Lu system II circuit the 3rd tunnel.