CN105262577A - Adaptive synchronization method and circuit of memristor-based x-power-including Chen hyper-chaotic system - Google Patents

Abstract

The invention relates to a chaotic system synchronization method and circuit, in particular to an adaptive synchronization method and circuit of a memristor-based x-power-including Chen hyper-chaotic system. As a physical element being newly discovered by the HP Labs in 2008, a memristor can construct a chaotic system instead of a Chua's diode in a Chua's circuit, and can be added into a three-dimensional chaotic system such as a Lorenz system, a Chen system and a Lorenz system as an element, thereby forming a hyper-chaotic system. At present, a method and a circuit for forming chaos or hyper-chaos by taking the memristor as an element are already put forward. However, a synchronization method for forming the hyper-chaos system by taking the memristor as an element is not put forward yet, which is a defect in the prior art. The invention provides the x-power-including Chen hyper-chaotic system by using the memristor, and provides the adaptive synchronization method of the chaotic system on the basis.

Description

A kind of adaptive synchronicity method and circuit containing the Chen hyperchaotic system of x side based on memristor

Technical field

The present invention relates to a Synchronization of Chaotic Systems and circuit, particularly a kind of adaptive synchronicity method and circuit containing the Chen hyperchaotic system of x side based on memristor.

Background technology

Memristor was as the newfound physical component in HP Lab in 2008, the Cai Shi diode in cai's circuit can be replaced to form chaos system, also three-dimensional chaotic system can be increased to as Lorenz system as element, in Chen system and Lu system, form hyperchaotic system, at present, memristor as element formed chaos or hyperchaos Method and circuits oneself be suggested, but the synchronous method utilizing memristor to form hyperchaotic system as an element does not still propose, this is the deficiencies in the prior art parts, the present invention utilizes memristor to propose a kind of Chen hyperchaotic system containing x side, and propose the adaptive synchronicity method of this chaos system on this basis.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of the adaptive synchronicity method and the circuit that contain the Chen hyperchaotic system of x side based on memristor, and the present invention adopts following technological means to realize goal of the invention:

1., based on the adaptive synchronicity method of memristor containing the Chen hyperchaotic system of x side, it is characterized in that, comprise the following steps:

(1) three-dimensional Chen chaos system i is:

$\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=(c-a)x-cy+xz\\ dz/dt=x^2-bz\end{array}\right.,a=35,b=3,c=28---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of three-dimensional Chen chaos system i, obtain and a kind ofly there is memristor containing the Chen hyperchaotic system iv of x side:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kyW\left(u\right)\\ dy/dt=(c-a)x-cy+xz\\ dz/dt=x^2-bz\\ du/dt=-y\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(5) to contain the Chen hyperchaotic system of x side for drive system v based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=(c-a)x_1-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={x_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-y_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(6) to contain the Chen hyperchaotic system of x side for responding system vi based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{ky}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=(c-a)x_2-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt={x_2}^2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-y_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=(c-a)x_1-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={x_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-y_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{ky}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=(c-a)x_2-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt={x_2}^2-{\mathrm{cz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-y_2\end{array}\right.---ix$

2. one kind contains the adaptive synchronicity circuit of the Chen hyperchaotic system of x side based on memristor, it is characterized in that: the adaptive synchronicity of a kind of Chen hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Chen system I circuit containing x side and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, containing the Chen system II circuit of x side and memristor II circuit, driving system circuit drives responding system circuit by signal;

Containing the Chen system I circuit of x side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output of the first via, connect the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the inverting input of the first via respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, second road homophase of input termination Chen system I circuit exports, and output connects the input of the anti-phase adder of the first via of Chen system I circuit by 2 multipliers;

Containing the Chen system II circuit of x side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output of the first via, connect the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end of the first via and the inverting input of the first via respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, input termination exports containing the first via homophase of the Chen system II circuit of x side, and output connects the input of the anti-phase adder of the first via of Chen system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, the reversed-phase output on the in-phase output end that the input of anti-phase adder connects containing the Chen system I circuit first via of x side and Chen system II circuit second tunnel, multiplier (A9) exports the anti-phase adder input of the Chen system II circuit first via connect containing x side;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, the reversed-phase output on the in-phase output end that the input of anti-phase adder connects containing Chen system I circuit the 3rd tunnel of x side and Chen system II circuit the 3rd tunnel, multiplier (A10) exports the anti-phase adder input on Chen system II circuit the 3rd tunnel connect containing x side.

Beneficial effect: the present invention is on the basis of three-dimensional chaotic system, and the present invention utilizes memristor to propose a kind of Chen hyperchaotic system containing x side, and proposes the adaptive synchronicity method of this chaos system on this basis.

Accompanying drawing explanation

Fig. 1 is the electrical block diagram of the preferred embodiment of the present invention.

Fig. 2 is the Chen system I circuit diagram containing x side in the present invention.

Fig. 3 is the circuit diagram of memristor I in the present invention.

Fig. 4 is the Chen system II circuit diagram containing x side in the present invention.

Fig. 5 is the circuit diagram of memristor II in the present invention.

Fig. 6 is the circuit diagram of middle controller 1 of the present invention.

Fig. 7 is the circuit diagram of middle controller 2 of the present invention.

Fig. 8 is the synchronous circuit design sketch of x1 and x2 in the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 8

1., based on the adaptive synchronicity method of memristor containing the Chen hyperchaotic system of x side, it is characterized in that, comprise the following steps:

(1) three-dimensional Chen chaos system i is:

$\left\{\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=(c-a)x-cy+xz\\ dz/dt=x^2-bz\end{array}\right.,a=35,b=3,c=28---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of three-dimensional Chen chaos system i, obtain and a kind ofly there is memristor containing the Chen hyperchaotic system iv of x side:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kyW\left(u\right)\\ dy/dt=(c-a)x-cy+xz\\ dz/dt=x^2-bz\\ du/dt=-y\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(5) to contain the Chen hyperchaotic system of x side for drive system v based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=(c-a)x_1-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={x_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-y_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(6) to contain the Chen hyperchaotic system of x side for responding system vi based on memristor described in iv:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{ky}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=(c-a)x_2-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt={x_2}^2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-y_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{ky}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=(c-a)x_1-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt={x_1}^2-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-y_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{ky}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=(c-a)x_2-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt={x_2}^2-{\mathrm{cz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-y_2\end{array}\right.---ix$

2. one kind contains the adaptive synchronicity circuit of the Chen hyperchaotic system of x side based on memristor, it is characterized in that: the adaptive synchronicity of a kind of Chen hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Chen system I circuit containing x side and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, containing the Chen system II circuit of x side and memristor II circuit, driving system circuit drives responding system circuit by signal;

Containing the Chen system I circuit of x side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output of the first via, connect the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the inverting input of the first via respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, second road homophase of input termination Chen system I circuit exports, and output connects the input of the anti-phase adder of the first via of Chen system I circuit by 2 multipliers;

Containing the Chen system II circuit of x side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output of the first via, connect the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end of the first via and the inverting input of the first via respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, input termination exports containing the first via homophase of the Chen system II circuit of x side, and output connects the input of the anti-phase adder of the first via of Chen system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, the reversed-phase output on the in-phase output end that the input of anti-phase adder connects containing the Chen system I circuit first via of x side and Chen system II circuit second tunnel, multiplier (A9) exports the anti-phase adder input of the Chen system II circuit first via connect containing x side;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, the reversed-phase output on the in-phase output end that the input of anti-phase adder connects containing Chen system I circuit the 3rd tunnel of x side and Chen system II circuit the 3rd tunnel, multiplier (A10) exports the anti-phase adder input on Chen system II circuit the 3rd tunnel connect containing x side.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1., based on the adaptive synchronicity method of memristor containing the Chen hyperchaotic system of x side, it is characterized in that, comprise the following steps:

(1) three-dimensional Chen chaos system i is:

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of three-dimensional Chen chaos system i, obtain and a kind ofly there is memristor containing the Chen hyperchaotic system iv of x side:

In formula, x, y, z, u are state variable, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(5) to contain the Chen hyperchaotic system of x side for drive system v based on memristor described in iv:

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(6) to contain the Chen hyperchaotic system of x side for responding system vi based on memristor described in iv:

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=35, b=3, c=28, k=1, m=8, n=0.006;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

。

2. one kind contains the adaptive synchronicity circuit of the Chen hyperchaotic system of x side based on memristor, it is characterized in that: the adaptive synchronicity of a kind of Chen hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Chen system I circuit containing x side and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, containing the Chen system II circuit of x side and memristor II circuit, driving system circuit drives responding system circuit by signal;

Containing the Chen system I circuit of x side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output of the first via, connect the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the inverting input of the first via respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, second road homophase of input termination Chen system I circuit exports, and output connects the input of the anti-phase adder of the first via of Chen system I circuit by 2 multipliers;

Containing the Chen system II circuit of x side by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output of the first via, connect the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end of the first via and the inverting input of the first via respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, input termination exports containing the first via homophase of the Chen system II circuit of x side, and output connects the input of the anti-phase adder of the first via of Chen system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, the reversed-phase output on the in-phase output end that the input of anti-phase adder connects containing the Chen system I circuit first via of x side and Chen system II circuit second tunnel, multiplier (A9) exports the anti-phase adder input of the Chen system II circuit first via connect containing x side;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, the reversed-phase output on the in-phase output end that the input of anti-phase adder connects containing Chen system I circuit the 3rd tunnel of x side and Chen system II circuit the 3rd tunnel, multiplier (A10) exports the anti-phase adder input on Chen system II circuit the 3rd tunnel connect containing x side.