CN105207770A - Self-adaptive synchronization method and circuit of Lu hyperchaotic system based on memristor - Google Patents

Abstract

The invention relates to a chaotic system synchronization method and circuit, in particular to a self-adaptive synchronization method and circuit of a Lu hyperchaotic system based on a memristor. The memristor serves as a physical component which is discovered in the Hewlett-Packard laboratory in 2008 and can replace a Chua diode of a Chua circuit to form a chaotic system, and the memristor can also serve as a component to be added to three-dimensional chaotic systems such as a Lorenz system, a Chen system and a Lu system to form a hyperchaotic system. At present, the method and the circuit of taking the memristor as a component to form chaos or hyperchaos are put forward, however, the synchronization method of taking the memristor as a component to form the hyperchaotic system is not put forward, and the defect in the prior art is put forward. The Lu hyperchaotic system using the memristor is provided, and a self-adaptive synchronization method of the chaotic system is provided on the basis.

Description

A kind of adaptive synchronicity method of the Lu hyperchaotic system based on memristor and circuit

Technical field

The present invention relates to a Synchronization of Chaotic Systems and circuit, particularly a kind of adaptive synchronicity method of the Lu hyperchaotic system based on memristor and circuit.

Background technology

Memristor was as the newfound physical component in HP Lab in 2008, the Cai Shi diode in cai's circuit can be replaced to form chaos system, also three-dimensional chaotic system can be increased to as Lorenz system as element, in Chen system and Lu system, form hyperchaotic system, at present, memristor as element formed chaos or hyperchaos Method and circuits oneself be suggested, but the synchronous method utilizing memristor to form hyperchaotic system as an element does not still propose, this is the deficiencies in the prior art parts, the present invention utilizes memristor to propose a kind of Lu hyperchaotic system, and propose the adaptive synchronicity method of this chaos system on this basis.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of adaptive synchronicity method and circuit of the Lu hyperchaotic system based on memristor, and the present invention adopts following technological means to realize goal of the invention:

1., based on an adaptive synchronicity method for the Lu hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) three-dimensional Lu chaos system i is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=-cy+xz\\ dz/dt=xy-bz\end{array}& a=36,b=3,c=20\end{array}\right.---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of three-dimensional Lu chaos system i, obtain a kind of Lu hyperchaotic system iv with memristor:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kxW\left(u\right)\\ dy/dt=-cy+xz\\ dz/dt=xy-bz\\ du/dt=-x\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(5) with described in iv based on the Lu hyperchaotic system of memristor for drive system v:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt=x_1{y}_1-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(6) with described in iv based on the Lu hyperchaotic system of memristor for responding system vi:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt=x_2{y}_2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-x_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt=x_1{y}_1-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt=x_2{y}_2-{\mathrm{bz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-x_2\end{array}\right.---ix$

2. the adaptive synchronicity circuit based on the Lu hyperchaotic system of memristor, it is characterized in that: the adaptive synchronicity of a kind of Lu hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Lu system I circuit and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, Lu system II circuit and memristor II circuit, and driving system circuit drives responding system circuit by signal;

Lu system I circuit is by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system I circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system I circuit by 2 multipliers;

Lu system II circuit is by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end of the first via and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system II circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit second tunnel and the reversed-phase output on Lu system II circuit second tunnel, and multiplier (A9) exports the anti-phase adder input connecing Lu system II circuit second tunnel;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit the 3rd tunnel and the reversed-phase output on Lu system II circuit the 3rd tunnel, and multiplier (A10) exports the anti-phase adder input connecing Lu system II circuit the 3rd tunnel.

Beneficial effect: the present invention is on the basis of three-dimensional chaotic system, and the present invention utilizes memristor to propose a kind of Lu hyperchaotic system, and proposes the adaptive synchronicity method of this chaos system on this basis.

Accompanying drawing explanation

Fig. 1 is the electrical block diagram of the preferred embodiment of the present invention.

Fig. 2 is Lu system I circuit diagram in the present invention.

Fig. 3 is the circuit diagram of memristor I in the present invention.

Fig. 4 is Lu system II circuit diagram in the present invention.

Fig. 5 is the circuit diagram of memristor II in the present invention.

Fig. 6 is the circuit diagram of middle controller 1 of the present invention.

Fig. 7 is the circuit diagram of middle controller 2 of the present invention.

Fig. 8 is the synchronous circuit design sketch of x1 and x2 in the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 8.

1., based on an adaptive synchronicity method for the Lu hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) three-dimensional Lu chaos system i is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=-cy+xz\\ dz/dt=xy-bz\end{array}& a=36,b=3,c=20\end{array}\right.---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of three-dimensional Lu chaos system i, obtain a kind of Lu hyperchaotic system iv with memristor:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kxW\left(u\right)\\ dy/dt=-cy+xz\\ dz/dt=xy-bz\\ du/dt=-x\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(5) with described in iv based on the Lu hyperchaotic system of memristor for drive system v:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt=x_1{y}_1-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(6) with described in iv based on the Lu hyperchaotic system of memristor for responding system vi:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt=x_2{y}_2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-x_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt=x_1{y}_1-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt=x_2{y}_2-{\mathrm{bz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-x_2\end{array}\right.---ix$

2. the adaptive synchronicity circuit based on the Lu hyperchaotic system of memristor, it is characterized in that: the adaptive synchronicity of a kind of Lu hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Lu system I circuit and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, Lu system II circuit and memristor II circuit, and driving system circuit drives responding system circuit by signal;

Lu system I circuit is by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system I circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system I circuit by 2 multipliers;

Lu system II circuit is by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end of the first via and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system II circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit second tunnel and the reversed-phase output on Lu system II circuit second tunnel, and multiplier (A9) exports the anti-phase adder input connecing Lu system II circuit second tunnel;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit the 3rd tunnel and the reversed-phase output on Lu system II circuit the 3rd tunnel, and multiplier (A10) exports the anti-phase adder input connecing Lu system II circuit the 3rd tunnel.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1., based on an adaptive synchronicity method for the Lu hyperchaotic system of memristor, it is characterized in that, comprise the following steps:

(1) three-dimensional Lu chaos system i is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=a(y-x)\\ dy/dt=-cy+xz\\ dz/dt=xy-bz\end{array}& a=36,b=3,c=20\end{array}\right.---i$

In formula, x, y, z are state variable;

(2) the memristor model that the present invention adopts is ii:

Wherein represent that magnetic control recalls resistance, represent magnetic flux, m, n be greater than zero parameter;

(3) obtaining iii to the memristor differentiate of ii is:

represent and recall and lead, m, n be greater than zero parameter;

(4) using memristor model iii as unidimensional system variable, be added on first equation of three-dimensional Lu chaos system i, obtain a kind of Lu hyperchaotic system iv with memristor:

$\left\{\begin{array}{c}dx/dt=a(y-x)-kxW\left(u\right)\\ dy/dt=-cy+xz\\ dz/dt=xy-bz\\ du/dt=-x\end{array}\right.---iv$

In formula, x, y, z, u are state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(5) with described in iv based on the Lu hyperchaotic system of memristor for drive system v:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt=x_1{y}_1-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\end{array}\right.---v$

X in formula ₁, y ₁, z ₁, u ₁for state variable, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(6) with described in iv based on the Lu hyperchaotic system of memristor for responding system vi:

$\left\{\begin{array}{c}{\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)+v_1\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2+v_2\\ {\mathrm{dz}}_2/dt=x_2{y}_2-{\mathrm{bz}}_2+v_3\\ {\mathrm{du}}_2/dt=-x_2+v_4\end{array}\right.---vi$

X in formula ₂, y ₂, z ₂, u ₂for state variable, v ₁, v ₂, v ₃, v ₄for controller, parameter value a=36, b=20, c=3, k=2, m=10, n=0.008;

(7) error system e is defined ₁=(y ₂-y ₁), e ₂=(z ₂-z ₁), when controller get be worth as follows time, drive chaos system v and response chaos system vi to realize synchronous;

$\left\{\begin{array}{c}{v}_1=0\\ v_2=-e_1\∫e_1^{2}dt\\ v_3=-e_2\∫e_2^{2}dt\\ v_4=0\end{array}\right.---vii$

By the Chaotic Synchronous circuit driving chaos system v and response chaos system vi to form be:

$\left\{\begin{array}{c}{\mathrm{dx}}_1/dt=a(y_1-x_1)-{\mathrm{kx}}_{1}W\left(u_1\right)\\ {\mathrm{dy}}_1/dt=-{\mathrm{cy}}_1+x_1{z}_1\\ {\mathrm{dz}}_1/dt=x_1{y}_1-{\mathrm{bz}}_1\\ {\mathrm{du}}_1/dt=-x_1\\ {\mathrm{dx}}_2/dt=a(y_2-x_2)-{\mathrm{kx}}_{2}W\left(u_2\right)\\ {\mathrm{dy}}_2/dt=-{\mathrm{cy}}_2+x_2{z}_2-(y_2-y_1)\∫{(y_2-y_1)}^{2}dt\\ {\mathrm{dz}}_2/dt=x_2{y}_2-{\mathrm{bz}}_2-(z_2-z_1)\∫{(z_2-z_1)}^{2}dt\\ {\mathrm{du}}_2/dt=-x_2\end{array}\right.---ix$

2. the adaptive synchronicity circuit based on the Lu hyperchaotic system of memristor, it is characterized in that: the adaptive synchronicity of a kind of Lu hyperchaotic system based on memristor of described circuit is made up of drive system and responding system, drive system comprises Lu system I circuit and memristor I circuit, responding system comprises controller 1 circuit, controller electricity 2 tunnels, Lu system II circuit and memristor II circuit, and driving system circuit drives responding system circuit by signal;

Lu system I circuit is by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A2) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A2), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A3) connects the in-phase input end of the first via and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A3),

Memristor I circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system I circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system I circuit by 2 multipliers;

Lu system II circuit is by integrated operational amplifier (LF347N) and resistance, the three anti-phase adders in tunnel that electric capacity is formed, inverting integrator and inverter and multiplier composition, the anti-phase anti-phase output of the adder input termination first via of the first via and the homophase on the second tunnel export, the anti-phase adder input on the second tunnel connects the reversed-phase output on the second tunnel, the input of multiplier (A4) connects the anti-phase output of the first via and the homophase output on the 3rd tunnel respectively, the input of the anti-phase adder in output termination second tunnel of multiplier (A4), the anti-phase input on the 3rd tunnel connects the in-phase output end on the 3rd tunnel, the input of multiplier (A5) connects the in-phase input end of the first via and the inverting input on the second tunnel respectively, the anti-phase adder input on output termination the 3rd tunnel of multiplier (A5),

Memristor II circuit is made up of integrated operational amplifier (LF353N) and 2 multipliers (AD633JN), integrated operational amplifier (LF353N) and resistance, electric capacity form inverting integrator, the first via homophase of input termination Lu system II circuit exports, and output connects the input of the anti-phase adder of the first via of Lu system II circuit by 2 multipliers;

Controller 1 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit second tunnel and the reversed-phase output on Lu system II circuit second tunnel, and multiplier (A9) exports the anti-phase adder input connecing Lu system II circuit second tunnel;

Controller 2 circuit is made up of anti-phase adder, multiplier, inverter and inverting integrator, anti-phase adder input connects the in-phase output end on Lu system I circuit the 3rd tunnel and the reversed-phase output on Lu system II circuit the 3rd tunnel, and multiplier (A10) exports the anti-phase adder input connecing Lu system II circuit the 3rd tunnel.