CN105681019A - Construction method of Chen type hyper-chaotic system with x power based on memristor - Google Patents

Abstract

The invention relates to a construction method and circuit of a Chen type hyper-chaotic system with x power based on a memristor. Additive operation, inversion operation and integral operation are achieved through an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a resistor and a capacitor, multiplication in the system is achieved through a multiplying unit U4 and a multiplying unit U5, a memristor model in the system is achieved through an operational amplifier U6, a multiplying unit U7 and a multiplying unit U8, the operational amplifier U1 is connected with the operational amplifier U2, the operational amplifier U6, the multiplying unit U4, the multiplying unit U5 and the multiplying unit U8, the operational amplifier U2 is connected with the operational amplifier U3 and the multiplying unit U4, the operational amplifier U3 is connected with the multiplying unit U5, the operational amplifier U6 is connected with the multiplying unit U7 and the multiplying unit U8, and the multiplying unit U7 is connected with the multiplying unit U8. On the basis of the Chen type chaotic system with the x power, one dimension is added through one memristor element to form the four-dimension hyper-chaotic system, and a new method for applying the memristor to the hyper-chaotic system is provided.

Description

Based on the construction process of the Chen type hyperchaotic system containing x side of memristor

Technical field

The present invention relates to a kind of chaos system and circuit realiration, in particular to construction process and the circuit of a kind of Chen type hyperchaotic system containing x side based on memristor.

Background technology

Currently, the method constructing four dimension ultra-chaos is mainly on the basis of three-dimensional chaotic system, increase by a dimension and form four-dimensional hyperchaotic system, memristor is as the physical component of HP Lab new discovery in 2008, the Cai Shi diode in cai's circuit can be replaced to form four dimensional chaos system, to be formed super chaos in cai's circuit then needs 2 to recall resistance element, it is thus desirable to five dimensions or five tie up above system, having, the circuit system realizing super chaos in the four-dimensional system recalling resistance element is also fewer, the method that memristor is applied to four-dimensional hyperchaotic system is not also suggested, this is the deficiencies in the prior art parts.

Summary of the invention

The technical problem to be solved in the present invention is to provide construction process and the circuit of a kind of Chen type hyperchaotic system containing x side based on memristor:

1. based on the construction process of Chen type hyperchaotic system containing x side of memristor, it is characterised in that, comprise the following steps:

(1) Chen type chaos system i containing x side is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=(c-a)x+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{bz}\end{array}\right.,a=35,b=3,c=28---i$

In formula, x, y, z are state variables;

(2) to be magnetic control memristor model ii be described memristor:

WhereinRepresent that resistance is recalled in magnetic control,Represent magnetic flux;

(3) the magnetic control memristor model of ii asked lead to recall and lead device model iii and be:

Represent that magnetic control is recalled to lead;

(4) magnetic control recalled lead device model iii as a dimension system variable, be added in containing on the first equation of the Chen type chaos system of x side, obtain a kind of Chen type hyperchaotic system iv containing x side based on memristor:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)+\mathrm{kyW}\left(u\right)\\ \mathrm{dy}/\mathrm{dt}=(c-a)x+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{bz}\\ \mathrm{du}/\mathrm{dt}=y\end{array}\right.---\mathrm{iv}$

In formula, x, y, z, u are state variables, parameter value a=35, b=3, c=28, m=8, n=0.006, k=1;

(5) based on the circuit of system iv structure, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity is utilized to realize addition, anti-phase and integral operation, utilize the multiplying that multiplier U4 and multiplier U5 realizes in system, operational amplifier U6 and multiplier U7, multiplier U8 and electric capacity is utilized to realize described memristor model, described operational amplifier U1, U2 and U3 adopt LF347BN, described multiplier U4, U5, U7 and U8 adopt AD633JN, and described operational amplifier U6 adopts LF353N;

1st pin of described operational amplifier U1 connects the 2nd pin by electric capacity Cx, the 6th pin is connected by resistance R2, 1st pin directly connects the 1st pin and the 3rd pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, 2nd pin, 6th pin, 7th pin is unsettled, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 13rd pin of operational amplifier U1 is connect by resistance Rx3, the 6th pin of operational amplifier U6 is connect by resistance R8, by the 7th pin of the series connection multiplier U8 of resistance R10 and resistance R9, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 1st pin of multiplier U8, 13rd pin connects the 14th pin by resistance Ry, 14th pin connects the 9th pin by resistance R4,

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

1st pin of described multiplier U4 connects the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 3rd pin connects the 1st pin of operational amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of described multiplier U5 and the 3rd pin connect the 1st pin of operational amplifier U1, and the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1.

2. magnetic control memristor described in is realized by operational amplifier U6 and multiplier U7 and multiplier U8, and described operational amplifier U6 connects operational amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 and connects multiplier U8, multiplier U8 connection operational amplifier U2;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 13rd pin of operational amplifier U1 is connected by resistance R8 and resistance Rx3, connected the 13rd pin of operational amplifier U1 by resistance R8 and resistance Rx2, the 7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 3rd pin connect the 7th pin of operational amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin directly connects the 8th pin of operational amplifier U2,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC.

3. based on the Chen type hyperchaotic system circuit containing x side of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, operational amplifier U6 and multiplier U7 and multiplier U8 is utilized to realize described memristor model, operational amplifier U1 connects operational amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 connects multiplier U4, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N,

1st pin of described operational amplifier U1 connects the 2nd pin by electric capacity Cx, the 6th pin is connected by resistance R2, 1st pin directly connects the 1st pin and the 3rd pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, 2nd pin, 6th pin, 7th pin is unsettled, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 13rd pin of operational amplifier U1 is connect by resistance Rx3, the 6th pin of operational amplifier U6 is connect by resistance R8, by the 7th pin of the series connection multiplier U8 of resistance R10 and resistance R9, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 1st pin of multiplier U8, 13rd pin connects the 14th pin by resistance Ry, 14th pin connects the 9th pin by resistance R4,

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

1st pin of described multiplier U4 connects the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 3rd pin connects the 1st pin of operational amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of described multiplier U5 and the 3rd pin connect the 1st pin of operational amplifier U1, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 13rd pin of operational amplifier U1 is connected by resistance R8 and resistance Rx3, connected the 13rd pin of operational amplifier U1 by resistance R8 and resistance Rx2, the 7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 3rd pin connect the 7th pin of operational amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin directly connects the 8th pin of operational amplifier U2,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC.

Useful effect: the present invention is containing, on the basis of the Chen type chaos system of x side, utilizing one to recall resistance element increases by a four-dimensional hyperchaotic system of dimension formation, it is proposed that memristor is applied to the novel method of hyperchaotic system.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 realizes in the present invention recalling the actual interface chart of the circuit leading device.

Fig. 3 is the actual interface chart of circuit of operational amplifier U1.

Fig. 4 is the actual interface chart of circuit of multiplier U4 and operational amplifier U2.

Fig. 5 is the actual interface chart of circuit of multiplier U5 and operational amplifier U3.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 5.

1. based on the construction process of Chen type hyperchaotic system containing x side of memristor, it is characterised in that, comprise the following steps:

(1) Chen type chaos system i containing x side is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=(c-a)x+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{bz}\end{array}\right.,a=35,b=3,c=28---i$

In formula, x, y, z are state variables;

(2) to be magnetic control memristor model ii be described memristor:

WhereinRepresent that resistance is recalled in magnetic control,Represent magnetic flux;

(3) the magnetic control memristor model of ii asked lead to recall and lead device model iii and be:

Represent that magnetic control is recalled to lead;

(4) magnetic control recalled lead device model iii as a dimension system variable, be added in containing on the first equation of the Chen type chaos system of x side, obtain a kind of Chen type hyperchaotic system iv containing x side based on memristor:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)+\mathrm{kyW}\left(u\right)\\ \mathrm{dy}/\mathrm{dt}=(c-a)x+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{bz}\\ \mathrm{du}/\mathrm{dt}=y\end{array}\right.---\mathrm{iv}$

In formula, x, y, z, u are state variables, parameter value a=35, b=3, c=28, m=8, n=0.006, k=1;

(5) based on the circuit of system iv structure, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity is utilized to realize addition, anti-phase and integral operation, utilize the multiplying that multiplier U4 and multiplier U5 realizes in system, operational amplifier U6 and multiplier U7, multiplier U8 and electric capacity is utilized to realize described memristor model, described operational amplifier U1, U2 and U3 adopt LF347BN, described multiplier U4, U5, U7 and U8 adopt AD633JN, and described operational amplifier U6 adopts LF353N;

1st pin of described operational amplifier U1 connects the 2nd pin by electric capacity Cx, the 6th pin is connected by resistance R2, 1st pin directly connects the 1st pin and the 3rd pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, 2nd pin, 6th pin, 7th pin is unsettled, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 13rd pin of operational amplifier U1 is connect by resistance Rx3, the 6th pin of operational amplifier U6 is connect by resistance R8, by the 7th pin of the series connection multiplier U8 of resistance R10 and resistance R9, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 1st pin of multiplier U8, 13rd pin connects the 14th pin by resistance Ry, 14th pin connects the 9th pin by resistance R4,

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

1st pin of described multiplier U4 connects the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 3rd pin connects the 1st pin of operational amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of described multiplier U5 and the 3rd pin connect the 1st pin of operational amplifier U1, and the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1.

2. magnetic control memristor described in is realized by operational amplifier U6 and multiplier U7 and multiplier U8, and described operational amplifier U6 connects operational amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 and connects multiplier U8, multiplier U8 connection operational amplifier U2;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 13rd pin of operational amplifier U1 is connected by resistance R8 and resistance Rx2, connected the 13rd pin of operational amplifier U1 by resistance R8 and resistance Rx3, the 7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 3rd pin connect the 7th pin of operational amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin directly connects the 8th pin of operational amplifier U2,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC.

3. based on the Chen type hyperchaotic system circuit containing x side of memristor, it is characterized in that, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity realizes addition, anti-phase and integral operation, utilize multiplier U4, the multiplying in system is realized with multiplier U5, operational amplifier U6 and multiplier U7 and multiplier U8 is utilized to realize described memristor model, operational amplifier U1 connects operational amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 connects multiplier U4, operational amplifier U3 connects multiplier U5, operational amplifier U6 connects multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, described operational amplifier U1, U2 and U3 adopts LF347BN, described multiplier U4, U5, U7 and U8 adopts AD633JN, described operational amplifier U6 adopts LF353N,

1st pin of described operational amplifier U1 connects the 2nd pin by electric capacity Cx, the 6th pin is connected by resistance R2, 1st pin directly connects the 1st pin and the 3rd pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, 2nd pin, 6th pin, 7th pin is unsettled, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 13rd pin of operational amplifier U1 is connect by resistance Rx3, the 6th pin of operational amplifier U6 is connect by resistance R8, by the 7th pin of the series connection multiplier U8 of resistance R10 and resistance R9, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 1st pin of multiplier U8, 13rd pin connects the 14th pin by resistance Ry, 14th pin connects the 9th pin by resistance R4,

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

1st pin of described multiplier U4 connects the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 3rd pin connects the 1st pin of operational amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of described multiplier U5 and the 3rd pin connect the 1st pin of operational amplifier U1, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 13rd pin of operational amplifier U1 is connected by resistance R8 and resistance Rx3, connected the 13rd pin of operational amplifier U1 by resistance R8 and resistance Rx2, the 7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 3rd pin connect the 7th pin of operational amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin directly connects the 8th pin of operational amplifier U2,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC.

Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and change, remodeling, interpolation or the replacement that those skilled in the art make in the essential scope of the present invention, also belongs to protection scope of the present invention.

Claims (2)

1. based on the construction process of Chen type hyperchaotic system containing x side of memristor, it is characterised in that, comprise the following steps:

(1) Chen type chaos system i containing x side is:

$\left\{\begin{array}{cc}\begin{array}{c}dx/dt=a\left(y-x\right)\\ dy/dt=\left(c-a\right)x+cy-xz\\ dz/dt=y^2-bz\end{array}& a=35,b=3,c=28\end{array}\right.---i$

In formula, x, y, z are state variables;

(2) to be magnetic control memristor model ii be described memristor:

WhereinRepresent that resistance is recalled in magnetic control,Represent magnetic flux;

(3) the magnetic control memristor model of ii asked lead to recall and lead device model iii and be:

Represent that magnetic control is recalled to lead;

(4) magnetic control recalled lead device model iii as a dimension system variable, be added in containing on the first equation of the Chen type chaos system of x side, obtain a kind of Chen type hyperchaotic system iv containing x side based on memristor:

$\left\{\begin{array}{c}dx/dt=a\left(y-x\right)+kyW\left(u\right)\\ dy/dt=\left(c-a\right)x+cy-xz\\ dz/dt=y^2-bz\\ du/dt=y\end{array}\right.---iv$

In formula, x, y, z, u are state variables, parameter value a=35, b=3, c=28, m=8, n=0.006, k=1;

(5) based on the circuit of system iv structure, operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, electric capacity is utilized to realize addition, anti-phase and integral operation, utilize the multiplying that multiplier U4 and multiplier U5 realizes in system, operational amplifier U6 and multiplier U7, multiplier U8 and electric capacity is utilized to realize described memristor model, described operational amplifier U1, U2 and U3 adopt LF347BN, described multiplier U4, U5, U7 and U8 adopt AD633JN, and described operational amplifier U6 adopts LF353N;

1st pin of described operational amplifier U1 connects the 2nd pin by electric capacity Cx, the 6th pin is connected by resistance R2, 1st pin directly connects the 1st pin and the 3rd pin of multiplier U5, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, 9th pin is unsettled, 6th pin connects the 7th pin by resistance R3, 7th pin connects the 13rd pin by resistance Rx1, the 13rd pin of operational amplifier U2 is connect by resistance Ry1, 7th pin directly connects the 1st pin of multiplier U4, 13rd pin connects the 14th pin by resistance Rx, 14th pin connects the 2nd pin by resistance R1,

1st pin of described operational amplifier U2, 2nd pin, 6th pin, 7th pin is unsettled, 3rd pin, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin connects the 13rd pin by resistance Ry2, the 13rd pin of operational amplifier U1 is connect by resistance Rx2, the 13rd pin of operational amplifier U1 is connect by resistance Rx3, the 6th pin of operational amplifier U6 is connect by resistance R8, by the 7th pin of the series connection multiplier U8 of resistance R10 and resistance R9, the 9th pin is connect by electric capacity Cy, 8th pin directly connects the 1st pin of multiplier U8, 13rd pin connects the 14th pin by resistance Ry, 14th pin connects the 9th pin by resistance R4,

1st pin of described operational amplifier U3 connects the 2nd pin by electric capacity Cz, the 6th pin is connect by resistance R6,1st pin directly connects the 3rd pin of multiplier U4,3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 8th pin, the 9th pin are unsettled, 6th pin connects the 7th pin by resistance R7,7th pin connects the 13rd pin by resistance Rz2,13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5;

1st pin of described multiplier U4 connects the 7th pin of operational amplifier U1,2nd pin, the 4th pin, the 6th pin ground connection, 3rd pin connects the 1st pin of operational amplifier U3,5th pin meets VEE, 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance Ry3;

1st pin of described multiplier U5 and the 3rd pin connect the 1st pin of operational amplifier U1, and the 2nd pin, the 4th pin, the 6th pin ground connection, the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd pin of operational amplifier U3 by resistance Rz1.

2. according to claim 1 based on the construction process of Chen type hyperchaotic system containing x side of memristor, described magnetic control memristor is realized by operational amplifier U6 and multiplier U7 and multiplier U8, described operational amplifier U6 connects operational amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 connects multiplier U8, multiplier U8 and connects operational amplifier U2;

1st pin of described operational amplifier U6, the 2nd pin, the 3rd pin are unsettled, 4th pin meets VEE, 5th pin ground connection, 6th pin connects the 7th pin by electric capacity C4, the 13rd pin of operational amplifier U1 is connected by resistance R8 and resistance Rx3, connected the 13rd pin of operational amplifier U1 by resistance R8 and resistance Rx2, the 7th pin directly connects the 1st pin and the 3rd pin of multiplier U7, and the 8th pin meets VCC;

1st pin of described multiplier U7 and the 3rd pin connect the 7th pin of operational amplifier U6, the 2nd pin, the 4th pin, the 6th pin ground connection, and the 5th pin meets VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC;

1st pin of described multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by series connection the 7th pin of resistance R10 and resistance R9,1st pin directly connects the 8th pin of operational amplifier U2,2nd pin, the 4th pin, the 6th pin ground connection, 5th pin meets VEE, 7th pin connects the 13rd pin of operational amplifier U1 by resistance R9, and the 8th pin meets VCC.