CN114301580B - Chaotic synchronization circuit based on Duffing-Van der pol memristor chaotic oscillator - Google Patents
Chaotic synchronization circuit based on Duffing-Van der pol memristor chaotic oscillator Download PDFInfo
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Abstract
The invention provides a chaotic synchronization circuit based on a Duffing-Van derpol memristor chaotic oscillator, which comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, an operational amplifier U7, an operational amplifier U8, an operational amplifier U9, an operational amplifier U10, an operational amplifier U11, an operational amplifier U12, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, a multiplier A5, a multiplier A6, a multiplier A7, a multiplier A8, peripheral resistors and two sinusoidal signal sources. The beneficial effects of the invention are as follows: the synchronization of the two chaotic systems is realized by coupling the two Duffing-Van der pol memristor chaotic oscillator circuits with the magnetic control memristor model.
Description
Technical Field
The invention relates to the field of chaotic circuits, in particular to a chaotic synchronization circuit based on a Duffing-Van der pol memristor chaotic oscillator.
Background
The memristor is a nonlinear circuit element, has natural nonlinearity and plasticity, synchronously designs a Duffing-Van der pol memristor chaotic oscillator circuit based on the memristor, and can construct a chaotic synchronization system based on the Duffing-Van der pol memristor chaotic oscillator by adopting a driving-response synchronization method. The chaotic synchronization circuit based on Duffing-Van der pol memristor chaotic oscillator is a control method for a chaotic system, and has unique dynamic behavior. Through the chaotic synchronization control method, the complete synchronization of output signals of two chaotic systems under different initial conditions can be realized, and the method has important roles in the fields of weak signal detection, secret communication, signal processing and the like based on the chaotic systems. At present, the chaotic synchronization control method based on the Duffing-Van der Pol memristor chaotic oscillator is few, the types of chaotic synchronization circuits based on the chaotic oscillator are limited, the synchronous circuits of the memristor chaotic system have great practical significance for enriching a chaotic synchronization circuit library, and the chaotic synchronization system can play an important role in the fields of secret communication, weak signal detection and the like.
Disclosure of Invention
In order to solve the above problems, the present invention provides a chaos synchronization circuit based on a Duffing-Van der pol memristor chaos oscillator, which includes an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, an operational amplifier U7, an operational amplifier U8, an operational amplifier U9, an operational amplifier U10, an operational amplifier U11, an operational amplifier U12, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, a multiplier A5, a multiplier A6, a multiplier A7, a multiplier A8, a peripheral resistor and two sinusoidal signal sources;
the inverting input end of the operational amplifier U1 is respectively connected with one end of a resistor R1, one end of a resistor R2, one end of a resistor R3, one end of a resistor R4, one end of a resistor R5 and one end of a resistor R6, the other end of the resistor R1 is connected with the output end of a multiplier A2, the other end of the resistor R2 is connected with the output end of the operational amplifier U2, the other end of the resistor R3 is connected with the output end of the operational amplifier U4, the other end of the resistor R4 is connected with the output end of the multiplier A3, the other end of the resistor R5 is connected with the positive electrode of a sinusoidal signal source V1, the other end of the resistor R6 is connected with the output end of the operational amplifier U1, and the non-inverting input end of the operational amplifier U1 is grounded, and the output end of the operational amplifier U1 is connected with the inverting input end of the operational amplifier U2 through a resistor R7;
the resistor R10 and the capacitor C1 are connected in parallel to form a first parallel network, and two ends of the first parallel network are respectively connected with the inverting input end of the operational amplifier U2 and the output end of the operational amplifier U2; the non-inverting input end of the operational amplifier U2 is grounded through a resistor R11, the output end of the operational amplifier U2 is connected with the inverting input end of the operational amplifier U3 through a resistor R9, and the output end of the operational amplifier U2 is also connected with the non-inverting input end of the operational amplifier U10 through a resistor R31; one end of a resistor R8 is connected with the inverting input end of the operational amplifier U3, and the other end of the resistor R8 is connected with the output end of the operational amplifier U3; the non-inverting input end of the operational amplifier U3 is grounded, and the output end of the operational amplifier U3 is connected with the inverting input end of the operational amplifier U4 through a resistor R12;
the resistor R13 and the capacitor C2 are connected in parallel to form a second parallel network, two ends of the second parallel network are respectively connected with the inverting input end of the operational amplifier U4 and the output end of the operational amplifier U4, the non-inverting input end of the operational amplifier U4 is grounded through the resistor R14, and the output end of the operational amplifier U4 is connected with the inverting input end of the operational amplifier U5 through the resistor R16;
one end of a resistor R17 is connected with the inverting input end of the operational amplifier U5, and the other end of the resistor R17 is connected with the output end of the operational amplifier U5; the non-inverting input end of the operational amplifier U5 is grounded, and the output end of the operational amplifier U5 is connected with the inverting input end of the operational amplifier U6 through a resistor R15; the resistor R19 and the capacitor C3 form a third parallel network, two ends of the third parallel network are respectively connected with the inverting input end of the operational amplifier U6 and the output end of the operational amplifier U6, the non-inverting input end of the operational amplifier U6 is grounded through the resistor R18, and the output end of the operational amplifier U6 is connected with the Y port of the multiplier A4;
the X port and the Y port of the multiplier A1 are connected with the output end of the operational amplifier U5, and the output port of the multiplier A1 is connected with the Y port of the multiplier A2; the X port of the multiplier A2 is connected with the output end of the operational amplifier U3; the X port and the Y port of the multiplier A4 are connected with the output end of the operational amplifier U6, and the output port of the multiplier A4 is connected with the X port of the multiplier A3; the Y port of the multiplier A3 is connected with the output end of the operational amplifier U5;
the inverting input end of the operational amplifier U7 is respectively connected with one end of a resistor R20, one end of a resistor R21, one end of a resistor R22, one end of a resistor R23 and one end of a resistor R24, the other end of the resistor R20 is connected with the output end of a multiplier A6, the other end of the resistor R21 is connected with the output end of the operational amplifier U8, the other end of the resistor R22 is connected with the inverting input end of the operational amplifier U11 through a resistor R35, the other end of the resistor R22 is also connected with the other end of a resistor R3, the other end of the resistor R23 is connected with the output end of the multiplier A7, and the other end of the resistor R24 is connected with the positive electrode of a sinusoidal signal source V2; the two ends of the resistor R25 are respectively connected with the inverting input end of the operational amplifier U7 and the output end of the operational amplifier U7, the non-inverting input end of the operational amplifier U7 is grounded, and the output end of the operational amplifier U7 is connected with the inverting input end of the operational amplifier U8 through the resistor R26;
the resistor R28 is connected with the capacitor C4 in parallel to form a fourth parallel network, two ends of the fourth parallel network are respectively connected with the inverting input end of the operational amplifier U8 and the output end of the operational amplifier U8, the non-inverting input end of the operational amplifier U8 is grounded through the resistor R29, the output end of the operational amplifier U8 is connected with the inverting input end of the operational amplifier U9 through the resistor R27, and the output end of the operational amplifier U8 is connected with the inverting input end of the operational amplifier U10 through the resistor R33;
the two ends of the resistor R30 are respectively connected with the inverting input end of the operational amplifier U9 and the output end of the operational amplifier U9, the non-inverting input end of the operational amplifier U9 is grounded, and the output end of the operational amplifier U9 is connected with the X port of the multiplier A6; the two ends of the resistor R36 are respectively connected with the inverting input end of the operational amplifier U11 and the output end of the operational amplifier U11, the non-inverting input end of the operational amplifier U11 is grounded, and the output end of the operational amplifier U11 is connected with the inverting input end of the operational amplifier U12 through the resistor R34;
the resistor R38 and the capacitor C5 are connected in parallel to form a fifth parallel network, two ends of the fifth parallel network are connected with the inverting input end of the operational amplifier U12 and the output end of the operational amplifier U12, the non-inverting input end of the operational amplifier U12 is grounded through the resistor R37, and the output end of the operational amplifier U12 is connected with the X port and the Y port of the multiplier A8;
the X port and the Y port of the multiplier A5 are connected with the output end of the operational amplifier U11, and the output port of the multiplier A5 is connected with the Y port of the multiplier A6; the output port of the multiplier A8 is connected with the X port of the multiplier A7; the Y port of the multiplier A7 is connected with the output end of the operational amplifier U11; the non-inverting input terminal of the operational amplifier U10 is grounded through a resistor R32, and the output terminal of the operational amplifier U10 is connected with the inverting input terminal of the operational amplifier U10 through a resistor R39.
Further, the working principle of the chaotic synchronization circuit is as follows:
the method comprises the steps of inputting a sinusoidal signal V1, and obtaining a first output signal after the sinusoidal signal V1 passes through a first summing circuit; the first output signal is integrated by a first integrating circuit to obtain a second output signal; the second output signal is subjected to reverse operation through the first reverse circuit to obtain a third output signal; the third output signal is integrated by the second integrating circuit to obtain a fourth output signal; the fourth output signal is subjected to reverse operation through a second reverse circuit to obtain a fifth output signal; the fifth output signal is integrated by a third integrating circuit to obtain a sixth output signal; the first summing circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and an operational amplifier U1; the first integrating circuit comprises a resistor R7, a resistor R10, a resistor R11, a capacitor C1 and an operational amplifier U2; the first reverse circuit comprises a resistor R9, a resistor R8 and an operational amplifier U3; the second integrating circuit comprises a resistor R12, a resistor R13, a resistor R14, a capacitor C2 and an operational amplifier U4; the second reverse circuit comprises a resistor R16, a resistor R17 and an operational amplifier U5; the third integrating circuit comprises a resistor R15, a resistor R19, a resistor R18, a capacitor C3 and an operational amplifier U6;
the sixth output signal is multiplied by a multiplier A4 to obtain a seventh output signal; the seventh output signal is multiplied with the fifth output signal through a multiplier A3 to obtain an eighth output signal; the fifth output signal is multiplied by a multiplier A1 to obtain a ninth output signal; the ninth output signal is multiplied with the third output signal through a multiplier A2 to obtain a tenth output signal;
the second output signal, the fourth output signal, the eighth output signal and the tenth output signal are reversely added with the sinusoidal signal V1 through the first summing circuit; the sinusoidal signal V1 is reversely added to signals output by the multiplier A2, the multiplier A3, the operational amplifier U2 and the operational amplifier U4 through the first summing circuit, so as to obtain the first output signal.
Inputting a sinusoidal signal V2, and obtaining an eleventh output signal after the sinusoidal signal V2 passes through a second summing circuit; the eleventh output signal is integrated by a fourth integrating circuit to obtain a twelfth output signal; the twelfth output signal is subjected to inverse transformation by a third inverse circuit to obtain a thirteenth output signal; the fourth output signal is subjected to reverse operation through a fourth reverse circuit to obtain a fourteenth output signal; the fourteenth output signal is integrated by a fifth integrating circuit to obtain the fifteenth output signal;
the second summing circuit comprises a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25 and an operational amplifier U7; the fourth integrating circuit comprises a resistor R26, a resistor R28, a resistor R29, a capacitor C4 and an operational amplifier U8; the third inverting circuit comprises a resistor R27, a resistor R30 and an operational amplifier U9; the fourth reverse circuit comprises a resistor R35, a resistor R36 and an operational amplifier U11; the fifth integrating circuit comprises a resistor R34, a resistor R38, a resistor R37, a capacitor C5 and an operational amplifier U12;
the fifteenth output signal is multiplied by a multiplier A8 to obtain a sixteenth output signal; the sixteenth output signal is multiplied with the fourteenth output signal through a multiplier A7 to obtain a seventeenth output signal; the fourteenth output signal is multiplied by a multiplier A5 to obtain an eighteenth output signal; multiplying the eighteenth output signal with the thirteenth output signal through a multiplier A6 to obtain a nineteenth output signal; the fourth output signal, the twelfth output signal, the seventeenth output signal, and the nineteenth output signal are reversely added to the sinusoidal signal V2 through the second summing circuit;
the sinusoidal signal V2 is reversely added to signals output by the multiplier A6, the multiplier A7, the operational amplifier U8 and the operational amplifier U4 through the second summing circuit, so as to obtain the eleventh output signal;
the second output signal and the twelfth output signal are amplified by a differential amplifying circuit to obtain a twentieth output signal; the differential amplifying circuit comprises a resistor R31, a resistor R32, a resistor R33, a resistor R39 and an operational amplifier U10.
Further, the Duffing-Van der pol memristor chaotic oscillator comprises a first magnetic control memristor and a second magnetic control memristor, wherein the first magnetic control memristor comprises the third integrating circuit, the multiplier A3 and the multiplier A4, and the second magnetic control memristor comprises the fifth integrating circuit, the multiplier A7 and the multiplier A8.
Further, the mathematical model of the Duffing-Van der pol memristor chaotic oscillator is shown in a formula (1):
wherein x represents voltage, delta represents nonlinear damping coefficient, gamma represents amplitude of sinusoidal signal, omega represents angular frequency of sinusoidal signal, and t represents time;
the chaotic synchronous circuit designed based on the Duffing-Van der pol memristor chaotic oscillator has two nonlinear systems, a driving and response relationship exists between the two systems, the whole chaotic synchronous circuit is divided into a driving system and a response system, the motion trail of independent variables of the driving system is not influenced by the response system, the response system is controlled by the driving system, namely, a certain independent variable in the driving system is used as a driving variable to drive the response system, so that the driving system and the response system realize synchronization;
a driving system: equation (1) is expressed as a differential equation as shown in equation (2):
wherein x is d 、y d 、z d Is three state variables of the drive system, x d Representing the output voltage, y, of the operational amplifier U6 d Representing the output voltage, z, of the operational amplifier U4 d The output voltage of the operational amplifier U2 is shown, and the memristor value of the magnetic control memristor is shown
By->
Decision, i.e.)>
q represents the charge amount, < >>
Representing magnetic flux->
The value of (2) is equal to the integral of the voltage across the magnetically controlled memristor over time t;
response part: based on the driving system, one state variable is reduced, and the output terminal voltage y of the operational amplifier U4 is introduced d To drive the response system, expressed as a differential equation as shown in equation (3):
wherein x is r 、z r Is responsive to two state variables, x, of the system r Representing the output voltage, z, of the operational amplifier U11 r Representing the output end voltage of the operational amplifier U8, and the memristor value of the magnetic control memristor
By->
Determination, i.e.
q represents the charge amount, < >>
Representing magnetic flux->
The value of (2) is equal to the integral of the voltage across the magnetically controlled memristor over time t.
The technical scheme provided by the invention has the beneficial effects that: the driving-response synchronization method is adopted to realize the chaotic synchronization system with real-time synchronization characteristic by synchronously designing the Duffing-Van der pol memristor chaotic oscillator circuit based on the memristor.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic diagram of a chaotic synchronization circuit based on a Duffing-Van der pol memristor chaotic oscillator in an embodiment of the invention;
FIG. 2 is z in an embodiment of the invention d -z r Phase diagram.
Detailed Description
For a clearer understanding of technical features, objects and effects of the present invention, a detailed description of embodiments of the present invention will be made with reference to the accompanying drawings.
The embodiment of the invention provides a chaotic synchronization circuit based on a Duffing-Van der pol memristor chaotic oscillator.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chaotic synchronization circuit based on a Duffing-Van der pol memristor chaotic oscillator in an embodiment of the present invention, where the chaotic synchronization circuit includes an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, an operational amplifier U7, an operational amplifier U8, an operational amplifier U9, an operational amplifier U10, an operational amplifier U11, an operational amplifier U12, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, a multiplier A5, a multiplier A6, a multiplier A7, a multiplier A8, a peripheral resistor, and two sinusoidal signal sources;
one end of the resistor R1 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R1 is connected with the output end of the multiplier A2; one end of the resistor R2 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R2 is connected with the output end of the operational amplifier U2; one end of a resistor R3 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R3 is connected with the output end of the operational amplifier U4; one end of a resistor R4 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R4 is connected with the output end of the multiplier A3; one end of a resistor R5 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R5 is connected with the positive electrode of the sinusoidal signal source V1; one end of a resistor R6 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R6 is connected with the output end of the operational amplifier U1; the non-inverting input end of the operational amplifier U1 is grounded, and the output end of the operational amplifier U1 is connected with the inverting input end of the operational amplifier U2 through a resistor R7;
the resistor R10 and the capacitor C1 are connected in parallel to form a first parallel network, one end of the first parallel network is connected with the inverting input end of the operational amplifier U2, and the other end of the first parallel network is connected with the output end of the operational amplifier U2; the non-inverting input end of the operational amplifier U2 is grounded through a resistor R11, the output end of the operational amplifier U2 is connected with the inverting input end of the operational amplifier U3 through a resistor R9, and the output end of the operational amplifier U2 is connected with the non-inverting input end of the operational amplifier U10 through a resistor R31; one end of a resistor R8 is connected with the inverting input end of the operational amplifier U3, and the other end of the resistor R8 is connected with the output end of the operational amplifier U3; the non-inverting input end of the operational amplifier U3 is grounded, and the output end of the operational amplifier U3 is connected with the inverting input end of the operational amplifier U4 through a resistor R12;
the resistor R13 and the capacitor C2 are connected in parallel to form a second parallel network, one end of the second parallel network is connected with the inverting input end of the operational amplifier U4, and the other end of the second parallel network is connected with the output end of the operational amplifier U4; the non-inverting input end of the operational amplifier U4 is grounded through a resistor R14, and the output end of the operational amplifier U4 is connected with the inverting input end of the operational amplifier U5 through a resistor R16;
one end of a resistor R17 is connected with the inverting input end of the operational amplifier U5, and the other end of the resistor R17 is connected with the output end of the operational amplifier U5; the non-inverting input end of the operational amplifier U5 is grounded, and the output end of the operational amplifier U5 is connected with the inverting input end of the operational amplifier U6 through a resistor R15; the resistor R19 and the capacitor C3 form a third parallel network, one end of the third parallel network is connected with the inverting input end of the operational amplifier U6, and the other end of the third parallel network is connected with the output end of the operational amplifier U6; the non-inverting input end of the operational amplifier U6 is grounded through a resistor R18, and the output end of the operational amplifier U6 is connected with the Y port of the multiplier A4;
the Y port of the multiplier A1 is connected with the output end of the operational amplifier U5, the X port of the multiplier A1 is connected with the output end of the operational amplifier U5, and the output port of the multiplier A1 is connected with the Y port of the multiplier A2; the X port of the multiplier A2 is connected with the output end of the operational amplifier U3; the X port of the multiplier A4 is connected with the output end of the operational amplifier U6, and the output port of the multiplier A4 is connected with the X port of the multiplier A3; the Y port of the multiplier A3 is connected with the output end of the operational amplifier U5;
one end of a resistor R20 is connected with the inverting input end of the operational amplifier U7, and the other end of the resistor R20 is connected with the output end of the multiplier A6; one end of a resistor R21 is connected with the inverting input end of the operational amplifier U7, and the other end of the resistor R21 is connected with the output end of the operational amplifier U8; one end of a resistor R22 is connected with the inverting input end of the operational amplifier U7, and the other end of the resistor R22 is connected with the inverting input end of the operational amplifier U11 through a resistor R35; one end of a resistor R23 is connected with the inverting input end of the operational amplifier U7, and the other end of the resistor R23 is connected with the output end of the multiplier A7; one end of a resistor R24 is connected with the inverting input end of the operational amplifier U7, and the other end of the resistor R24 is connected with the positive electrode of the sinusoidal signal source V2; one end of a resistor R25 is connected with the inverting input end of the operational amplifier U7, and the other end of the resistor R25 is connected with the output end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is grounded, and the output end of the operational amplifier U7 is connected with the inverting input end of the operational amplifier U8 through a resistor R26;
the resistor R28 and the capacitor C4 are connected in parallel to form a fourth parallel network, one end of the fourth parallel network is connected with the inverting input end of the operational amplifier U8, and the other end of the fourth parallel network is connected with the output end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is grounded through a resistor R29, the output end of the operational amplifier U8 is connected with the inverting input end of the operational amplifier U9 through a resistor R27, and the output end of the operational amplifier U8 is connected with the inverting input end of the operational amplifier U10 through a resistor R33;
one end of a resistor R30 is connected with the inverting input end of the operational amplifier U9, and the other end of the resistor R30 is connected with the output end of the operational amplifier U9; the non-inverting input end of the operational amplifier U9 is grounded, and the output end of the operational amplifier U9 is connected with the X port of the multiplier A6; one end of a resistor R36 is connected with the inverting input end of the operational amplifier U11, and the other end of the resistor R36 is connected with the output end of the operational amplifier U11; the non-inverting input end of the operational amplifier U11 is grounded, and the output end of the operational amplifier U11 is connected with the inverting input end of the operational amplifier U12 through a resistor R34;
the resistor R38 and the capacitor C5 are connected in parallel to form a fifth parallel network, one end of the fifth parallel network is connected with the inverting input end of the operational amplifier U12, and the other end of the fifth parallel network is connected with the output end of the operational amplifier U12; the non-inverting input end of the operational amplifier U12 is grounded through a resistor R37, and the output end of the operational amplifier U12 is connected with the Y port of the multiplier A8;
the Y port of the multiplier A5 is connected with the output end of the operational amplifier U11, the X port of the multiplier A5 is connected with the output end of the operational amplifier U11, and the output port of the multiplier A5 is connected with the Y port of the multiplier A6; the X port of the multiplier A8 is connected with the output end of the operational amplifier U12, and the output port of the multiplier A8 is connected with the X port of the multiplier A7; the Y port of the multiplier A7 is connected with the output end of the operational amplifier U11; the non-inverting input terminal of the operational amplifier U10 is grounded through a resistor R32, and the output terminal of the operational amplifier U10 is connected with the inverting input terminal of the operational amplifier U10 through a resistor R39.
The working principle of the chaotic synchronous circuit is as follows:
the method comprises the steps of inputting a sinusoidal signal V1, and obtaining a first output signal after the sinusoidal signal V1 passes through a first summing circuit; the first output signal is integrated by a first integrating circuit to obtain a second output signal; the second output signal is subjected to reverse operation through the first reverse circuit to obtain a third output signal; the third output signal is integrated by the second integrating circuit to obtain a fourth output signal; the fourth output signal is subjected to reverse operation through a second reverse circuit to obtain a fifth output signal; the fifth output signal is integrated by a third integrating circuit to obtain a sixth output signal; the first summing circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and an operational amplifier U1; the first integrating circuit comprises a resistor R7, a resistor R10, a resistor R11, a capacitor C1 and an operational amplifier U2; the first reverse circuit comprises a resistor R9, a resistor R8 and an operational amplifier U3; the second integrating circuit comprises a resistor R12, a resistor R13, a resistor R14, a capacitor C2 and an operational amplifier U4; the second reverse circuit comprises a resistor R16, a resistor R17 and an operational amplifier U5; the third integrating circuit comprises a resistor R15, a resistor R19, a resistor R18, a capacitor C3 and an operational amplifier U6;
the sixth output signal is multiplied by a multiplier A4 to obtain a seventh output signal; the seventh output signal is multiplied with the fifth output signal through a multiplier A3 to obtain an eighth output signal; the fifth output signal is multiplied by a multiplier A1 to obtain a ninth output signal; the ninth output signal is multiplied with the third output signal through a multiplier A2 to obtain a tenth output signal;
the second output signal, the fourth output signal, the eighth output signal and the tenth output signal are reversely added with the sinusoidal signal V1 through the first summing circuit; the sinusoidal signal V1 is reversely added to signals output by the multiplier A2, the multiplier A3, the operational amplifier U2 and the operational amplifier U4 through the first summing circuit, so as to obtain the first output signal.
Inputting a sinusoidal signal V2, and obtaining an eleventh output signal after the sinusoidal signal V2 passes through a second summing circuit; the eleventh output signal is integrated by a fourth integrating circuit to obtain a twelfth output signal; the twelfth output signal is subjected to inverse transformation by a third inverse circuit to obtain a thirteenth output signal; the fourth output signal is subjected to reverse operation through a fourth reverse circuit to obtain a fourteenth output signal; the fourteenth output signal is integrated by a fifth integrating circuit to obtain the fifteenth output signal;
the second summing circuit comprises a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25 and an operational amplifier U7; the fourth integrating circuit comprises a resistor R26, a resistor R28, a resistor R29, a capacitor C4 and an operational amplifier U8; the third inverting circuit comprises a resistor R27, a resistor R30 and an operational amplifier U9; the fourth reverse circuit comprises a resistor R35, a resistor R36 and an operational amplifier U11; the fifth integrating circuit comprises a resistor R34, a resistor R38, a resistor R37, a capacitor C5 and an operational amplifier U12;
the fifteenth output signal is multiplied by a multiplier A8 to obtain a sixteenth output signal; the sixteenth output signal is multiplied with the fourteenth output signal through a multiplier A7 to obtain a seventeenth output signal; the fourteenth output signal is multiplied by a multiplier A5 to obtain an eighteenth output signal; multiplying the eighteenth output signal with the thirteenth output signal through a multiplier A6 to obtain a nineteenth output signal; the fourth output signal, the twelfth output signal, the seventeenth output signal, and the nineteenth output signal are reversely added to the sinusoidal signal V2 through the second summing circuit;
the sinusoidal signal V2 is reversely added to signals output by the multiplier A6, the multiplier A7, the operational amplifier U8 and the operational amplifier U4 through the second summing circuit, so as to obtain the eleventh output signal;
the second output signal and the twelfth output signal are amplified by a differential amplifying circuit to obtain a twentieth output signal; the differential amplifying circuit comprises a resistor R31, a resistor R32, a resistor R33, a resistor R39 and an operational amplifier U10.
The third integrating circuit, the multiplier A3 and the multiplier A4 form a magnetic control memristor of a first Duffing-Van der pol memristor, and the fifth integrating circuit, the multiplier A7 and the multiplier A8 form a magnetic control memristor of a second Duffing-Van der pol memristor.
The Duffing-Van der pol memristor chaotic oscillator can be expressed as a mathematical model as shown in a formula (1):
where x represents the voltage, δ represents the nonlinear damping coefficient, γ represents the amplitude of the sinusoidal signal, ω represents the angular frequency of the sinusoidal signal, and t represents time.
Based on the Duffing-Van der pol memristor chaotic oscillator, the chaotic synchronous circuit designed by the patent has two nonlinear systems, a driving and responding relation exists between the two nonlinear systems, the whole synchronous circuit is divided into a driving system and a responding system, the motion trail of the independent variable of the driving system is not influenced by the responding system, the behavior of the responding system is controlled by the driving system, namely, the responding system is driven by using a certain independent variable in the driving system as a driving variable, so that the driving system and the responding system realize synchronization.
A driving system: equation (1) is expressed as the following differential equation such as equation (2):
wherein x is d 、y d 、z d Is three state variables of the drive system, x d Representing the output voltage, y, of the operational amplifier U6 d Representing the output voltage, z, of the operational amplifier U4 d The output voltage of the operational amplifier U2 is shown, and the memristor value of the magnetic control memristor is shown
By->
Decision, i.e.)>
q represents the charge amount, < >>
Representing magnetic flux->
The value of (2) is equal to the integral of the voltage across the magnetically controlled memristor over time t;
response part: based on the driving system, one state variable is reduced, and the output terminal voltage y of the operational amplifier U4 is introduced d To drive the response system, expressed as a differential equation as shown in equation (3):
wherein x is r 、z r Is responsive to two state variables, x, of the system r Representing the output voltage, z, of the operational amplifier U11 r The output voltage of the operational amplifier U8 is shown, and the memristor value is controlled by the magnetic control
By->
Determination, i.e.
q represents the charge amount, < >>
Representing magnetic flux->
The value of (2) is equal to the integral of the voltage across the magnetically controlled memristor over time t.
Please refer to fig. 2, a diagram2 is z in the examples of the invention d -z r In the phase diagram, the operational amplifiers U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, U11 and U12 are all selected from the operational amplifier TL082, the multiplier A1, the multiplier A2, the multiplier A3, the multiplier A4, the multiplier A5, the multiplier A6, the multiplier A7 and the multiplier A8 are all selected from the four-quadrant multiplier AD633, the capacitor c1=100 uF, the capacitor c2=100 uF, the capacitor c3=100 uF, the capacitor c4=100 uF, the resistor r1=20kΩ, the resistor r2=20kΩ, the resistor r3=10kΩ, the resistor r4=10kΩ, the resistor r5=10kΩ, the resistor r6=10kΩ, the resistor r7=10kΩ, the resistor r8=10kΩ, the resistor r9=10kΩ, the resistor r10=220kΩ, the resistor r11=9.5kΩ, the resistor r12=10kΩ, the resistor r13=220kΩ, the resistor r14=9.5kΩ, the resistor r15=10kΩ, the resistor r16=10kΩ, the r17=10kΩ, the r18=9.5kΩ, the r19=220kΩ, the resistance r20=20kΩ, the resistance r21=20kΩ, the resistance r22=10kΩ, the resistance r23=10kΩ, the resistance r24=10kΩ, the resistance r25=10kΩ, the resistance r26=10kΩ, the resistance r27=10kΩ, the resistance r28=220kΩ, the resistance r29=9.5 kΩ, the resistance r30=10kΩ, the resistance r31=10kΩ, the resistance r32=10kΩ, the resistance r33=10kΩ, the resistance r34=10kΩ, the resistance r35=10kΩ, the resistance r36=10kΩ, the resistance r37=9.5 kΩ, r38=220kΩ, r39=10kΩ, and the values of the parameters are: gamma=0.5V, ω=1 rad/s,
a＝1，
as can be seen from FIG. 2, the chaotic synchronization circuit based on the Duffing-Van der pol memristor chaotic oscillator has good synchronization characteristics, and can realize the synchronization of a driving system and a response system.
The beneficial effects of the invention are as follows: the driving-response synchronization method is adopted to realize the chaotic synchronization system with real-time synchronization characteristic by synchronously designing the Duffing-Van der pol memristor chaotic oscillator circuit based on the memristor.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (4)
1. A chaotic synchronization circuit based on Duffing-Van derpol memristor chaotic oscillator is characterized in that: the chaotic synchronization circuit comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, an operational amplifier U7, an operational amplifier U8, an operational amplifier U9, an operational amplifier U10, an operational amplifier U11, an operational amplifier U12, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, a multiplier A5, a multiplier A6, a multiplier A7, a multiplier A8, peripheral resistors and two sine signal sources;
the inverting input end of the operational amplifier U1 is respectively connected with one end of a resistor R1, one end of a resistor R2, one end of a resistor R3, one end of a resistor R4, one end of a resistor R5 and one end of a resistor R6, the other end of the resistor R1 is connected with the output end of a multiplier A2, the other end of the resistor R2 is connected with the output end of the operational amplifier U2, the other end of the resistor R3 is connected with the output end of the operational amplifier U4, the other end of the resistor R4 is connected with the output end of the multiplier A3, the other end of the resistor R5 is connected with the positive electrode of a sinusoidal signal source V1, the other end of the resistor R6 is connected with the output end of the operational amplifier U1, and the non-inverting input end of the operational amplifier U1 is grounded, and the output end of the operational amplifier U1 is connected with the inverting input end of the operational amplifier U2 through a resistor R7;
the resistor R10 and the capacitor C1 are connected in parallel to form a first parallel network, and two ends of the first parallel network are respectively connected with the inverting input end of the operational amplifier U2 and the output end of the operational amplifier U2; the non-inverting input end of the operational amplifier U2 is grounded through a resistor R11, the output end of the operational amplifier U2 is connected with the inverting input end of the operational amplifier U3 through a resistor R9, and the output end of the operational amplifier U2 is also connected with the non-inverting input end of the operational amplifier U10 through a resistor R31; one end of a resistor R8 is connected with the inverting input end of the operational amplifier U3, and the other end of the resistor R8 is connected with the output end of the operational amplifier U3; the non-inverting input end of the operational amplifier U3 is grounded, and the output end of the operational amplifier U3 is connected with the inverting input end of the operational amplifier U4 through a resistor R12;
the resistor R13 and the capacitor C2 are connected in parallel to form a second parallel network, two ends of the second parallel network are respectively connected with the inverting input end of the operational amplifier U4 and the output end of the operational amplifier U4, the non-inverting input end of the operational amplifier U4 is grounded through the resistor R14, and the output end of the operational amplifier U4 is connected with the inverting input end of the operational amplifier U5 through the resistor R16;
one end of a resistor R17 is connected with the inverting input end of the operational amplifier U5, and the other end of the resistor R17 is connected with the output end of the operational amplifier U5; the non-inverting input end of the operational amplifier U5 is grounded, and the output end of the operational amplifier U5 is connected with the inverting input end of the operational amplifier U6 through a resistor R15; the resistor R19 and the capacitor C3 form a third parallel network, two ends of the third parallel network are respectively connected with the inverting input end of the operational amplifier U6 and the output end of the operational amplifier U6, the non-inverting input end of the operational amplifier U6 is grounded through the resistor R18, and the output end of the operational amplifier U6 is connected with the Y port of the multiplier A4;
the X port and the Y port of the multiplier A1 are connected with the output end of the operational amplifier U5, and the output port of the multiplier A1 is connected with the Y port of the multiplier A2; the X port of the multiplier A2 is connected with the output end of the operational amplifier U3; the X port and the Y port of the multiplier A4 are connected with the output end of the operational amplifier U6, and the output port of the multiplier A4 is connected with the X port of the multiplier A3; the Y port of the multiplier A3 is connected with the output end of the operational amplifier U5;
the inverting input end of the operational amplifier U7 is respectively connected with one end of a resistor R20, one end of a resistor R21, one end of a resistor R22, one end of a resistor R23 and one end of a resistor R24, the other end of the resistor R20 is connected with the output end of a multiplier A6, the other end of the resistor R21 is connected with the output end of the operational amplifier U8, the other end of the resistor R22 is connected with the inverting input end of the operational amplifier U11 through a resistor R35, the other end of the resistor R22 is also connected with the other end of a resistor R3, the other end of the resistor R23 is connected with the output end of the multiplier A7, and the other end of the resistor R24 is connected with the positive electrode of a sinusoidal signal source V2; the two ends of the resistor R25 are respectively connected with the inverting input end of the operational amplifier U7 and the output end of the operational amplifier U7, the non-inverting input end of the operational amplifier U7 is grounded, and the output end of the operational amplifier U7 is connected with the inverting input end of the operational amplifier U8 through the resistor R26;
the resistor R28 is connected with the capacitor C4 in parallel to form a fourth parallel network, two ends of the fourth parallel network are respectively connected with the inverting input end of the operational amplifier U8 and the output end of the operational amplifier U8, the non-inverting input end of the operational amplifier U8 is grounded through the resistor R29, the output end of the operational amplifier U8 is connected with the inverting input end of the operational amplifier U9 through the resistor R27, and the output end of the operational amplifier U8 is connected with the inverting input end of the operational amplifier U10 through the resistor R33;
the two ends of the resistor R30 are respectively connected with the inverting input end of the operational amplifier U9 and the output end of the operational amplifier U9, the non-inverting input end of the operational amplifier U9 is grounded, and the output end of the operational amplifier U9 is connected with the X port of the multiplier A6; the two ends of the resistor R36 are respectively connected with the inverting input end of the operational amplifier U11 and the output end of the operational amplifier U11, the non-inverting input end of the operational amplifier U11 is grounded, and the output end of the operational amplifier U11 is connected with the inverting input end of the operational amplifier U12 through the resistor R34;
the resistor R38 and the capacitor C5 are connected in parallel to form a fifth parallel network, two ends of the fifth parallel network are connected with the inverting input end of the operational amplifier U12 and the output end of the operational amplifier U12, the non-inverting input end of the operational amplifier U12 is grounded through the resistor R37, and the output end of the operational amplifier U12 is connected with the X port and the Y port of the multiplier A8;
the X port and the Y port of the multiplier A5 are connected with the output end of the operational amplifier U11, and the output port of the multiplier A5 is connected with the Y port of the multiplier A6; the output port of the multiplier A8 is connected with the X port of the multiplier A7; the Y port of the multiplier A7 is connected with the output end of the operational amplifier U11; the non-inverting input terminal of the operational amplifier U10 is grounded through a resistor R32, and the output terminal of the operational amplifier U10 is connected with the inverting input terminal of the operational amplifier U10 through a resistor R39.
2. The chaotic synchronization circuit based on the Duffing-Van derpol memristor chaotic oscillator as set forth in claim 1, wherein: the working principle of the chaotic synchronous circuit is as follows:
the method comprises the steps of inputting a sinusoidal signal V1, and obtaining a first output signal after the sinusoidal signal V1 passes through a first summing circuit; the first output signal is integrated by a first integrating circuit to obtain a second output signal; the second output signal is subjected to reverse operation through the first reverse circuit to obtain a third output signal; the third output signal is integrated by the second integrating circuit to obtain a fourth output signal; the fourth output signal is subjected to reverse operation through a second reverse circuit to obtain a fifth output signal; the fifth output signal is integrated by a third integrating circuit to obtain a sixth output signal; the first summing circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and an operational amplifier U1; the first integrating circuit comprises a resistor R7, a resistor R10, a resistor R11, a capacitor C1 and an operational amplifier U2; the first reverse circuit comprises a resistor R9, a resistor R8 and an operational amplifier U3; the second integrating circuit comprises a resistor R12, a resistor R13, a resistor R14, a capacitor C2 and an operational amplifier U4; the second reverse circuit comprises a resistor R16, a resistor R17 and an operational amplifier U5; the third integrating circuit comprises a resistor R15, a resistor R19, a resistor R18, a capacitor C3 and an operational amplifier U6;
the sixth output signal is multiplied by a multiplier A4 to obtain a seventh output signal; the seventh output signal is multiplied with the fifth output signal through a multiplier A3 to obtain an eighth output signal; the fifth output signal is multiplied by a multiplier A1 to obtain a ninth output signal; the ninth output signal is multiplied with the third output signal through a multiplier A2 to obtain a tenth output signal;
the second output signal, the fourth output signal, the eighth output signal and the tenth output signal are reversely added with the sinusoidal signal V1 through the first summing circuit; the sinusoidal signal V1 is reversely added to signals output by the multiplier A2, the multiplier A3, the operational amplifier U2 and the operational amplifier U4 through the first summing circuit, so as to obtain the first output signal;
inputting a sinusoidal signal V2, and obtaining an eleventh output signal after the sinusoidal signal V2 passes through a second summing circuit; the eleventh output signal is integrated by a fourth integrating circuit to obtain a twelfth output signal; the twelfth output signal is subjected to inverse transformation by a third inverse circuit to obtain a thirteenth output signal; the fourth output signal is subjected to reverse operation through a fourth reverse circuit to obtain a fourteenth output signal; the fourteenth output signal is integrated through a fifth integrating circuit to obtain a fifteenth output signal;
the second summing circuit comprises a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25 and an operational amplifier U7; the fourth integrating circuit comprises a resistor R26, a resistor R28, a resistor R29, a capacitor C4 and an operational amplifier U8; the third inverting circuit comprises a resistor R27, a resistor R30 and an operational amplifier U9; the fourth reverse circuit comprises a resistor R35, a resistor R36 and an operational amplifier U11; the fifth integrating circuit comprises a resistor R34, a resistor R38, a resistor R37, a capacitor C5 and an operational amplifier U12;
the fifteenth output signal is multiplied by a multiplier A8 to obtain a sixteenth output signal; the sixteenth output signal is multiplied with the fourteenth output signal through a multiplier A7 to obtain a seventeenth output signal; the fourteenth output signal is multiplied by a multiplier A5 to obtain an eighteenth output signal; multiplying the eighteenth output signal with the thirteenth output signal through a multiplier A6 to obtain a nineteenth output signal; the fourth output signal, the twelfth output signal, the seventeenth output signal, and the nineteenth output signal are reversely added to the sinusoidal signal V2 through the second summing circuit;
the sinusoidal signal V2 is reversely added to signals output by the multiplier A6, the multiplier A7, the operational amplifier U8 and the operational amplifier U4 through the second summing circuit, so as to obtain the eleventh output signal;
the second output signal and the twelfth output signal are amplified by a differential amplifying circuit to obtain a twentieth output signal; the differential amplifying circuit comprises a resistor R31, a resistor R32, a resistor R33, a resistor R39 and an operational amplifier U10.
3. The chaotic synchronization circuit based on the Duffing-Van derpol memristor chaotic oscillator as claimed in claim 2, wherein the chaotic synchronization circuit is characterized in that: the first Duffing-Van derpol memristor chaotic oscillator comprises the third integrating circuit, the multiplier A3 and the multiplier A4, and the second Duffing-Van derpol memristor chaotic oscillator comprises the fifth integrating circuit, the multiplier A7 and the multiplier A8.
4. The chaotic synchronization circuit based on the Duffing-Van derpol memristor chaotic oscillator as set forth in claim 3, wherein:
the mathematical model of the Duffing-Van derpol memristor chaotic oscillator is shown in a formula (1):
wherein x represents voltage, delta represents nonlinear damping coefficient, gamma represents amplitude of sinusoidal signal, omega represents angular frequency of sinusoidal signal, and t represents time;
the chaotic synchronous circuit designed based on the Duffing-Van derpol memristor chaotic oscillator has two nonlinear systems, a driving and response relationship exists between the two systems, the whole chaotic synchronous circuit is divided into a driving system and a response system, the motion trail of independent variables of the driving system is not influenced by the response system, the response system is controlled by the driving system, namely, a certain independent variable in the driving system is used as a driving variable to drive the response system, so that the driving system and the response system realize synchronization;
a driving system: equation (1) is expressed as a differential equation as shown in equation (2):
wherein x is d 、y d 、z d Is three state variables of the drive system, x d Representing the output voltage, y, of the operational amplifier U6 d Representing the output voltage, z, of the operational amplifier U4 d The output voltage of the operational amplifier U2 is shown, and the memristor value of the magnetic control memristor is shown
By->
Decision, i.e.)>
q represents the charge amount, < >>
Representing magnetic flux->
The value of (2) is equal to the integral of the voltage across the magnetically controlled memristor over time t;
response part: based on the driving system, one state variable is reduced, and the output terminal voltage y of the operational amplifier U4 is introduced d To drive the response system, expressed as a differential equation as shown in equation (3):
wherein x is r 、z r Is in response to two state variables of the system,x r representing the output voltage, z, of the operational amplifier U11 r Representing the output end voltage of the operational amplifier U8, and the memristor value of the magnetic control memristor
By->
Decision, i.e.)>
q represents the charge amount, < >>
Representing magnetic flux->
The value of (2) is equal to the integral of the voltage across the magnetically controlled memristor over time t. />
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