CN110222451B - Third-order absolute value local active memristor circuit model - Google Patents
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Abstract
The invention discloses a mathematical model of a third-order absolute value local active memristor and an equivalent circuit model thereof. The circuit model comprises an integrated operational amplifier U1, an integrated operational amplifier U2, multipliers U3, U4, U5, U6 and U7, and component resistors and capacitors. The integrated operational amplifier U1 is used to implement an integrating operation, an adding operation, and an inverting amplification operation. The integrated operational amplifier U2 is used for absolute value operation, addition operation, and inversion operation to obtain a desired control signal. Multipliers U3, U4, U5, U6, U7 perform multiplication of the signals. The invention designs an equivalent circuit of the local active memristor by utilizing the integrated operational amplifier and the multiplier, and replaces the actual local active memristor to carry out experiments, application and researches.
Description
Technical Field
The invention belongs to the technical field of circuit design, relates to a local active memristor circuit model in an absolute value form, and particularly relates to a mathematical model of a third-order absolute value local active memristor and design and realization of an equivalent circuit model of the mathematical model.
Background
In the field of circuits, locally active devices have the ability to amplify very small weak signals, and locally active characteristics are the origin of all complexities. The local active memristor can generate more complex and rich dynamic behaviors in the circuit so as to meet various requirements of an artificial neural network, a chaotic oscillating circuit and the like, and has important significance for maintaining oscillation and amplifying small signals of a nonlinear dynamic system. As a nonvolatile local active device, the nonvolatile semiconductor device can be applied to various fields such as oscillating circuits, artificial neural networks, nonvolatile memory, digital logic circuits and the like, and has great potential application prospect.
At present, passive memristors are mostly studied at home and abroad, and the concept of local active memristors is recently related. Because the local active characteristics of the memristor are complex, the memristor is in a preliminary theoretical analysis and modeling research state at present, only a few mathematical models are provided, and no commercialized actual device exists yet. The device modeling is a key technology of theoretical analysis and application circuit design, and the mathematical model of the local active memristor and the equivalent circuit thereof are designed under the condition that the actual device of the local active memristor does not appear, so that the device modeling has important significance in enriching the mathematical model of the memristor and replacing the actual memristor with the equivalent circuit for experiment and application research.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a mathematical model of a third-order absolute value local active memristor, designs an equivalent circuit model, is used for simulating the voltage-current characteristic of the memristor, and is applied to circuit design instead of an actual memristor.
The technical scheme adopted for solving the technical problems is as follows:
designing a mathematical model of the local active memristor: i= (|x) 3 |-1)u,dx/dt＝-x 3 +0.64x+u, where i, u, x are the current, voltage, and internal state variables of the memristor, respectively. And designing an equivalent circuit according to the mathematical model. The equivalent circuit comprises a state variable generating circuit for controlling the memristor value and a local active memristor equivalent circuit, wherein the state variable generating circuit for controlling the memristor value consists of an integrated operational amplifier U1 and multipliers U3, U4 and U5, the generated state variable is used as a memristor control input signal of the local active memristor equivalent circuit, and the integrated operational amplifier U1 is used for realizing integral operation, addition operation and inverting amplification operation. The local active memristor equivalent circuit is composed of an integrated operational amplifier U2 and a multiplier U6, wherein the integrated operational amplifier U2 is used for realizing absolute value operation, addition operation and inversion operation to obtain a required control signal, and the multiplier U7 is used for multiplying the control signal and an input voltage signal to obtain the final memristor current.
Preferably, the local active memristor equivalent circuit comprises an integrated operational amplifier U1, an integrated operational amplifier U2, multipliers U3, U4, U5, U6, U7, fourteen resistors and a capacitor; the integrated operational amplifier U1 and the integrated operational amplifier U2 adopt LF347; multipliers U3, U4, U5, U6 and U7 adopt AD633;
the pin 1 of the integrated operational amplifier U1 is connected with the pin 2 through a resistor R4; pin 2 is connected with signals u, -x through resistor R1, resistor R2 and resistor R3 respectively 3 0.64x; pins 3 and 5 are grounded; pin 4 is connected with electricityA source VCC; pin 6 is connected with pin 1 through resistor R5, pin 7 is connected with pin 6 through capacitor C1, and pin 8 is connected with pin 9 through resistor R6; pin 9 is connected to x through resistor R7 3 Pin 10 is grounded; pin 11 connects VEE; the output of the pin 7 is x; pin 8 output is-x 3 。
The multipliers U3, U4 and U5 adopt AD633, and pins 1 and 3 of the multiplier U4 are respectively connected with x; pins 2, 4 and 6 are grounded; pin 8 is connected with power +VS, pin 5 is connected with power-VS; pin 7 is the output x 2 . Multiplier U3 pin 1 is connected with x 2 The method comprises the steps of carrying out a first treatment on the surface of the Pin 3 is connected with x; pins 2, 4 and 6 are grounded; pin 8 is connected with power +VS, pin 5 is connected with power-VS; pin 7 is the output x 3 . The U5 pin 1 of the multiplier is connected with x; pin 3 is connected with 0.64V; pins 2, 4 and 6 are grounded; pin 8 is connected with power +VS, pin 5 is connected with power-VS; pin 7 is an output of 0.64x.
The pin 1 of the integrated operational amplifier U2 is directly connected with the pin 6; pin 2 connection x 3 The method comprises the steps of carrying out a first treatment on the surface of the Pins 3 and 5 are grounded; pin 4 is connected with power VCC; pin 6 is connected with pin 7 through R8; pin 7 is connected to pin 6 through resistor R9; the output of the pin 7 is connected with the pin 1 of the multiplier U6; pin 3 connection x of U6 3 The method comprises the steps of carrying out a first treatment on the surface of the Pins 2, 4 and 6 are grounded; pin 8 is connected with power +VS, pin 5 is connected with power-VS; pin 7 is the output |x 3 I (I); pin 9 of U2 connects pin 7 of multiplier U6 through resistor R10, pin 9 connects-1V through resistor R11; pin 8 of U2 is connected to pin 9 through resistor R12; the output of pin 8 is- |x 3 I+1; pins 10, 12 are grounded; pin 11 connects VEE; pin 13 is connected to- |x through resistor R13 3 I+1; pin 14 is connected to pin 13 through resistor R14; the output of pin 14 is |x 3 |-1。
Pin 1 of multiplier U7 is connected to signal U; pin 3 is connected to pin 14 of integrated op amp U2; pins 2, 4 and 6 are grounded; pin 8 is connected with power +VS; pin 5 is connected to power supply-VS; pin 7 outputs a current i.
The invention designs a mathematical model capable of realizing the volt-ampere characteristic of the local active memristor, and establishes an analog equivalent circuit according to the mathematical model, wherein the analog circuit comprises 2 integrated operational amplifier chips and 5 multipliers, has a simple structure, can replace an actual device to realize circuit design, experiment and application related to the local active memristor under the condition that the actual local active memristor cannot be obtained at present and in the future, and has important practical significance for the characteristic and application research of the local active memristor.
The analog circuit for realizing the local active memristor, which is designed by the invention, realizes the volt-ampere characteristic of the local active memristor by utilizing the analog circuit, and particularly realizes the volt-ampere characteristic of the voltage-controlled local active memristor. The invention utilizes an integrated operational amplifier and an analog multiplier circuit to realize corresponding operation in the characteristic of the memristor, wherein the integrated operational amplifier U1 is mainly used for realizing integral operation, voltage reverse amplification and addition operation of a state variable, and the state variable realizes product operation of an absolute value circuit, an addition circuit, reverse amplification voltage and a memristor control function through the integrated operational amplifier U2 and the multiplier.
Drawings
Fig. 1 is a block diagram of an equivalent circuit of the present invention.
Fig. 2 is a schematic diagram of an analog equivalent circuit of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The theoretical starting point of the invention is a novel voltage-controlled third-order absolute value local active memristor mathematical model defined as follows:
i and u represent the current and voltage of the local active memristor, and the variable x represents the state of the memristor.
According to the mathematical model of the local active memristor, an equivalent circuit model can be designed, and a principle block diagram of the equivalent circuit model is shown in fig. 1.
As shown in fig. 1, the analog equivalent circuit of the voltage-controlled local active memristor of the present example includes an integrated operational amplifier U1, an integrated operational amplifier U2, multipliers U3, U4, U5, U6, U7, and a small amount of resistors and capacitors, where the integrated operational amplifier U1 mainly implements an integrating operation, an adding operation, and an inverting amplification operation; the integrated operational amplifier U2 and the multiplier U6 mainly realize absolute value operation; multipliers U3, U4, U5, U7 implement the multiplication of two signals. U1 and U2 adopt LF347, U3, U4, U5, U6 and U7 adopt AD633, and LF347 and AD633 are all of the prior art.
As shown in FIG. 2, the operational amplifiers corresponding to pins 1, 2 and 3 of the integrated operational amplifier U1 and peripheral resistors R1, R2, R3 and R4 form an inverting adder with inputs U and x respectively 3 0.64x, where x represents the state of the memristor, 0.64x is the W pin voltage of multiplier U6, -x 3 Is the voltage at pin 8 of op-amp U1. Since r1=r2=r3=r4=10k, the voltage at U1 pin 1 is:
u 1-1 ＝-(-x 3 +0.64x+u)
the operational amplifier corresponding to pins 5, 6 and 7 of the integrated operational amplifier U1, the peripheral C1 and the resistor R5 form an integrator for realizing the input voltage U 1-1 Since r5=100m, c1=10nf, the voltage at u1 pin 7 is:
the mathematical model of the local active memristor is known as follows:i.e. x= ≡ (-x) 3 +0.64x+u) dt, then:
u 1-7 ＝∫(-x 3 +0.64x+u)dt＝x
i.e. the voltage u of pin 7 of the integrated operational amplifier 1-7 Representing the state variable x of the memristor.
The operational amplifier corresponding to the 8 th, 9 th and 10 th pins of the integrated operational amplifier U1, and the peripheral resistor R6 and the resistor R7 form an inverting operational amplifier for realizing the inversion of the voltage of the pin 9 of U1, wherein the resistor R6 = R7 = 10K and the voltage of the pin 8 of U1 is U 1-8 ：
Multiplier U5 is used for realizing voltage U of integrated operational amplifier pin 7 1-7 The product operation with voltage 0.64V, namely the voltage of the W pin of the U6 output end:
u 5w ＝0.64u 1-7 ＝0.64x
multiplier U4 is used for realizing voltage U of integrated operational amplifier pin 7 1-7 Square operation of (a), namely the voltage of the W pin of the U4 output end:
u 4w ＝u 1-7 u 1-7 ＝x 2
multiplier U3 is used for realizing voltage U of integrated operational amplifier pin 7 1-7 The product of the voltage of the output end W pin of the U4, namely the voltage of the output end W pin of the U3:
u 3w ＝u 4w u 1-7 ＝x 3
the operational amplifier corresponding to pins 1, 2 and 3 of the integrated operational amplifier U2 forms a negative sign function, the open loop amplification factor of the operational amplifier is set to be A, the output saturation voltage is set to be Esat, the Esat is about 13, the output voltage of the amplifier in a linear region works, and in ideal cases, A-infinity exists. The output voltage of pin 1 is therefore:
u 2-1 ＝-Esat sgn(x 3 )
the 5 th, 6 th and 7 th pins of the integrated operational amplifier U2 and the peripheral resistor R8 and the resistor R9 constitute an inverting operator, because r8=13k, r9=1k, esat≡13, U2 pin 7 outputs a voltage:
pin 1 of the multiplier U6 is connected with pin 7 of U2, and pin 3 of U6 is connected with x 3 The voltage of the W pin of the U6 output end is used for realizing absolute value operation:
u 6w ＝x 3 sgn(x 3 )＝|x 3 |
the operational amplifier corresponding to the 8 th, 9 th and 10 th pins of the integrated operational amplifier U2, and the peripheral resistor R10, the resistor R11 and the resistor R12 form an inverting adder, and r10=r11=r12=10k, the voltage at the U2 pin 8 is:
the operational amplifier corresponding to pins 12, 13, 14 of the integrated operational amplifier U2 and the peripheral resistors R13, R14 form an inverting amplifier for implementing the inverting operation of pin 8 of the integrated operational amplifier U2, where r13=r14=10k, that is, the output voltage of pin 14 of U2 is:
multiplier U7 is used to implement voltage U of integrated operational amplifier pin 14 2-14 The product of the input voltage U is calculated, namely the voltage of the output end W pin of U7:
u 7w ＝(|x 3 |-1)u
the output W of multiplier U7 is the current i, and therefore,
i＝(|x 3 |-1)u
wherein,
x＝∫(-x 3 +0.64x+u)dt
the memristor simulates the volt-ampere characteristic of an equivalent circuit, and the conductance is obtained by comparing the volt-ampere characteristic with the voltage-controlled memristor:
G＝|x 3 |-1
the integrated operational amplifier U1 adopts LM347, and the 1 st pin of the integrated operational amplifier U is connected with the 2 nd pin through a resistor R4; the 2 nd pin is respectively connected with signals u and x through a resistor R1, a resistor R2 and a resistor R3 3 0.64x; pin 3; pin 4 is connected with power VCC; the 5 th pin is grounded; the 6 th pin is connected with the 1 st pin through a resistor R5, the 7 th pin is connected with the 6 th pin through a capacitor C1, and the 8 th pin is connected with the 9 th pin through a resistor R6; the 9 th pin is connected with x through a resistor R7 3 The 10 th pin is grounded; the 11 th pin is connected with VEE; the output of the pin 7 is x; pin 8 output is-x 3 。
Multiplier U3, U4, U5With AD633, multiplier U3 pin 1 is connected to x 2 The method comprises the steps of carrying out a first treatment on the surface of the The 2 nd pin is grounded; the 3 rd pin is connected with x; the 4 th pin is grounded; the 5 th pin is connected with a power supply-VS; the 6 th pin is grounded; pin 7 output x 3 The method comprises the steps of carrying out a first treatment on the surface of the Pin 8 is connected to power +vs. The 1 st pin of the multiplier U4 is connected with x; the 2 nd pin is grounded; the 3 rd pin is connected with x; the 4 th pin is grounded; the 5 th pin is connected with a power supply-VS; the 6 th pin is grounded; the 7 th pin is output x 2 The method comprises the steps of carrying out a first treatment on the surface of the The 8 th pin is connected with a power supply +VS. The 1 st pin of the multiplier U5 is connected with x; pin 3 is connected with 0.64V; the 2 nd pin is grounded; the 4 th pin is grounded; the 5 th pin is connected with a power supply-VS; the 6 th pin is grounded; the 7 th pin is output 0.64x; the 8 th pin is connected with a power supply +VS.
The integrated operational amplifier U2 employs LM347 and the multiplier U6 employs AD633. The 1 st pin and the 6 th pin of the integrated operational amplifier U1 are directly connected; pin 2 connection x 3 The method comprises the steps of carrying out a first treatment on the surface of the The 3 rd pin is grounded; the 4 th pin is connected with a power VCC; the 5 th pin is grounded; the 6 th pin is connected with the 7 th pin through R8; the 7 th pin is connected with the 6 th pin through a resistor R9; the output of the 7 th pin is connected with the 1 st pin of the multiplier U6; the 2 nd pin of U6 is grounded; 3 rd pin connection x 3 The method comprises the steps of carrying out a first treatment on the surface of the The 4 th pin is grounded; the 5 th pin is connected with a power supply-VS; the 6 th pin is grounded; the 7 th pin is the output |x 3 I (I); the 8 th pin is connected with a power supply +VS; the 9 th pin of U2 is connected with the 7 th pin of the multiplier U6 through a resistor R10, and the 8 th pin of U2 is connected with the 9 th pin through a resistor R12; 9 th is connected with-1V through a resistor R11; the output of the 8 th pin is- |x 3 I+1; the 10 th pin is grounded; the 11 th pin is connected with VEE; the 12 th pin is grounded; the 13 th pin is connected with the I x through a resistor R13 3 I+1; the 14 th pin is connected with the 13 th pin through a resistor R14; the output of the 4 th pin is |x 3 |-1。
The multiplier U7 adopts AD633, and the 1 st pin of the multiplier U7 is connected with a signal U; the 2 nd pin is grounded; pin 3 is connected to pin 14 of integrated op amp U2; the 4 th pin is grounded; the 5 th pin is connected with a power supply-VS; the 6 th pin is grounded; the 8 th pin is connected with a power supply +VS; the 7 th pin output is current i.
It will be appreciated by persons skilled in the art that the above embodiments are merely for the purpose of verifying the invention, and are not intended to limit the invention, and that changes and modifications to the above embodiments fall within the scope of the invention as long as they fall within the scope of the invention.
Claims (1)
1. The third-order absolute value local active memristor circuit model is characterized in that the circuit model is designed based on the following mathematical relationship:
i and u are the current and voltage of the memristor respectively, and the variable x is the state of the memristor;
the circuit model comprises an integrated operational amplifier U1, an integrated operational amplifier U2, multipliers U3, U4, U5, U6 and U7, wherein the integrated operational amplifier U1 and the multipliers U3, U4 and U5 form a state variable generating circuit for controlling memristors, and the state variable generating circuit comprises the following components:
the integrated operational amplifier U1 is used for realizing integral operation, addition operation and inverting amplification operation, and takes an output signal as a memristor equivalent circuit memristor control signal;
the local active memristor equivalent circuit is composed of an integrated operational amplifier U2 and multipliers U6 and U7, the integrated operational amplifiers U2 and U6 are used for realizing absolute value large operation, reverse addition operation and reverse operation to obtain a required control signal, and the multiplier U7 is used for multiplying the control signal and voltage quantity to obtain the final memristor current quantity;
specific:
the integrated operational amplifier U1 and the integrated operational amplifier U2 adopt LM324, and the multipliers U3, U4, U5, U6 and U7 adopt AD633;
the 1 st pin of the integrated operational amplifier U1 inputs memristor voltage, and the 7 th pin of the multiplier U7 outputs memristor current;
the 1 st pin of the integrated operational amplifier U1 is connected with the 2 nd pin through a resistor R4; the 2 nd pin is respectively connected with a signal U (t), the 8 th pin of the integrated operational amplifier U1 and the 7 th pin of the multiplier U5 through a resistor R1, a resistor R2 and a resistor R3;
the inputs of pins 1, 2 and 3 of the integrated operational amplifier U1 are U and x respectively 3 0.64x; wherein 0.64x is the 7 th pin voltage of multiplier U5, -x 3 For the voltage of the 8 th pin of the integrated operational amplifier U1, the resistances of the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are the same, and the output voltage U of the 1 st pin of the integrated operational amplifier U1 1-1 ：
u 1-1 ＝-(-x 3 +0.64x+u)；
The 3 rd pin of the integrated operational amplifier U1 is grounded; the 4 th pin is connected with a power VCC;
the 5 th pin of the integrated operational amplifier U1 is grounded; the 6 th pin is connected with the 1 st pin through a resistor R5, the 7 th pin is connected with the 6 th pin through a capacitor C1, and the output voltage u of the capacitor C1 1-7 ：
Wherein R5 is the resistance of the resistor R5, 100MΩ is taken, C1 is the capacitance of the capacitor C1, and 10nF is taken;
the 8 th pin of the integrated operational amplifier U1 is connected with the 9 th pin through a resistor R6; the 9 th pin is connected with x through a resistor R7 3 The 10 th pin is grounded; the operational amplifier corresponding to the 8 th pin, the 9 th pin and the 10 th pin of the integrated operational amplifier U1, the peripheral resistor R6 and the resistor R7 form an inverting operational amplifier, and the inverting operational amplifier is used for realizing voltage inversion of the 9 th pin of the integrated operational amplifier U1;
the 11 th pin of the integrated operational amplifier U1 is connected with VEE;
the 1 st pin of the integrated operational amplifier U2 is connected to the 6 th pin, the 2 nd pin is connected to the 7 th pin of the multiplication U3, and the 3 rd pin is grounded;
the operational amplifiers corresponding to pins 1, 2 and 3 of the integrated operational amplifier U2 form a negative sign function, and if the open-loop amplification factor is A and the output saturation voltage is Esat, the output voltage U of pin 1 of the integrated operational amplifier U2 2-1 ：
u 2-1 ＝-Esatsgn(x 3 )；
The 4 th pin of the integrated operational amplifier U2 is connected with a power supply VCC;
integrated operationThe 5 th pin of the amplifier U2 is grounded, the 6 th pin is connected to the 7 th pin through a resistor R8, and the 7 th pin is connected to the 6 th pin through a resistor R9; output voltage U of 7 th pin of integrated operational amplifier U2 2-7 ：
Wherein R8 is the resistance of the resistor R8, 13KΩ is taken, and R9 is the resistance of the resistor R9, 1KΩ is taken;
the 1 st pin of the multiplier U6 is connected to the 7 th pin of the operational amplifier U2, and the 3 rd pin of the multiplier U6 is connected to the 7 th pin of the multiplier U3;
the 7 th pin of the multiplier U6 is connected to the 9 th pin of the integrated operational amplifier U2 through a resistor R10, -1V is connected to the 9 th pin through a resistor R11, and the 9 th pin of the integrated operational amplifier U2 is connected to the 8 th pin through a resistor R12; the output voltage U of the 8 th pin of the integrated operational amplifier U2 2-8 ：
Wherein R10 is the resistance of resistor R10, R11 is the resistance of resistor R11, R12 is the resistance of resistor R12, and the resistance of the three resistors is 10KΩ;
the 10 th pin of the integrated operational amplifier U2 is grounded, and the 11 th pin is connected with a power supply VEE;
the 12 th pin of the integrated operational amplifier U2 is grounded, the 13 th pin is connected to the 8 th pin through a resistor R13, and the 14 th pin is connected to the 13 th pin through a resistor R14;
output voltage U of 14 th pin of integrated operational amplifier U2 2-14 ：
Wherein R13 is the resistance of resistor R13, R14 is the resistance of resistor R14, and the resistance of both resistors is 10KΩ;
the 1 st pin of the multiplier U7 is connected with the input end of the voltage, the 3 rd pin of the multiplier U7 is connected with the 14 th pin of the U2, and the 7 th pin of the multiplier U7 is the output end of the current;
the multiplier U5 is used for realizing the output voltage U of the 7 th pin of the integrated operational amplifier U1 1-7 Performing product operation with voltage of 0.64V;
the multiplier U4 is used for realizing the output voltage U of the 7 th pin of the integrated operational amplifier U1 1-7 Square operations of (a);
the multiplier U3 is used for realizing the output voltage U of the 7 th pin of the integrated operational amplifier U1 1-7 Product of the output voltage of the output end pin of the multiplier U4;
the multiplier U6 is used for realizing the output voltage U of the 7 th pin of the integrated operational amplifier U2 2-7 Absolute value operation of the output voltage of the 3 rd pin of the multiplier U6;
the multiplier U7 is used for realizing the output voltage U of the 14 th pin of the integrated operational amplifier U2 2-14 The product of the input voltage u.
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| CN103219983A (en) * | 2013-04-16 | 2013-07-24 | 杭州电子科技大学 | Memristor equivalent simulation circuit |
| CN103259518A (en) * | 2013-05-20 | 2013-08-21 | 华南理工大学 | Magnetic control type memory resistor and control method thereof |
| WO2016054340A1 (en) * | 2014-10-02 | 2016-04-07 | Board Of Regents, The University Of Texas System | Coupled memristor devices to enable feedback control and sensing of micro/nanoelectromechanical actuator and sensors |
| CN105450210A (en) * | 2015-12-18 | 2016-03-30 | 杭州电子科技大学 | Memristor simulator circuit based on digital potentiometer |
| CN109086558A (en) * | 2018-09-29 | 2018-12-25 | 杭州电子科技大学 | The local active memristor emulator of logarithmic |
| CN108959837A (en) * | 2018-09-30 | 2018-12-07 | 杭州电子科技大学 | A kind of realization circuit of four values memristor emulator |
| CN109829194A (en) * | 2018-12-28 | 2019-05-31 | 山东科技大学 | A kind of absolute value magnetic control memristor equivalent simulation circuit |
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