CN110728100B - Equivalent analog circuit of segmented voltage-controlled memristor - Google Patents
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Abstract
The invention discloses an equivalent simulation circuit of a segmented voltage-controlled memristor, belongs to the technical field of circuit design, and realizes corresponding operation in the characteristic of a generalized memristor by using an integrated operation circuit so as to realize the volt-ampere characteristic of the segmented voltage-controlled memristor. The integrated operational circuit and the functions thereof included in the invention are as follows: the voltage follower is used for realizing that the output voltage is equal to the input voltage; the inverting integrator is used for realizing inverting integration operation on the input voltage; the inverse proportion device is used for realizing inverse proportion operation on the input voltage; the inverting adder is used for realizing inverting addition operation on the input voltage; the absolute value circuit network is used for realizing absolute value operation on the input voltage; the voltage comparator is used for comparing input voltages at two ends and outputting high and low levels; the multiplication circuit is used for realizing multiplication operation of input voltages at two ends. The memristor-based circuit design and experiment device is simple in structure, can replace an actual generalized memristor to achieve circuit design, experiment and application related to the memristor, and has important significance for researching characteristics and application of the memristor.
Description
Technical Field
The invention belongs to the technical field of circuit design, and particularly relates to a segmented voltage-controlled memristor equivalent analog circuit.
Background
The memristor is a novel basic circuit element, is a nonlinear resistor compared with a resistor, inductor and capacitor circuit element, has the resistance value depending on the history of flowing current, and has the memory function of keeping the resistance value after power failure. In 1971, chua theoretically proposes a guess of feasibility of the memristive element for the first time, and TiO2 memristor objects are not developed and shown in Hewlett packard laboratories until 2008, and the memristor objects have the characteristics of passivity, nonvolatility, nonlinearity, nanoscale, ultralow power consumption and the like. Because of the memory function of the memristor, the memristor is used as a memory and a processor and is a more optimized approach for a new generation of computers. In addition, artificial neural networks are another important application of new memory devices. The human brain basic computing processing unit is synapses and axons, the local passive nonvolatile memristor can well simulate synapse characteristics and is a basic module for simulation, memory and learning. In a word, in the aspects of electronics, artificial intelligence, neural networks and the like, the memristor has a great application prospect, but due to the high cost and difficult realization of the nanotechnology, the memristor entity is not widely used in the market. Therefore, the equivalent analog circuit is used for replacing a physical memristor, and the circuit design and application by using the equivalent analog circuit have wide and profound significance.
At present, reported memristor simulation models comprise hardware simulation equivalent circuits and PSPICE simulation models of memristors, and on one hand, the two memristor models are complex in principle and difficult to realize; on the other hand, the precision of the two types of memristors is not high, and the volt-ampere characteristic of the practical memristor is not difficult to simulate. Therefore, the memristor equivalent analog circuit which is simple in principle, easy to implement and high in accuracy degree is designed to be of great significance.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides the effective analog circuit of the segmented voltage-controlled memristor, which is reasonable in design, overcomes the defects of the prior art and has a good effect.
In order to achieve the purpose, the invention adopts the following technical scheme:
a segmented voltage-controlled memristor equivalent analog circuit comprises a resistance network, a voltage follower, an inverse integrator, an inverse proportioner, an inverse adder, an absolute value circuit network, a voltage comparator and a multiplier;
a voltage follower configured to achieve an output voltage equal to an input voltage;
an inverting integrator configured to perform an inverting integration operation on the input voltage;
an inverting scaler configured to perform an inverting scaling operation on the input voltage;
an inverting adder configured to perform an inverting addition operation on the input voltage;
an absolute value circuit network configured to implement an absolute value operation on an input voltage;
the voltage comparator is configured to be used for comparing input voltages at two ends and outputting high and low levels;
a multiplier configured to realize a multiplication operation on input voltages at two ends;
the segmented voltage-controlled memristor equivalent analog circuit comprises four closed-loop circuits; the circuit comprises a resistor network, a voltage follower U1, a first inverse proportion device U2, a first inverse integrator U3, a second inverse proportion device U6, a second inverse integrator U7, an absolute value networking circuit, a voltage comparator U9, a third inverse proportion device U10, an inverse adder U5 and a fourth inverse proportion device U4, wherein the resistor network, the voltage follower U1, the first inverse proportion device U2, the first inverse integrator U3, the second inverse proportion device U6, the second inverse integrator U7, the absolute value networking circuit, the voltage comparator U9, the third inverse proportion device U10, the inverse adder U5 and the fourth inverse proportion device U4 are sequentially connected through lines to form a first closed loop circuit; the resistance network, the voltage follower U1, the first inverse phase proportion device U2, the first inverse phase integrator U3, the second inverse phase proportion device U6, the first multiplier UA1, the inverse phase adder U5 and the fourth inverse phase proportion device U4 are sequentially connected through a circuit to form a second closed loop circuit; the resistor network, the voltage follower U1, the first inverse phase proportioner U2, the first inverse phase integrator U3, the second inverse phase proportioner U6, the second multiplier UA2, the inverse phase adder U5 and the fourth inverse phase proportioner U4 are sequentially connected through a circuit to form a third closed loop circuit; the resistor network, the voltage follower U1, the first inverse phase proportioner U2, the first inverse phase integrator U3, the second inverse phase proportioner U6, the second multiplier UA1, the second multiplier UA2, the inverse phase adder U5 and the fourth inverse phase proportioner U4 are sequentially connected through a circuit to form a fourth closed loop circuit;
the resistor network comprises a resistor R12, one end of the resistor R12 is connected with a pin 3 of the voltage follower U1 to serve as an input end, and the other end of the resistor R12 is connected with a pin 6 of the fourth inverse phase proportioner U4 to serve as an output end.
The absolute value networking circuit comprises four resistors R16, R17, R18 and R19, a diode D1 and two inverse scalers U8 and U11. The 2 nd pin of the first inverse phase proportioner U8 and the 2 nd pin of the second inverse phase proportioner U11 are respectively connected with one ends of a first resistor R16 and a second resistor R17, the other ends of the two resistors are connected to be used as the input end of the network, and the 6 th pin of the first inverse phase proportioner U8 is used as the output end of the network. A2 nd pin of the first inverse phase proportioner U8 is connected with a 6 th pin thereof through a third resistor R18, a 3 rd pin is respectively connected with a second resistor R17, a diode D1 and a2 nd pin of the second inverse phase proportioner U11, a 4 th pin thereof is connected with a power supply VEE, a 7 th pin thereof is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended; a second pin of the second inverse phase proportioner U11 is connected with a 6 th pin thereof through a diode D1, a 3 rd pin is grounded through a fourth resistor R19, a 4 th pin thereof is connected with a power supply VEE, a 7 th pin thereof is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended;
the input end of the resistor network is connected with a pin 3 of a voltage follower U1, a pin 2 of the voltage follower U1 is connected with a pin 6, the pin 3 is connected with a pin 2 of a first inverse phase proportioner U2 through a first resistor R1, a pin 4 is connected with a power supply VEE, a pin 7 is connected with a power supply VCC, and the pin 1 and the pin 8 are suspended; a2 nd pin of the first inverse phase proportioner U2 is connected with a 6 th pin of the first inverse phase proportioner U2 through a second resistor R2, the 6 th pin of the first inverse phase proportioner U2 is also connected with a2 nd pin of the inverse phase integrator U3 through a third resistor R3, a 3 rd pin of the first inverse phase proportioner U is grounded, a 4 th pin of the first inverse phase proportioner U is connected with a power supply VEE, a 7 th pin of the first inverse phase proportioner U is connected with a power supply VCC, and a1 st pin and an 8 th pin of the first inverse phase proportioner U2 are suspended; a2 nd pin of the inverse integrator U3 is connected with a 6 th pin through a parallel circuit consisting of a fourth resistor R4 and a first capacitor C1, and the 6 th pin is also connected with a second inverse proportion device U6 through a thirteenth resistor R13; a2 nd pin of the second inverse proportion device U6 is connected with a 6 th pin thereof through a fourteenth resistor R14, a sixth pin thereof is respectively connected with an X1 th pin and a Y1 th pin of the first multiplier UA1 and an X1 th pin of the first multiplier UA2, and is connected with a2 nd pin of the second inverse integrator U7 through a fifteenth resistor R15, a 3 rd pin thereof is grounded, a 4 th pin is connected with the power VEE, a 7 th pin is connected with the power VCC, and the 1 st pin and the 8 th pin are suspended; pins X1 and Y1 of the first multiplier UA1 are connected with a sixth pin of a second inverse proportion device U6, a pin X2 and a pin Y2 of the first multiplier UA1 are grounded, a pin VS + is connected with the ground through a third capacitor C3 while being connected with a power supply VCC, a pin VS-is connected with the ground through a fourth capacitor C4 while being connected with a power supply VEE, a pin Z is grounded, a pin W is connected with a pin X1 of the second multiplier UA2 and is also connected with a second pin of an inverse adder U5 through a sixth resistor R6; a pin Y1 of the second multiplier UA2 is connected with a pin sixth of the second inverse proportion device U6, a pin X2 and a pin Y2 are grounded, a pin VS + is connected with a power supply VCC and is connected with the ground through a fifth capacitor C5, a pin VS-is connected with a power supply VEE and is connected with the ground through a sixth capacitor C6, a pin Z is grounded, and a pin W is connected with a pin 2 of the inverse proportion device U5 through a seventh resistor R7; the 2 nd pin of the second inverting integrator U7 is connected to the 6 th pin of the second inverting proportioner U6 through a fifteenth resistor R16, and the 6 th pin thereof is connected to the input end of the absolute value networking. The output end of the absolute value networking is connected with a2 nd pin of an inverse comparator U9, a 3 rd pin of the absolute value networking is connected with a power supply with the voltage of 1V, a 6 th pin of the absolute value networking is connected with a2 nd pin of a third inverse comparator U10 through a sixteenth resistor R20, a 4 th pin of the absolute value networking is connected with a power supply VEE, a 7 th pin of the absolute value networking is connected with a power supply VCC, and a1 st pin and an 8 th pin of the absolute value networking are suspended; a2 nd pin of the third inverse proportion device U10 is respectively connected with a 6 th pin of the inverse comparator U9, a power supply with the voltage of 12V and a 6 th pin of the third inverse proportion device U10 through a twentieth resistor R20, a twenty-first resistor R21 and a twenty-second resistor R22, the 6 th pin of the third inverse proportion device U is also connected with a2 nd pin of the inverse adder through a fifth resistor R5, the 3 rd pin is grounded, the 4 th pin is connected with the power supply VEE, the 7 th pin is connected with the power supply VCC, and the 1 st pin and the 8 th pin are suspended; the 2 nd pin of the inverting adder U5 is connected to the W pin of the first multiplier UA1, the W pin of the second multiplier UA2, the 6 th pin of the third inverting proportioner U10 and the 6 th pin thereof through a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8, respectively, and the 6 th pin thereof is also connected to the 2 nd pin of the fourth inverting proportioner U4 through a ninth resistor R9. The 3 rd pin is grounded, the 4 th pin is connected with a power supply VEE, the 7 th pin is connected with a power supply VCC, and the 1 st pin and the 8 th pin are suspended; the 2 nd pin of the fourth inverse phase proportioner U4 is respectively connected with the 6 th pin of the first inverse phase proportioner U2 and the 6 th pin of the inverse adder through a tenth resistor R10 and a ninth resistor R9, meanwhile, the 6 th pin of the fourth inverse phase proportioner U4 is also respectively connected with the input end of the resistor network and the 2 nd pin of the fourth inverse phase proportioner U2 through a first resistor R12 and an eleventh resistor R11, the 3 rd pin is grounded, the 4 th pin is connected with the power supply VEE, the 7 th pin is connected with the power supply VCC, and the 1 st pin and the 8 th pin are suspended.
As a further improvement scheme, an OP07CP chip is adopted for a voltage follower U1, a first inverse proportion device U2, a first inverse integrator U3, a second inverse proportion device U6, a second inverse integrator U7, a first inverse proportion device U8, a second inverse proportion device U11, a voltage comparator U9, a third inverse proportion device U10, an inverse adder U5 and a fourth inverse proportion device U4 in an absolute value networking circuit; the first multiplier UA1 and the first multiplier UA2 adopt AD633JN chips; the diode adopts a 1N4004 chip.
The invention has the following beneficial technical effects:
the analog equivalent circuit capable of realizing the volt-ampere characteristic of the generalized memristor is designed, the analog circuit comprises 10 operational amplifiers, 2 multipliers and one diode, is simple in structure, can replace the actual generalized memristor to realize circuit design, experiments and application related to the memristor, and has important significance for research on the characteristic and application of the memristor.
The analog circuit for realizing the memristor utilizes the analog circuit to realize the current-voltage characteristic of the generalized memristor, and specifically realizes the current-voltage characteristic of the generalized memristor. According to the memristor characteristic calculating method, corresponding operation in memristor characteristics is achieved through an integrated operation circuit, wherein a voltage follower is used for achieving that output voltage is equal to input voltage, and an inverting integrator is used for achieving inverting integration operation on the input voltage; the inverting adder is used for realizing inverting addition operation on the input voltage; the absolute value circuit network is used for realizing that the output voltage is the absolute value of the input voltage; the inverse proportioner is used for realizing inverse proportion operation of the input voltage; the voltage comparator is used for realizing the comparison of input voltages from two ends and outputting high and low levels; the multiplication circuit is used for realizing multiplication of input signals from two ends.
Drawings
Fig. 1 is a block diagram of the circuit schematic structure of the present invention.
FIG. 2 is an equivalent simulation circuit diagram of the segmented voltage-controlled memristor of the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
the theoretical starting point of the invention is a definition expression of the segmented voltage-controlled memristor:
wherein Fx is defined as
As shown in fig. 1, a segmented voltage-controlled memristor equivalent analog circuit includes a resistance network, a voltage follower, an inverse integrator, an inverse proportioner, an inverse adder, an absolute value circuit network, a voltage comparator and a multiplier; a voltage follower configured to achieve an output voltage equal to an input voltage;
a voltage follower configured for achieving equality of the output voltage and the input voltage;
an inverting integrator configured to perform an inverting integration operation on the input voltage;
an inverse scaler configured to perform an inverse scaling operation on the input voltage;
an inverting adder configured to perform an inverting addition operation on the input voltage;
an absolute value circuit network configured to implement an absolute value operation on an input voltage;
the voltage comparator is configured to be used for comparing input voltages at two ends and outputting high and low levels;
a multiplier configured to perform a multiplication operation on input voltages at both ends;
as shown in FIG. 2, the segmented voltage-controlled memristor equivalent analog circuit includes four closed-loop circuits; the circuit comprises a resistor network, a voltage follower U1, a first inverse proportion device U2, a first inverse integrator U3, a second inverse proportion device U6, a second inverse integrator U7, an absolute value networking circuit, a voltage comparator U9, a third inverse proportion device U10, an inverse adder U5 and a fourth inverse proportion device U4, wherein the resistor network, the voltage follower U1, the first inverse proportion device U2, the first inverse integrator U3, the second inverse proportion device U6, the second inverse integrator U7, the absolute value networking circuit, the voltage comparator U9, the third inverse proportion device U10, the inverse adder U5 and the fourth inverse proportion device U4 are sequentially connected through lines to form a first closed loop circuit; the resistance network, the voltage follower U1, the first inverse proportion device U2, the first inverse integrator U3, the second inverse proportion device U6, the first multiplier UA1, the inverse adder U5 and the fourth inverse proportion device U4 are connected in sequence through lines to form a second closed loop circuit; the resistance network, the voltage follower U1, the first inverse proportion device U2, the first inverse integrator U3, the second inverse proportion device U6, the second multiplier UA2, the inverse adder U5 and the fourth inverse proportion device U4 are sequentially connected through a circuit to form a third closed loop circuit; the resistor network, the voltage follower U1, the first inverse phase proportioner U2, the first inverse phase integrator U3, the second inverse phase proportioner U6, the second multiplier UA1, the second multiplier UA2, the inverse phase adder U5 and the fourth inverse phase proportioner U4 are sequentially connected through a circuit to form a fourth closed loop circuit;
the resistor network comprises a resistor R12, one end of the resistor R12 is connected with a pin 3 of the voltage follower U1 to serve as an input end, and the other end of the resistor R12 is connected with a pin 6 of the fourth inverse phase proportioner U4 to serve as an output end.
The absolute value networking circuit comprises four resistors R16, R17, R18 and R19, a diode D1 and two inverse scalers U8 and U11. The 2 nd pin of the first inverse phase proportioner U8 and the 2 nd pin of the second inverse phase proportioner U11 are respectively connected with one ends of a first resistor R16 and a second resistor R17, the other ends of the two resistors are connected to be used as the input end of the network, and the 6 th pin of the first inverse phase proportioner U8 is used as the output end of the network. A2 nd pin of the first inverse phase proportioner U8 is connected with a 6 th pin thereof through a third resistor R18, a 3 rd pin is respectively connected with a second resistor R17, a diode D1 and a2 nd pin of the second inverse phase proportioner U11, a 4 th pin thereof is connected with a power supply VEE, a 7 th pin thereof is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended; a second pin of the second inverse proportion device U11 is connected with a 6 th pin thereof through a diode D1, a 3 rd pin is grounded through a fourth resistor R19, a 4 th pin thereof is connected with a power supply VEE, a 7 th pin thereof is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended;
the input end of the resistor network is connected with a pin 3 of a voltage follower U1, a pin 2 of the voltage follower U1 is connected with a pin 6, the pin 3 is connected with a pin 2 of a first inverse proportion device U2 through a first resistor R1, a pin 4 is connected with a power supply VEE, a pin 7 is connected with a power supply VCC, and the pin 1 and a pin 8 are suspended; a2 nd pin of the first inverse phase proportioner U2 is connected with a 6 th pin of the first inverse phase proportioner U2 through a second resistor R2, the 6 th pin of the first inverse phase proportioner U2 is also connected with a2 nd pin of the inverse phase integrator U3 through a third resistor R3, a 3 rd pin of the first inverse phase proportioner U is grounded, a 4 th pin of the first inverse phase proportioner U is connected with a power supply VEE, a 7 th pin of the first inverse phase proportioner U is connected with a power supply VCC, and a1 st pin and an 8 th pin of the first inverse phase proportioner U2 are suspended; a2 nd pin of the inverse integrator U3 is connected with a 6 th pin through a parallel circuit consisting of a fourth resistor R4 and a first capacitor C1, and the 6 th pin is also connected with a second inverse proportion device U6 through a thirteenth resistor R13; a2 nd pin of the second inverse proportion device U6 is connected with a 6 th pin thereof through a fourteenth resistor R14, a sixth pin thereof is respectively connected with an X1 th pin and a Y1 th pin of the first multiplier UA1 and an X1 th pin of the first multiplier UA2, and is connected with a2 nd pin of the second inverse integrator U7 through a fifteenth resistor R15, a 3 rd pin thereof is grounded, a 4 th pin is connected with the power VEE, a 7 th pin is connected with the power VCC, and the 1 st pin and the 8 th pin are suspended; pins X1 and Y1 of the first multiplier UA1 are connected with a sixth pin of a second inverse proportion device U6, a pin X2 and a pin Y2 of the first multiplier UA1 are grounded, a pin VS + is connected with the ground through a third capacitor C3 while being connected with a power supply VCC, a pin VS-is connected with the ground through a fourth capacitor C4 while being connected with a power supply VEE, a pin Z is grounded, a pin W is connected with a pin X1 of the second multiplier UA2 and is also connected with a second pin of an inverse adder U5 through a sixth resistor R6; a pin Y1 of the second multiplier UA2 is connected with a pin sixth of the second inverse proportion device U6, a pin X2 and a pin Y2 are grounded, a pin VS + is connected with a power supply VCC and is connected with the ground through a fifth capacitor C5, a pin VS-is connected with a power supply VEE and is connected with the ground through a sixth capacitor C6, a pin Z is grounded, and a pin W is connected with a pin 2 of the inverse proportion device U5 through a seventh resistor R7; the 2 nd pin of the second inverting integrator U7 is connected to the 6 th pin of the second inverting proportioner U6 through a fifteenth resistor R16, and the 6 th pin thereof is connected to the input end of the absolute value networking. The output end of the absolute value networking is connected with a2 nd pin of an inverting comparator U9, a 3 rd pin of the inverting comparator U is connected with a power supply with the voltage of 1V, a 6 th pin of the inverting comparator U is connected with a2 nd pin of a third inverting comparator U10 through a sixteenth resistor R20, a 4 th pin of the inverting comparator U is connected with a power supply VEE, a 7 th pin of the inverting comparator U is connected with a power supply VCC, and a1 st pin and an 8 th pin of the inverting comparator U are suspended; a2 nd pin of the third inverse proportion device U10 is respectively connected with a 6 th pin of the inverse comparator U9, a power supply with the voltage of 12V and a 6 th pin of the third inverse proportion device U10 through a twentieth resistor R20, a twenty-first resistor R21 and a twenty-second resistor R22, the 6 th pin of the third inverse proportion device U is also connected with a2 nd pin of the inverse adder through a fifth resistor R5, the 3 rd pin is grounded, the 4 th pin is connected with the power supply VEE, the 7 th pin is connected with the power supply VCC, and the 1 st pin and the 8 th pin are suspended; the 2 nd pin of the inverting adder U5 is connected to the W pin of the first multiplier UA1 through a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, respectively, the W pin of the second multiplier UA2, the 6 th pin of the third inverting proportioner U10, and the 6 th pin thereof, and meanwhile, the 6 th pin thereof is also connected to the 2 nd pin of the fourth inverting proportioner U4 through a ninth resistor R9. The 3 rd pin is grounded, the 4 th pin is connected with a power supply VEE, the 7 th pin is connected with a power supply VCC, and the 1 st pin and the 8 th pin are suspended; the 2 nd pin of the fourth inverse proportion device U4 is respectively connected with the 6 th pin of the first inverse proportion device U2 and the 6 th pin of the inverse adder through a tenth resistor R10 and a ninth resistor R9, meanwhile, the 6 th pin of the fourth inverse proportion device U4 is also respectively connected with the input end of the resistor network and the 2 nd pin of the fourth inverse proportion device U2 through a first resistor R12 and an eleventh resistor R11, the 3 rd pin is grounded, the 4 th pin is connected with the power supply VEE, the 7 th pin is connected with the power supply VCC, and the 1 st pin and the 8 th pin are suspended.
In a preferred embodiment, the voltage follower U1, the first inverse proportion device U2, the first inverse integrator U3, the second inverse proportion device U6, the second inverse integrator U7, the first inverse proportion device U8 and the second inverse proportion device U11, the voltage comparator U9, the third inverse proportion device U10, the inverse adder U5 and the fourth inverse proportion device U4 in the absolute value networking circuit all adopt an OP07CP chip; the first multiplier UA1 and the first multiplier UA2 adopt AD633JN chips; the diode adopts a 1N4004 chip.
The working principle of the circuit is as follows:
the resistor network comprises a resistor R12, one end of the resistor R12 is connected with a pin 3 of the voltage follower U1 to serve as an input end, and the other end of the resistor R12 is connected with a pin 6 of the fourth inverse proportion device U4 to serve as an output end. The output voltage v of the 3 rd pin of the voltage follower U1 13 To the voltage v of the connection input in And (3) equality:
v 13 ＝v in (3)；
the voltage follower U1 is used for realizing the input voltage v in With currentless, non-attenuating transmission, i.e. pin 6 v of the voltage follower U1 16 Comprises the following steps:
v 16 ＝v 13 ＝v in (4)；
the output value of the first inverse proportion device U2 has inverse proportion relation with the output value, so
v 26 ＝-v 16 ＝-v in (5)；
A first inverting integrator U3 forThe integration of the input current is realized, and the voltage v of the pin 6 of the inverse integrator U3 is defined 36 For the state variable φ of the memristor, the following equation can be obtained:
v 36 ＝φ (6)；
if take R 4 Far greater than R 3 Then, then
The output of the first inverse integrator U3 is obtained by the operation of the second inverse proportion device U6
v 66 ＝-φ (9)；
The second inverse integrator U7 is used to integrate the state variable Φ, and the result is defined as the state variable x, so that the following equation can be obtained:
the X1 and Y1 pins of the first multiplier UA1 are simultaneously connected with the 6 th pin of the second inverse proportion device U6, so the W pin output voltage v of the first multiplier UA1 A1w Comprises the following steps:
v A1w ＝v 66 ·v 66 ＝φ 2 (11)；
the X1 th pin of the second multiplier UA2 is connected with the 6 th pin of the second inverse proportion device U6, the Y1 th pin is connected with the W pin of the first multiplier UA1, namely the W pin output voltage v of the second multiplier UA2 A2w Comprises the following steps:
v A2w ＝v A1w ·v 66 ＝-φ 3 (12)；
the output of the second inverting integrator U7 is connected to an absolute value network for the purpose of shapingThe state variable x is used for absolute value operation, so that the output voltage v in the absolute value networking 86 Comprises the following steps:
v 86 ＝|x| (13)；
output voltage v of absolute value networking 86 Comparing with voltage 1V by a voltage comparator if V 86 If the voltage is less than or equal to 1, the voltage comparator U9 outputs a low level-E U9 Otherwise, high level E is output U9 ，E U9 Is the power supply voltage of the voltage comparator U9, so the output voltage v of the voltage comparator U9 96 Comprises the following steps:
the output voltage of the voltage comparator U9 and the power supply voltage with the voltage value of 12V are used as the input voltage of the third inverse proportion device, so the output voltage V of the third inverse proportion device U10 106 Comprises the following steps:
due to E U9 And v 106 Are all constants, for the sake of calculation, the symbol F X ＝–v 109 ，
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Equation (15) can be transformed into:
the output ends of the first multiplier UA1, the second multiplier UA2 and the third inverse proportion device U10 are connected with different resistors to form a parallel circuit as the input end of the inverse adder U5, so the output voltage v of the inverse adder U5 56 Comprises the following steps:
the 2 nd pin of the fourth inverse proportion device U4 is connected to the 6 th pin of the first inverse proportion device U2 and the 6 th pin of the inverse adder through a tenth resistor R10 and a ninth resistor R9, respectively, and the 6 th pin is also connected to the input terminal of the resistor network and the 2 nd pin thereof through a first resistor R12 and an eleventh resistor R11, respectively. The 6 th pin of the fourth inverse proportion device U4 is the output end of the analog circuit, so the output voltage v 46 Comprises the following steps:
as shown in fig. 2, assuming that the current flowing through the resistor R12 is i (t), the current-voltage characteristic at both ends of the resistor R12 is:
let R 11 /R 10 =1, then equation 19 can be transformed to:
in combination with equations (8) and (10), the internal state variable equation of the equivalent circuit of the segmented voltage-controlled memristor is as follows:
let C 2 R 15 =1 and C 1 R 3 1, the expression of the equivalent circuit of the segmented voltage-controlled memristor is:
compared with equation (1), parameters of segmented voltage-controlled memristor expression
And &>
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make various changes, modifications, additions and substitutions within the spirit and scope of the present invention.
Claims (2)
1. A segmented voltage-controlled memristor equivalent analog circuit is characterized by comprising a resistance network, a voltage follower, an inverse integrator, an inverse proportioner, an inverse adder, an absolute value circuit network, a voltage comparator and a multiplier;
a voltage follower configured to achieve an output voltage equal to an input voltage;
an inverting integrator configured to perform an inverting integration operation on the input voltage;
an inverting scaler configured to perform an inverting scaling operation on the input voltage;
an inverting adder configured to perform an inverting addition operation on the input voltage;
an absolute value circuit network configured to implement an absolute value operation on an input voltage;
the voltage comparator is configured to be used for comparing input voltages at two ends and outputting high and low levels;
a multiplier configured to perform a multiplication operation on input voltages at both ends;
the segmented voltage-controlled memristor equivalent analog circuit comprises four closed-loop circuits; the circuit comprises a resistor network, a voltage follower U1, a first inverse proportion device U2, a first inverse integrator U3, a second inverse proportion device U6, a second inverse integrator U7, an absolute value networking circuit, a voltage comparator U9, a third inverse proportion device U10, an inverse adder U5 and a fourth inverse proportion device U4, wherein the resistor network, the voltage follower U1, the first inverse proportion device U2, the first inverse integrator U3, the second inverse proportion device U6, the second inverse integrator U7, the absolute value networking circuit, the voltage comparator U9, the third inverse proportion device U10, the inverse adder U5 and the fourth inverse proportion device U4 are sequentially connected through lines to form a first closed loop circuit; the resistance network, the voltage follower U1, the first inverse phase proportion device U2, the first inverse phase integrator U3, the second inverse phase proportion device U6, the first multiplier UA1, the inverse phase adder U5 and the fourth inverse phase proportion device U4 are sequentially connected through a circuit to form a second closed loop circuit; the resistor network, the voltage follower U1, the first inverse phase proportioner U2, the first inverse phase integrator U3, the second inverse phase proportioner U6, the second multiplier UA2, the inverse phase adder U5 and the fourth inverse phase proportioner U4 are sequentially connected through a circuit to form a third closed loop circuit; the resistance network, the voltage follower U1, the first inverse proportion device U2, the first inverse integrator U3, the second inverse proportion device U6, the second multiplier UA1, the second multiplier UA2, the inverse adder U5 and the fourth inverse proportion device U4 are sequentially connected through a circuit to form a fourth closed loop circuit;
the resistor network comprises a resistor R12, one end of the resistor R12 is connected with a pin 3 of the voltage follower U1 to serve as an input end, and the other end of the resistor R12 is connected with a pin 6 of the fourth inverse phase proportioner U4 to serve as an output end;
the absolute value networking circuit comprises four resistors R16, R17, R18 and R19, a diode D1 and two inverse scalers U8 and U11; a2 nd pin of the first inverse phase proportioner U8 and a2 nd pin of the second inverse phase proportioner U11 are respectively connected with one ends of a first resistor R16 and a second resistor R17, the other ends of the two resistors are connected to be used as an input end of the network, and a 6 th pin of the first inverse phase proportioner U8 is used as an output end of the network; a2 nd pin of the first inverse proportion device U8 is connected with a 6 th pin thereof through a third resistor R18, a 3 rd pin is respectively connected with a second resistor R17, a diode D1 and a2 nd pin of the second inverse proportion device U11, a 4 th pin thereof is connected with a power supply VEE, a 7 th pin thereof is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended; a second pin of the second inverse phase proportioner U11 is connected with a 6 th pin thereof through a diode D1, a 3 rd pin is grounded through a fourth resistor R19, a 4 th pin thereof is connected with a power supply VEE, a 7 th pin thereof is connected with a power supply VCC, and a1 st pin and an 8 th pin are suspended;
the input end of the resistor network is connected with a pin 3 of a voltage follower U1, a pin 2 of the voltage follower U1 is connected with a pin 6, the pin 3 is connected with a pin 2 of a first inverse phase proportioner U2 through a first resistor R1, a pin 4 is connected with a power supply VEE, a pin 7 is connected with a power supply VCC, and the pin 1 and the pin 8 are suspended; a2 nd pin of the first inverse phase proportioner U2 is connected with a 6 th pin of the first inverse phase proportioner U2 through a second resistor R2, the 6 th pin of the first inverse phase proportioner U2 is also connected with a2 nd pin of the inverse phase integrator U3 through a third resistor R3, a 3 rd pin of the first inverse phase proportioner U is grounded, a 4 th pin of the first inverse phase proportioner U is connected with a power supply VEE, a 7 th pin of the first inverse phase proportioner U is connected with a power supply VCC, and a1 st pin and an 8 th pin of the first inverse phase proportioner U2 are suspended; a2 nd pin of the inverse integrator U3 is connected with a 6 th pin through a parallel circuit consisting of a fourth resistor R4 and a first capacitor C1, and the 6 th pin is also connected with a second inverse proportion device U6 through a thirteenth resistor R13; a2 nd pin of the second inverse proportion device U6 is connected with a 6 th pin thereof through a fourteenth resistor R14, a sixth pin thereof is respectively connected with an X1 th pin and a Y1 th pin of the first multiplier UA1 and an X1 th pin of the first multiplier UA2, and is connected with a2 nd pin of the second inverse integrator U7 through a fifteenth resistor R15, a 3 rd pin thereof is grounded, a 4 th pin is connected with the power VEE, a 7 th pin is connected with the power VCC, and the 1 st pin and the 8 th pin are suspended; pins X1 and Y1 of the first multiplier UA1 are connected with a sixth pin of a second inverse proportion device U6, a pin X2 and a pin Y2 are grounded, a pin VS + is connected with a power supply VCC and is connected with the ground through a third capacitor C3, a pin VS-is connected with a power supply VEE and is connected with the ground through a fourth capacitor C4, a pin Z is grounded, a pin W is connected with a pin X1 of the second multiplier UA2 and is also connected with a second pin of an inverse adder U5 through a sixth resistor R6; a pin Y1 of the second multiplier UA2 is connected with a pin sixth of the second inverse proportion device U6, a pin X2 and a pin Y2 are grounded, a pin VS + is connected with a power supply VCC and is connected with the ground through a fifth capacitor C5, a pin VS-is connected with a power supply VEE and is connected with the ground through a sixth capacitor C6, a pin Z is grounded, and a pin W is connected with a pin 2 of the inverse proportion device U5 through a seventh resistor R7; a2 nd pin of the second inverse integrator U7 is connected with a 6 th pin of the second inverse proportion device U6 through a fifteenth resistor R16, and the 6 th pin of the second inverse integrator U7 is connected with an input end of the absolute value networking; the output end of the absolute value networking is connected with a2 nd pin of an inverting comparator U9, a 3 rd pin of the inverting comparator U is connected with a power supply with the voltage of 1V, a 6 th pin of the inverting comparator U is connected with a2 nd pin of a third inverting comparator U10 through a sixteenth resistor R20, a 4 th pin of the inverting comparator U is connected with a power supply VEE, a 7 th pin of the inverting comparator U is connected with a power supply VCC, and a1 st pin and an 8 th pin of the inverting comparator U are suspended; a2 nd pin of the third inverse proportion device U10 is respectively connected with a 6 th pin of the inverse comparator U9, a power supply with the voltage of 12V and a 6 th pin of the third inverse proportion device U10 through a twentieth resistor R20, a twenty-first resistor R21 and a twenty-second resistor R22, the 6 th pin of the third inverse proportion device U is also connected with a2 nd pin of the inverse adder through a fifth resistor R5, the 3 rd pin is grounded, the 4 th pin is connected with the power supply VEE, the 7 th pin is connected with the power supply VCC, and the 1 st pin and the 8 th pin are suspended; a2 nd pin of the inverting adder U5 is connected to a W pin of the first multiplier UA1, a W pin of the second multiplier UA2, a 6 th pin of the third inverting proportioner U10 and a 6 th pin thereof through a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8, respectively, and the 6 th pin thereof is also connected to a2 nd pin of the fourth inverting proportioner U4 through a ninth resistor R9; the 3 rd pin is grounded, the 4 th pin is connected with a power supply VEE, the 7 th pin is connected with a power supply VCC, and the 1 st pin and the 8 th pin are suspended; the 2 nd pin of the fourth inverse phase proportioner U4 is respectively connected with the 6 th pin of the first inverse phase proportioner U2 and the 6 th pin of the inverse adder through a tenth resistor R10 and a ninth resistor R9, meanwhile, the 6 th pin of the fourth inverse phase proportioner U4 is also respectively connected with the input end of the resistor network and the 2 nd pin of the fourth inverse phase proportioner U2 through a first resistor R12 and an eleventh resistor R11, the 3 rd pin is grounded, the 4 th pin is connected with the power supply VEE, the 7 th pin is connected with the power supply VCC, and the 1 st pin and the 8 th pin are suspended.
2. The segmented voltage-controlled memristor equivalent analog circuit according to claim 1, wherein an OP07CP chip is adopted for each of the voltage follower U1, the first inverse proportion U2, the first inverse integrator U3, the second inverse proportion U6, the second inverse integrator U7, the first inverse proportion U8 and the second inverse proportion U11, the voltage comparator U9, the third inverse proportion U10, the inverse adder U5 and the fourth inverse proportion U4 in the absolute value networking circuit; the first multiplier UA1 and the first multiplier UA2 adopt AD633JN chips; the diode adopts a 1N4004 chip.
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