CN108959837B - Realization circuit of four-value memristor simulator - Google Patents
Realization circuit of four-value memristor simulator Download PDFInfo
- Publication number
- CN108959837B CN108959837B CN201811156823.8A CN201811156823A CN108959837B CN 108959837 B CN108959837 B CN 108959837B CN 201811156823 A CN201811156823 A CN 201811156823A CN 108959837 B CN108959837 B CN 108959837B
- Authority
- CN
- China
- Prior art keywords
- resistor
- pin
- multiplier
- memristor
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000013178 mathematical model Methods 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims 1
- 238000011160 research Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses an implementation circuit of a four-value memristor simulator, which comprises an integrated operational amplifier U1, multipliers U2, U3, U4, U5, U6, U7, U8, U9, U10 and U11, wherein the integrated operational amplifier U1 is connected with an input end, namely a testing end of voltage U and current i of the four-value memristor; the integrated operational amplifier U1 and multipliers U2, U3, U6, U7, U8, U9, U10 and U11 are used for realizing integral operation, summation operation and inversion operation, obtaining state variables for controlling memristive values, and obtaining a required memristive control function. The final memristor current is obtained through the inverse addition operation of the multipliers U4 and U5 and the integrated operational amplifier U1. The invention provides a simulator for realizing the characteristics of a four-value memristor, which is used for simulating the volt-ampere characteristics of the four-value memristor and is convenient for experiments and application researches on the four-value memristor.
Description
Technical Field
The invention belongs to the technical field of circuit design, relates to a four-value memristor simulator, and in particular relates to a mathematical model of a four-value memristor and design and implementation of the simulator.
Background
The four-value memristor is an extension of a binary memristor of a memory device, can enable the memristor to be stabilized to four different balanced states, and can be applied to multi-value digital logic circuits, memristor neural networks, nonvolatile storage and complex chaotic systems. In order to conduct pre-research on the multi-value memristor, the design of the four-value memristor simulator has very important significance.
At present, although a large number of binary memristor models have been proposed, the application range of the binary memristor models has a great limitation. The four-value memristor provided by the invention is an extension type subsequent to the binary memristor, and has more flexible nonvolatile function. The concept and the model of the multi-value memristor are still in a preliminary theoretical analysis and modeling research state due to the lack of the concept and the model of the multi-value memristor at present. Therefore, the simulator for realizing the multi-valued memristor is urgently required to be designed, and the circuit model is used for replacing the actual multi-valued memristor to be applied to a circuit experiment, so that the simulator has very important significance for analysis and research of the memristor.
Disclosure of Invention
Aiming at the defects of the existing binary memristor, the invention provides a mathematical model of the quaternary memristor and a simulator circuit based on the mathematical model, which are used for simulating the volt-ampere characteristic of the quaternary memristor and replacing an actual memristor to carry out circuit design and application.
The technical scheme adopted for solving the technical problems is as follows:
the invention comprises a state variable generating circuit and a measuring port circuit, wherein the state variable generating circuit consists of an integrated operational amplifier U1 and multipliers U2, U3, U6, U7, U8, U9, U10 and U11, the generated state variable x is used as a memristor control input signal of a four-value memristor simulator circuit, and the integrated operational amplifier U1 is used for realizing integral operation, addition operation and inverting amplification operation. The measuring port circuit is composed of an integrated operational amplifier U1 and multipliers U4 and U5, the integrated operational amplifier U1 is used for addition operation to obtain a required control signal, and the multipliers U4 and U5 are used for multiplying the control signal and an input voltage signal to obtain the final four-value memristor current quantity.
The integrated operational amplifier U1 has the 1 st pin connected to one end of the first resistor R1, the 2 nd pin connected to the other end of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the 3 rd and 5 th pins connected to the power VCC, the 6 th pin connected to one end of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the first capacitor C1, the 7 th pin connected to the other end of the first capacitor C1, the 8 th pin connected to one end of the first resistor R14, the 9 th pin connected to the other end of the fourteenth resistor R14, the fifteenth resistor R15, the 10 and 12 pins connected to the ground, the 11 th pin connected to the VEE, the 13 th pin connected to the seventeenth resistor R17 and the sixteenth resistor R16, the seventeenth resistor R16 connected to the other end of the seventeenth resistor R1, and the seventeenth resistor R14 connected to the other end of the seventeenth resistor R1.
The 7 th pin of the multiplier U2 is connected with the 1 st pin and the 3 rd pin of the multiplier U3 and the 3 rd pin of the multiplier U4, the 7 th pin of the multiplier U3 is connected with the other end of the eighth resistor R8 and the other end of the seventeenth resistor R17, the 7 th pin of the multiplier U5 is connected with the other end of the second resistor R2, the 7 th pin of the multiplier U6 is connected with the other end of the fifth resistor R5, the 7 th pin of the multiplier U7 is connected with the other end of the thirteenth resistor R13, the 7 th pin of the multiplier U8 is connected with the 1 st pin of the multiplier U9 and the other end of the tenth resistor R10, the 7 th pin of the multiplier U9 is connected with the 3 rd pin of the multiplier U6 and the other end of the ninth resistor R9, the 7 th pin of the multiplier U10 is connected with the 1 st pin of the multiplier U11 and the other end of the seventh resistor R7, and the 7 th pin of the multiplier U9 is connected with the other end of the ninth resistor R9. The 1 st pin of the multiplier U2 is used as a state variable output end and is connected with the 3 rd pin of the multiplier U8, the 3 rd pin of the multiplier U9, the 1 st pin of the multiplier U10, the 3 rd pin of the multiplier U11, the other end of the eleventh resistor R11, the other end of the fifteenth resistor R15 and the other end of the first capacitor C1.
The 2 nd, 4 th and 6 th pins of the multiplier are grounded, the 5 th pin is connected with a power supply VEE, and the 8 th pin is connected with a power supply VCC.
The invention designs a four-value memristor simulator circuit, which comprises 1 integrated operational amplifier chip and 11 multipliers, has simple structure, expands types and functions of memristors on the basis of the prior two-value memristor, can replace actual devices to realize circuit design, experiment and application related to the four-value memristor, and has important practical significance for the characteristics and application research of the multi-value memristor.
The four-value memristor simulator circuit designed by the invention specifically realizes the volt-ampere characteristic change of the four-value memristor. The invention utilizes an integrated operational amplifier and an analog multiplier circuit to realize corresponding operation in memristor characteristics, wherein the integrated operational amplifier is mainly used for realizing integral operation, voltage reverse amplification and addition operation of state variables, and the analog multiplier is used for realizing product operation of voltage and memristor control function.
Drawings
FIG. 1 is a schematic diagram of a mathematical model of the present invention;
FIG. 2 is a block diagram of an emulator circuit of the present invention;
fig. 3 is a schematic diagram of an emulator circuit of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The theoretical starting point of the invention is a mathematical expression of the volt-ampere characteristics of a four-value memristor:
i and u represent the current and voltage of the four-valued memristor, and x represents the variable state of the four-valued memristor.
As shown in fig. 1, four-value memristors have seven equilibrium points after power failure (u=0): q1 (-1, 0), Q2 (-0.5, 0), Q3 (0, 0), Q4 (0.5, 0), Q5 (0.8, 0), Q6 (1, 0), Q7 (1.5, 0). From the kinetic trace, Q1, Q3, Q5 and Q7 are asymptotically stable equilibrium points, and Q2, Q4 and Q6 are unstable equilibrium points, thus obtaining four stable equilibrium states, i.e., x (Q1) = -1, x (Q3) = 0, x (Q5) = 0.8, x (Q7) = 1.5, corresponding to four stable memristors W (x (Q1))= -5,W (x (Q3))= -5,W (x (Q5))= -5.2304, W (x (Q1))= -2.1875, thereby obtaining a mathematical model of the four-valued memristor.
As shown in fig. 2, the four-value memristor emulator circuit in this example includes an integrated operational amplifier U1, multipliers U2, U3, U4, U5, U6, U7, U8, U9, U10, U11, and a small amount of resistors and capacitors, and the integrated operational amplifier U1 mainly implements an integrating operation, an adding operation, and an inverting amplification operation; the multipliers U2-U11 perform a multiplication operation of the two signals. U1 adopts LM324, U2-U11 adopts AD633, and LM324, AD633 are prior art.
As shown in fig. 3, 4 operational amplifiers are integrated in the integrated operational amplifier U1, wherein the operational amplifiers corresponding to the 1 st, 2 nd and 3 rd pins and the peripheral first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 form an inverting addition operational circuit for realizing the product operation of the voltage of the four-valued memristor and the state variable function thereof, namely the current i of the pin 1 of the U1 m (t)。
This is the voltage and current characteristics of a four-valued memristor emulator circuit, where a, b represent meanings described below.
The operational amplifier corresponding to pins 5, 6 and 7 of the integrated operational amplifier U1, and the operational amplifier corresponding to pins 5, 6 and 7 of the integrated operational amplifier U1, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the first capacitor C1 form a simplified inverting addition and integration operational amplifier, and the input voltage U (t) is input to the pin 6 of the integrated operational amplifier U1 through the twelfth resistor R12 to obtain the state variable x of the memristor.
This is a four-valued memristor state variable function circuit, and a model of the four-valued memristor is obtained immediately in combination with the voltage-current relation function obtained by the above formula, wherein c is mentioned below.
The operational amplifier corresponding to the 8 th, 9 th and 10 th pins of the integrated operational amplifier U1, the fourteenth resistor R14 and the fifteenth resistor R15 form an inverting circuit, and the inverting circuit is used for realizing the voltage inverting gain of the pin 8 of the U1, and the voltage of the pin 9 of the U1 is U 15 (t)。
The operational amplifier corresponding to the 12 th, 13 th and 14 th pins of the integrated operational amplifier U1, the sixteenth resistor R16 and the seventeenth resistor R17 form an inverting circuit for realizing the voltage inverting gain of the pin 14 of the U1, and the voltage of the pin 13 of the U1 is U 17 (t)。
The model of the multiplier U2-U11 is AD633, which is used for realizing the product operation of the input signals.
The integrated operational amplifier U1 has the 1 st pin connected to one end of the first resistor R1, the 2 nd pin connected to the other end of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the 3 rd and 5 th pins grounded, the 4 th pin connected to the power VCC, the 6 th pin connected to one end of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the first capacitor C1, the 7 th pin connected to the other end of the first capacitor C1, the 8 th pin connected to one end of the first resistor R14, the 9 th pin connected to the other end of the fourteenth resistor R14, the fifteenth resistor R15, the 10 th and 12 pins grounded, the 11 th pin connected to the VEE, the 13 th pin connected to the seventeenth resistor R17 and the sixteenth resistor R16, the sixteenth resistor R16 connected to the other end of the seventeenth resistor R1, and the seventeenth resistor R16 connected to the other end of the first resistor R1, and the seventeenth resistor R1 being the output variable.
The 7 th pin of the multiplier U2 is connected with the 1 st and 3 rd pins of the multiplier U3 and the 3 rd pin of the multiplier U4, the 7 th pin of the multiplier U3 is connected with the other end of the eighth resistor R8 and the other end of the seventeenth resistor R17, the 7 th pin of the multiplier U5 is connected with the other end of the second resistor R2, the 7 th pin of the multiplier U6 is connected with the other end of the fifth resistor R5, the 7 th pin of the multiplier U7 is connected with the other end of the thirteenth resistor R13, the 7 th pin of the multiplier U8 is connected with the 1 st pin of the multiplier U9 and the other end of the tenth resistor R10, the 7 th pin of the multiplier U9 is connected with the 3 rd pin of the multiplier U6 and the other end of the ninth resistor R9, the 7 th pin of the multiplier U10 is connected with the 1 st pin of the multiplier U11 and the other end of the seventh resistor R7, and the other end of the ninth resistor R9. The 1 st pin of the multiplier U2 is used as a state variable output end and is connected with the 3 rd pin of the multiplier U8, the 3 rd pin of the multiplier U9, the 1 st pin of the multiplier U10, the 3 rd pin of the multiplier U11, the other end of the eleventh resistor R11, the other end of the fifteenth resistor R15 and the other end of the first capacitor C1.
The 2 nd, 4 th and 6 th pins of the multipliers U2, U3, U4, U5, U6, U7, U8, U9, U10 and U11 are grounded, the 5 th pin is connected with a power supply VEE, the 8 th pin is connected with a power supply VCC, and the 1 st pin, the 3 rd pin and the 7 th pin are input and output ends of the multipliers respectively.
It will be appreciated by persons skilled in the art that the above embodiments are merely for the purpose of verifying the invention, and are not intended to limit the invention, and that changes and modifications to the above embodiments fall within the scope of the invention as long as they fall within the scope of the invention.
Claims (1)
1. The realization circuit of the four-value memristor simulator is characterized by being designed based on the following mathematical model:
i and u are the current and voltage of the memristor, and x is the variable state of the memristor;
the system comprises a state variable generating circuit and a measurement port circuit, wherein the state variable generating circuit consists of an integrated operational amplifier U1 and multipliers U2, U3, U6, U7, U8, U9, U10 and U11, and the generated state variable x is used as a memristor control input signal of a four-value memristor simulator, wherein the integrated operational amplifier U1 is used for realizing integral operation, addition operation and inverting amplification operation; the measuring port circuit is composed of an integrated operational amplifier U1 and multipliers U4 and U5, the integrated operational amplifier U1 is used for adding operation to obtain a control signal, the multipliers U4 and U5 multiply the control signal with an input voltage signal to obtain a final four-value memristor current, and the measuring port circuit has the specific structure as follows:
the integrated operational amplifier U1 has the structure that a 1 st pin is connected with one end of a first resistor R1, a 2 nd pin is connected with the other end of the first resistor R1, one end of a second resistor R2, one end of a third resistor R3 and one end of a fourth resistor R4, 3 rd and 5 th pins are grounded, a 4 th pin is connected with a power supply VCC, a 6 th pin is connected with one end of a fifth resistor R5, one end of a sixth resistor R6, one end of a seventh resistor R7, one end of an eighth resistor R8, one end of a ninth resistor R9, one end of a tenth resistor R10, one end of an eleventh resistor R11, one end of a twelfth resistor R12, one end of a thirteenth resistor R13 and one end of a first capacitor C1, a 7 th pin is connected with the other end of the first capacitor C1, a 9 th pin is connected with the other end of the fourteenth resistor R14, one end of a fifteenth resistor R15 is grounded, a first pin 11 is connected with VEE, a first pin 13 and the other end of the seventeenth resistor R17 and the sixteenth resistor R16 are connected with the other end of the first resistor R1, and the output state of the seventeenth resistor R16 is a fifteenth resistor R1 is the integrated variable state;
the 2 nd, 4 th and 6 th pins of the multipliers U2, U3, U4, U5, U6, U7, U8, U9, U10 and U11 are grounded, the 5 th pin is connected with a power supply VEE, the 8 th pin is connected with a power supply VCC, the 1 st pin and the 3 rd pin are input ends of the multipliers, the 7 th pin is an output end of the multipliers, wherein the 7 th pin of the multiplier U2 is connected with the 1 st and 3 rd pins of the multiplier U3 and the 3 rd pin of the multiplier U4, the 7 th pin of the multiplier U3 is connected with the other end of an eighth resistor R8 and the other end of a seventeenth resistor R17, the 7 th pin of the multiplier U5 is connected with the other end of a second resistor R2, the 7 th pin of the multiplier U6 is connected with the other end of a fifth resistor R5, the 7 th pin of the multiplier U7 is connected with the other end of a thirteenth resistor R13, the 7 th pin of the multiplier U8 is connected with the 1 st pin of the multiplier U9, the other end of the tenth resistor R10 is connected with the other end of the multiplier U9, the 7 th pin of the multiplier U9 is connected with the seventh resistor R7, and the other end of the multiplier U9 is connected with the other end of the multiplier 7R 7; the 1 st pin of the multiplier U2 is used as a state variable output end and is connected with the 3 rd pin of the multiplier U8, the 3 rd pin of the multiplier U9, the 1 st pin of the multiplier U10, the 3 rd pin of the multiplier U11, the other end of the eleventh resistor R11, the other end of the fifteenth resistor R15 and the other end of the first capacitor C1; the integrated operational amplifier U1 adopts LM324, and the multipliers U2-U11 all adopt AD633.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811156823.8A CN108959837B (en) | 2018-09-30 | 2018-09-30 | Realization circuit of four-value memristor simulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811156823.8A CN108959837B (en) | 2018-09-30 | 2018-09-30 | Realization circuit of four-value memristor simulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108959837A CN108959837A (en) | 2018-12-07 |
| CN108959837B true CN108959837B (en) | 2024-03-01 |
Family
ID=64472493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811156823.8A Active CN108959837B (en) | 2018-09-30 | 2018-09-30 | Realization circuit of four-value memristor simulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108959837B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110222451B (en) * | 2019-06-14 | 2023-11-10 | 杭州电子科技大学 | Third-order absolute value local active memristor circuit model |
| CN110598351B (en) * | 2019-09-24 | 2022-11-08 | 杭州电子科技大学 | Threshold type memristor circuit simulator |
| CN110765718B (en) * | 2019-09-24 | 2024-05-03 | 杭州电子科技大学 | Binary memristor circuit simulator |
| CN111950213B (en) * | 2019-11-26 | 2024-03-22 | 杭州电子科技大学 | Simulator circuit model of binary local active memristor |
| CN113054987A (en) * | 2021-03-11 | 2021-06-29 | 杭州电子科技大学 | Homonymy twinborn local active memristor simulator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105373678A (en) * | 2015-12-10 | 2016-03-02 | 杭州电子科技大学 | Circuit for memory capacitor simulator |
| CN205265656U (en) * | 2015-12-15 | 2016-05-25 | 杭州电子科技大学 | Superficially voltage -controlled recall hinder ware emulation ware circuit |
| CN107451380A (en) * | 2017-09-08 | 2017-12-08 | 杭州电子科技大学 | Realize that the circuit of container emulator is recalled in exponential type lotus control |
| CN208705884U (en) * | 2018-09-30 | 2019-04-05 | 杭州电子科技大学 | A kind of four value memristor emulators |
-
2018
- 2018-09-30 CN CN201811156823.8A patent/CN108959837B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105373678A (en) * | 2015-12-10 | 2016-03-02 | 杭州电子科技大学 | Circuit for memory capacitor simulator |
| CN205265656U (en) * | 2015-12-15 | 2016-05-25 | 杭州电子科技大学 | Superficially voltage -controlled recall hinder ware emulation ware circuit |
| CN107451380A (en) * | 2017-09-08 | 2017-12-08 | 杭州电子科技大学 | Realize that the circuit of container emulator is recalled in exponential type lotus control |
| CN208705884U (en) * | 2018-09-30 | 2019-04-05 | 杭州电子科技大学 | A kind of four value memristor emulators |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108959837A (en) | 2018-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108959837B (en) | Realization circuit of four-value memristor simulator | |
| CN108846165B (en) | Four-order local active memristor circuit model | |
| CN107451380B (en) | Circuit for realizing exponential type charge control memory capacitor simulator | |
| CN110245421B (en) | Log absolute value local active memristor circuit model | |
| CN109829194B (en) | Absolute value magnetic control memristor equivalent simulation circuit | |
| CN105553459A (en) | Floating voltage-controlled memristor simulator circuit | |
| CN110598371A (en) | Three-value local active memristor simulator | |
| CN105375914B (en) | It is a kind of to realize the analog circuit for recalling sensor characteristic | |
| CN111079365B (en) | Simulator of arc tangent trigonometric function memristor | |
| CN110222451B (en) | Third-order absolute value local active memristor circuit model | |
| CN108718190B (en) | Exponential type local active memristor simulator | |
| CN109086558B (en) | Logarithmic local active memristor simulator | |
| CN108696274A (en) | A kind of circuit model of exponential type flow control memristor | |
| CN105373679A (en) | Analog circuit for realizing capacitance characteristic of capacitor with memory function | |
| Taherinejad et al. | Fully digital write-in scheme for multi-bit memristive storage | |
| CN110147597B (en) | Multi-stable-state magnetic control memristor equivalent simulation circuit | |
| CN110298435B (en) | Memristor type full-domain value BP neural network circuit | |
| CN209168107U (en) | A kind of circuit model of three values memristor | |
| CN205263816U (en) | Sensilla circuit is recalled to exponent form | |
| CN111079363B (en) | Hyperbolic sinusoidal memristor circuit model | |
| CN108416102B (en) | Recall equivalent analog circuit of inductor | |
| CN109766643A (en) | The circuit model of three value memristors | |
| CN208705884U (en) | A kind of four value memristor emulators | |
| CN109766645B (en) | Circuit model of three-value memory container | |
| CN105373678A (en) | Circuit for memory capacitor simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |