CN205265656U - Superficially voltage -controlled recall hinder ware emulation ware circuit - Google Patents

Abstract

The utility model discloses a superficially voltage -controlled recall hinder ware emulation ware circuit, including integrated operational amplifier U1, multiplier U2 and U3 and a small amount of resistance, electric capacity, the ohmic connection input, resistance and integrated operational amplifier U1 link to each other, utilize that integrated operational amplifier U1 is used for realizing that the difference is enlargied, opposition addition, integral and opposition enlarge, integrated operational amplifier U1 links to each other with multiplier U2, U3, and multiplier U2 links to each other with U3, and multiplier U2, U3 are used for realizing multiplying each other of signal. The utility model discloses utilize analog circuit realized voltage -controlled recall hinder ware voltage -current characteristic.

Description

A kind of voltage-controlled memristor emulator circuit floatingly

Technical field

The utility model belongs to circuit design technique field, relates to a kind of memristor emulator circuit, specifically relates toAnd a kind of design and realization of voltage-controlled memristor emulator circuit floatingly.

Background technology

Memristor is the 4th kind of component mutually arranged side by side with resistance, electric capacity, inductance in circuit, is Cai ShaotangProposed in 1971, within 2008, memristor has been realized in HP Lab. Memristor have non-volatile andNonlinear character, can be applicable to non-loss memory, artificial neural network and circuit design. But,Because existing memristor adopts nanometer technology, exist and realize difficulty and the high defect of cost, memristor is currentAlso do not move towards market as an actual element. Thereby, design a kind of memristor equivalent circuit and replace with itCarry out experiment and application research for actual memristor significant. Even memristor commercialization in the future, alsoBe to exist with the form of large scale integrated circuit, difficulty has the element of single nanoscale memristor to exist, because ofThis, utilizing memristor equivalent circuit to replace actual memristor to carry out application circuit design will have long-range meaningWith value.

At present, though report the existence of a small amount of memristor equivalent circuit, mainly concentrating on magnetic control recalls, not yet there is the equivalent circuit of voltage-controlled memristor, and utilize voltage-controlled in the equivalent circuit of resistance device and lotus control memristorThe circuit of memristor design is simpler than the circuit that contains magnetic control memristor or lotus control memristor, and floats recalling of groundResistance device uses more convenient than the memristor of one end ground connection. Therefore, a kind of voltage-controlled memristor equivalence floatingly of designCircuit is significant.

Summary of the invention

For prior art above shortcomings, the utility model provides a kind of voltage-controlled memristor floatingly imitativeTrue device circuit, in order to simulate the C-V characteristic of voltage-controlled memristor, substitute actual voltage-controlled memristor test withApplication and research.

The technical scheme that the utility model technical solution problem is taked is as follows: the utility model comprises integrated fortuneCalculate amplifier U1, multiplier U2 and multiplier U3.

Resistance R 1 one end connects input (A), is connected with one end of resistance R 2 simultaneously, and other end ground connection,The other end of R2 is connected on integrated operational amplifier U1 pin 3, is connected resistance simultaneously with one end of resistance R 3The other end ground connection of R3; Resistance R 4 one end connect inputs (B), one end phase of the other end and resistance R 5Connect, be connected on integrated operational amplifier U1 pin 2 simultaneously, the other end of resistance R 5 is connected on integrated computation and amplifiesDevice U1 pin 1.

Integrated operational amplifier U1 adopts LF347N; The pin 1 of described integrated operational amplifier U1 passes throughResistance R 5 is joined with pin 2, and pin 2 connects input (B) by R4, and pin 3 connects by R2Described input (A), by R3 ground connection, pin 4 meets power supply VCC, and pin 11 connects power supplyVEE; The pin 1 of integrated operational amplifier U1 is connected with pin 6 by resistance R 8, pin 5 ground connection,Pin 6 connects pin 7 by resistance R 9; Pin 7 joins by resistance R 10 and pin 9; Pin 8 is logicalParallel network and the pin 9 of crossing capacitor C 1 and resistance R 11 join, pin 10 ground connection; Pin 13 passes throughResistance R 12 connects pin 8, pin 12 ground connection; Pin 14 joins by resistance R 13 and pin 13, logicalCrossing resistance R 6 joins with pin 6.

Multiplier U2 adopts AD633JN; The X1 pin of described multiplier U2 meets integrated operational amplifier U1Pin 1, Y1 pin is connected with the pin 8 of integrated operational amplifier U1, X2 pin and Y2 pin connectGround, VS+ pin meets power supply VCC, and VS-pin meets power supply VEE, and Z pin is by resistance R 14 and WPin is connected, and by resistance R 15 ground connection, W pin is connected with the pin 6 of U1 by resistance R 7.

Multiplier U3 adopts AD633JN; The X1 pin of multiplier U3 connects the W pin of multiplier U2,Y1 pin is connected with the pin 8 of integrated operational amplifier U1, X2 pin and Y2 pin ground connection, and VS+ drawsPin meets power supply VCC, and VS-pin meets power supply VEE, and Z pin is connected with W pin by resistance R 16,By resistance R 17 ground connection, W pin is connected with the pin 2 of U1 by resistance R 4.

The utility model has designed a kind ofly can realize the analog equivalent electricity of voltage-controlled memristor C-V characteristic floatinglyRoad, this analog circuit contains 1 integrated transporting discharging and 2 multipliers and a small amount of resistance, electric capacity, at present andCannot obtain in the situation of single isolated voltage-controlled memristor device in the future, can be used for voltage-controlled memristor relevantCircuit design, experiment and application, have great importance to the characteristic and application research of voltage-controlled memristor.

The analog circuit of realizing memristor of the utility model design, it utilizes analog circuit to realize the voltage-controlled resistance of recallingDevice C-V characteristic, specific implementation voltage-controlled memristor C-V characteristic. The utility model utilizes integrated computation circuitRealize the corresponding computing in memristor characteristic with analog multiplier, wherein, integrated operational amplifier mainly in order toRealize the differential amplification of voltage, anti-phase addition, the integral operation of voltage and the anti-phase amplification of voltage of voltage,Analog multiplier is in order to realize the product between voltage and voltage.

Brief description of the drawings

Fig. 1 is circuit structure block diagram of the present utility model.

Fig. 2 is the utility model memristor equivalent simulation circuit theory diagrams.

Detailed description of the invention

Below in conjunction with accompanying drawing, the utility model preferred embodiment is elaborated.

Theoretical starting point of the present utility model is the general expression of voltage-controlled memristor C-V characteristic:

i＝G(z,u)u(t),

$\frac{dz}{dt}=f(z,u).$

Wherein, variable z represents the state of memristor.

As shown in Figure 1, the voltage-controlled memristor simulating equivalent circuit of the present embodiment comprises integrated operational amplifierU1, multiplier U2, U3 and a small amount of resistance, electric capacity, integrated operational amplifier U1 mainly realizes difference to be putAnti-phase addition, integral operation and anti-phase amplification greatly; Multiplier U2, U3 realize multiplying each other of two signals;U1 adopts LF347N, and U2 and U3 adopt AD633JN.

As shown in Figure 2, in the present embodiment, resistance R 1 connects input A and is connected to one end of resistance R 1, resistanceThis end of R1 also joins with one end of resistance R 2, the other end ground connection of resistance R 1, another of resistance R 2End joins with the 3rd pin of integrated operational amplifier U1, joins with the in-phase end of difference amplifier, alsoJoin with one end of resistance R 3, the other end ground connection of resistance R 3. If the input current of circuit is i:

$i=u_A(\frac{1}{R_1}+\frac{1}{R_2+R_3})$

Wherein, u_AFor input A voltage over the ground. Due to R₂+R₃>>R₁, the input current of circuit is approximately:

$i=\frac{R_5}{R_4}\·\frac{u_A}{R_1}$

In integrated operational amplifier U1, have 4 operational amplifiers, wherein, the 1st, 2,3 pins are correspondingOperational amplifier, forms difference amplifier with peripheral resistance R 2, R3, R4, R5, in order to realize both-end electricityPress u to transfer single-ended voltage over the ground to, the voltage of U1 pin 1 is:

$u_1=\frac{R_5}{R_4}(u_A-u_B)$

Wherein, u_BFor input B voltage over the ground, due to R₄＝R₅, the voltage of U1 pin 1 is

u₁＝u_A-u_B

Operational amplifier corresponding to the 5th, 6,7 pin of integrated operational amplifier U1, with peripheral resistanceR6, R7, R8, R9 form anti-phase adder, and the voltage of U1 pin 7 is:

$u_7=-(\frac{R_9}{R_6}{u}_{14}+\frac{R_9}{R_7}{u}_{2w}+\frac{R_9}{R_8}{u}_1)$

Wherein, u_2wFor the W pin voltage of multiplier U2, u₁₄For the electricity of integrated operational amplifier U1 pin 14Press.

The the 8th, 9,10 pins of integrated operational amplifier U1 and peripheral capacitor C 1, resistance R 10, R11Form integrator, in order to realize the integration of input voltage, i.e. the voltage of U1 pin 8:

$u_8=-\frac{1}{R_{10}{C}_1}\∫u_{7}dt=\frac{1}{R_{10}{C}_1}\∫(\frac{R_9}{R_6}{u}_{14}+\frac{R_9}{R_7}{u}_{2w}+\frac{R_9}{R_8}{u}_1)dt$

Operational amplifier corresponding to the 12nd, 13,14 pin of integrated operational amplifier U1, with peripheral resistanceR12, R13 form inverting amplifier, and the voltage of U1 pin 14 is:

$u_{14}=-\frac{R_{13}}{R_{12}}{u}_8=-\frac{R_{13}}{R_{12}{R}_{10}C}\∫(\frac{R_9}{R_6}{u}_{14}+\frac{R_9}{R_7}{u}_{2w}+\frac{R_9}{R_8}{u}_1)dt$

If above formula is represented by differential form, be

$\frac{{\mathrm{du}}_{14}}{dt}=-\frac{R_{13}}{R_{12}{R}_{10}C}(\frac{R_9}{R_6}{u}_{14}+\frac{R_9}{R_7}{u}_{2w}+\frac{R_9}{R_8}{u}_1)$

u₁₄For representing the state of memristor.

Multiplier U2 is in order to realize input voltage u₁Voltage u with U1 pin 8₈Product calculation, i.e. U2The voltage of output W pin:

$u_{2w}=\frac{R_{14}+R_{15}}{10R_{14}}{u}_1{u}_8=-\frac{R_{12}(R_{14}+R_{15})}{10R_{13}{R}_{14}}{u}_1{u}_{14}$

Multiplier U3 is in order to realize the voltage u of U2 output W pin_2wVoltage u with U1 pin 8₈'sProduct calculation, the i.e. voltage of U3 output W pin:

$u_{3w}=\frac{R_{16}+R_{17}}{10R_{16}}\·u_{2w}{u}_8=\frac{R_{16}+R_{17}}{10R_{16}}\·\frac{R_{14}+R_{15}}{10R_{14}}{u}_1{u}_8^2=\frac{R_{14}+R_{15}}{10R_{14}}\·\frac{R_{16}+R_{17}}{10R_{16}}{u}_1{\left(\frac{R_{12}}{R_{13}}{u}_{14}\right)}^2$

As shown in Figure 2, the C-V characteristic of input A, B is:

$u=u_1=u_A-u_B=R_{1}i-u_{3w}=R_{1}i-\frac{R_{14}+R_{15}}{10R_{14}}\·\frac{R_{16}+R_{17}}{10R_{16}}{u}_1{\left(\frac{R_{12}}{R_{13}}{u}_{14}\right)}^2$

Therefore,

$i=\frac{1}{R_1}\[1+\frac{R_{14}+R_{15}}{10R_{14}}\·\frac{R_{16}+R_{17}}{10R_{16}}{\left(\frac{R_{12}}{R_{13}}{u}_{14}\right)}^2\]u$

Wherein,

$u_{14}=-\frac{R_{13}}{R_{12}{R}_{10}C}\∫(\frac{R_9}{R_6}{u}_{14}+\frac{R_9}{R_7}{u}_{2w}+\frac{R_9}{R_8}{u}_1)dt$

The C-V characteristic of memristor simulating equivalent circuit, relatively learn that with voltage-controlled memristor C-V characteristic electricity leads:

$G=\frac{1}{R_1}\[1+\frac{R_{14}+R_{15}}{10R_{14}}\·\frac{R_{16}+R_{17}}{10R_{16}}{\left(\frac{R_{12}}{R_{13}}{u}_{14}\right)}^2\]$

The 1st pin of integrated operational amplifier U1 joins by resistance R 5 and the 2nd pin, and the 2nd pin is logicalCross R4 as signal input part, the 3rd pin passes through R3 ground connection, the 4th connect+15V of pin power supply VCC,The 11st connect-15V of pin power supply VEE; The 1st pin of integrated operational amplifier U1 is by resistance R 8 and the6 pins are connected, the 5th pin ground connection, and the 6th pin connects the 7th pin by resistance R 9; The 7th pin passes throughResistance R 10 and the 9th pin join; The parallel network of the 8th pin by capacitor C 1 and resistance R 11 and the9 pins join, the 10th pin ground connection; The 13rd pin connects the 8th pin by resistance R 12, the 12nd pinGround connection; The 14th pin joins by resistance R 13 and the 13rd pin, by resistance R 6 and the 6th pin phaseConnect.

The X1 pin of multiplier U2 connects the 1st pin of integrated operational amplifier U1, Y1 pin and integratedThe 8th pin of operational amplifier U1 joins, X2 pin and Y2 pin ground connection, connect+15V of VS+ pin electricitySource VCC, connect-15V of VS-pin power supply VEE, Z pin joins by resistance R 14 and W pin, logicalCross resistance R 15 ground connection, W pin joins by resistance R 7 and U1 the 6th pin.

The X1 pin of multiplier U3 connects the W pin of multiplier U2, and Y1 pin and integrated computation amplifyThe 8th pin of device U1 joins, X2 pin and Y2 pin ground connection, connect+15V of VS+ pin power supplyVCC, connect-15V of VS-pin power supply VEE, Z pin joins by resistance R 16 and W pin, passes throughResistance R 17 ground connection, W pin joins by resistance R 4 and U1 the 2nd pin.

Those of ordinary skill in the art will be appreciated that, above embodiment is only new for verifying this practicalityType, and not as to restriction of the present utility model, as long as in scope of the present utility model, to more thanVariation, the distortion of embodiment all will drop in protection domain of the present utility model.

Claims (1)

1. a voltage-controlled memristor emulator circuit floatingly, comprises integrated operational amplifier U1, multiplier U2, multiplier U3; It is characterized in that: resistance R 1 one end connects input (A), be connected with one end of resistance R 2 simultaneously, resistance R 1 one end other end ground connection, the other end of resistance R 2 is connected on integrated operational amplifier U1 pin 3, be connected the other end ground connection of resistance R 3 simultaneously with one end of resistance R 3; Resistance R 4 one end connect input (B), and one end of the other end and resistance R 5 joins, and is connected on integrated operational amplifier U1 pin 2 simultaneously, and the other end of resistance R 5 is connected on integrated operational amplifier U1 pin 1;

Described integrated operational amplifier U1 adopts LF347N; The pin 1 of described integrated operational amplifier U1 joins by resistance R 5 and pin 2, pin 2 connects input (B) by resistance R 4, and pin 3 connects input (A) by resistance R 2, by resistance R 3 ground connection, pin 4 meets power supply VCC, and pin 11 meets power supply VEE; The pin 1 of integrated operational amplifier U1 is connected with pin 6 by resistance R 8, pin 5 ground connection, and pin 6 connects pin 7 by resistance R 9; Pin 7 joins by resistance R 10 and pin 9; Pin 8 joins by parallel network and the pin 9 of capacitor C 1 and resistance R 11, pin 10 ground connection; Pin 13 connects pin 8 by resistance R 12, pin 12 ground connection; Pin 14 joins by resistance R 13 and pin 13, joins by resistance R 6 and pin 6;

Described multiplier U2 adopts AD633JN; The X1 pin of described multiplier U2 connects the pin 1 of integrated operational amplifier U1, Y1 pin is connected with the pin 8 of integrated operational amplifier U1, X2 pin and Y2 pin ground connection, VS+ pin meets power supply VCC, VS-pin meets power supply VEE, Z pin is connected with W pin by resistance R 14, and by resistance R 15 ground connection, W pin is connected with the pin 6 of integrated operational amplifier U1 by resistance R 7;

Described multiplier U3 adopts AD633JN; The X1 pin of multiplier U3 connects the W pin of multiplier U2, Y1 pin is connected with the pin 8 of integrated operational amplifier U1, X2 pin and Y2 pin ground connection, VS+ pin meets power supply VCC, VS-pin meets power supply VEE, Z pin is connected with W pin by resistance R 16, and by resistance R 17 ground connection, W pin is connected with the pin 2 of integrated operational amplifier U1 by resistance R 4.