CN117273103A - Third-order memristor chaotic neuron circuit model and establishment method - Google Patents
Third-order memristor chaotic neuron circuit model and establishment method Download PDFInfo
- Publication number
- CN117273103A CN117273103A CN202311229469.8A CN202311229469A CN117273103A CN 117273103 A CN117273103 A CN 117273103A CN 202311229469 A CN202311229469 A CN 202311229469A CN 117273103 A CN117273103 A CN 117273103A
- Authority
- CN
- China
- Prior art keywords
- memristor
- resistor
- pin
- local active
- control type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 210000002569 neuron Anatomy 0.000 title claims abstract description 55
- 230000000739 chaotic effect Effects 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 21
- 230000005284 excitation Effects 0.000 claims abstract description 9
- 238000013178 mathematical model Methods 0.000 claims description 10
- 230000004044 response Effects 0.000 claims description 5
- 238000004458 analytical method Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000009877 rendering Methods 0.000 claims 1
- 230000006399 behavior Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001537 neural effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000000284 resting effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 210000000225 synapse Anatomy 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N7/00—Computing arrangements based on specific mathematical models
- G06N7/08—Computing arrangements based on specific mathematical models using chaos models or non-linear system models
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Biophysics (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Artificial Intelligence (AREA)
- Health & Medical Sciences (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Neurology (AREA)
- Molecular Biology (AREA)
- General Health & Medical Sciences (AREA)
- Computational Linguistics (AREA)
- Nonlinear Science (AREA)
- Algebra (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a third-order memristor chaotic neuron circuit model and an establishment method thereof, wherein the model comprises a flow control type local active memristor and a capacitorC、InductanceL、ResistorRAnd an excitation voltage source. The key characteristic of the flow control type local active memristor is that the flow control type local active memristor is at DCV‑IThe partial region of the curve presents the characteristic of negative differential resistance, which is the key for designing the memristor neuron circuit model. When a proper voltage excitation is applied to the chaotic neuron circuit formed by the flow control type local active memristor, the inductor and the capacitor, rich neuromorphic behaviors including chaos can be generated by controlling the excitation voltage due to the local active characteristic of the memristor, and a certain model foundation and a certain design theoretical foundation are provided for the neuron circuit design and application based on the flow control type local active memristor.
Description
Technical Field
The invention relates to the field of neuron circuit design, in particular to a third-order chaotic neuron circuit model formed by a flow control type local active memristor and an establishment method thereof.
Background
Because the separate von neumann computing architecture cannot meet the requirement of explosive growth of data volume, the existing computing system has limitations in terms of computing speed, integration level and energy consumption, and needs to break through the traditional framework and search for a new architecture to solve the practical application problem. The neuromorphic computing architecture becomes a research hotspot in the current intelligent computing field with high computing energy efficiency, strong robustness and fault tolerance.
The fundamental units of neuromorphic architecture are neurons and synapses, and modeling and application studies on neurons remain a relatively challenging task due to the complex nonlinear characteristics of neuronal neuromorphics. Recent studies have found that locally active memristors are well suited for use in constructing neuron models due to their unique locally active characteristics.
The nano-scale local active memristor prepared at present has NbO 2 、VO 2 And TaO memristors, which are all fluidic local active memristors, have great potential in terms of neuron modeling, but are limited in that the neuron model established by the memristors based on actual materials is complex and difficult to analyze, and the performance is unstable. Therefore, a simple and effective memristor model capable of simulating key local active characteristics needs to be established, and a chaotic neuron circuit structure capable of reproducing complex chaotic phenomena in the human brain is further established.
Disclosure of Invention
The invention provides a flow control type local active memristor simulator model, and a third-order memristor chaotic neuron circuit is built based on the model.
The first aspect of the invention provides a third-order memristor chaotic neuron circuit model, which comprises a flow control type local active memristor, a capacitor, an inductor, a resistor and a voltage source; one end of the local active memristor is grounded, and the other end of the local active memristor is connected with one end of the inductor and is also a neuron output port; the other end of the inductor is connected with one end of the resistor and one end of the capacitor; the other end of the capacitor is grounded; the other end of the resistor is connected with an excitation voltage source;
the mathematical model of the flow control type local active memristor is as follows:
wherein i, v, x are the current flowing through the memristor, the voltage across the memristor, and the state variables of the memristor, R M C is a memristive function 2 ,d 2 ,a 2 ,h 2 And b 2 Is constant and meets the S-shaped negative differential resistance characteristic of the direct-current voltage-current curve of the current control type local active memristor.
The second aspect of the invention provides a method for establishing a third-order memristor chaotic neuron circuit, which comprises the following steps:
step 1: establishing a mathematical model of the flow control type local active memristor;
step 2: establishing a second-order memristor neuron circuit model;
obtaining the frequency response of a small signal impedance function of the flow control type local active memristor at a local active working point Q by using a small signal analysis method; constructing a second-order memristor neuron circuit model by connecting a parameter with a proper capacitance value in parallel;
step 3: constructing a third-order memristor chaotic neuron circuit model;
and connecting the current control type local active memristor with a capacitor in parallel and then connecting the current control type local active memristor with an inductor L in series to obtain the third-order chaotic neuron circuit based on the current control type local active memristor.
The invention has the beneficial effects that: the invention provides a simple and effective third-order memristor chaotic neuron circuit, which only comprises a flow control type local active memristor, a capacitor, an inductor, a resistor and an excitation voltage signal; the flow control type local memristor can simulate complex nonlinearity and local active characteristics of the existing nanometer local active memristor.
Compared with the existing neuron circuit, the neuron circuit has the advantages of simple structure, simplicity and convenience in implementation, abundant neuromorphic behaviors and the like, and can be used as a neuromorphic calculation architecture unit to construct a brain-like neural network to realize efficient calculation.
Drawings
FIG. 1 is a schematic diagram of a chaotic neuron circuit based on a fluidic-type locally active memristor;
FIG. 2 is a small signal equivalent circuit of a fluidic locally active memristor;
FIG. 3 is a graph showing the morphology of neurons and their regional distribution of parameters;
FIG. 4 is an analog circuit of a three-order memristive chaotic neuron circuit model.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
as shown in fig. 1, the embodiment of the application discloses a third-order memristor chaotic neuron circuit model, which consists of a flow control type local active memristor LAM, a capacitor C, an inductance L, a resistor R and an excitation voltage source. One end of the local active memristor LAM is grounded, and the other end of the local active memristor LAM is connected with one end of the inductor L and is also a neuron output port; one end of the other end of the inductor L is connected with one end of the capacitor C; the other end of the capacitor C is grounded; the other end of the resistor R is connected with an excitation voltage source.
According to the model provided by the embodiment, the application also discloses a process for establishing the third-order memristor chaotic neuron circuit, which comprises the following steps:
step 1: and establishing a mathematical model of the flow control type local active memristor.
(1) According to a Chua's expansion formula of the memristor model, the mathematical model of the universal current control type memristor is:
wherein i and v represent the current flowing through the memristor and the voltage across the memristor, respectively; r is R M (x) Is a memristive function; f (x, i) is a function of memristor state variables x and currents i, and sets of parameters a, β, d, δ may be used to fit memristors with different characteristics.
(2) Let n=1, m=2, p=q=0, a 0 ＝β 0 ＝0，a 1 =1, the memristor state equation with simple design is
The parameter k is set in the equation to represent the state change rate of the memristor, and the working frequency range of the memristor can be controlled by controlling the parameter.
(3) Let dx/dt=0 and v=v in formula (3) to obtain
X＝-β 1 I-β 2 I 2 (4)
(4) To meet the overall passive characteristics of an actual local active memristor, i.e. R M (x)>0, let r=1 here, the dc voltage and current relationship of the memristor can be described as:
V＝R M (X)I＝(d 0 +d 2 (-β 1 I-β 2 I 2 ) 2 )I (5)
to make the DC V-I curve of the memristor show S-shaped negative differential resistance characteristics, namely to meet the condition of the local active memristor, dV/dI <0 in the formula (5) needs to be met, and accordingly, a simple mathematical model of the flow control type local active memristor is provided as follows
Wherein d is 2 ＝2,d 0 ＝20,k＝-1×10 -3 ,β 2 ＝-2.8×10 -3 ,β 1 =1000. The set of parameters can meet the requirement that the DC V-I curve of the memristor shows negative differential resistance characteristics, and the memristor works in the voltage region, so that the memristor has the capability of amplifying small signals, and the memristor has complex characteristics.
Step 2: and (5) establishing a second-order memristor neuron circuit model.
The frequency response of the small signal impedance function of the current control type local active memristor at the local active working point Q can be obtained by using a small signal analysis method, and the frequency response is as follows:
wherein a is 1 ＝1,a 0 ＝-k,b 1 ＝d 2 X 2 +d 0 ,b 0 ＝2d 2 XI(2kβ 2 I+kβ 1 )-k(d 2 X 2 +d 0 )。
The small-signal equivalent circuit of the current-controlled local active memristor is shown in fig. 2. Therefore, a parameter with a proper capacitance value needs to be connected in parallel to construct a second-order neuron model, and the equivalent capacitance value needs to meet C & gtor-Im [ Z (iω, Q) ]/ω.
Step 3: and (3) constructing a third-order memristor chaotic neuron circuit model.
The three-order chaotic neuron circuit based on the current control type local active memristor can be constructed by connecting the current control type local active memristor with a capacitor in parallel and then connecting the current control type local active memristor with an inductor L in series, and a circuit schematic diagram is shown in figure 1. According to kirchhoff's law, the circuit state equation is:
wherein x, v C 、i L Respectively representing the state variable of the memristor, the voltage across the memristor and the current flowing through the inductor.
To show the memristive neuron circuit along with the excitation voltage V D And neuromorphic characteristics of capacitance C changes, plotted as V at l=30mh D Kinetic maps on the C parameter plane and various neuromorphic behaviors at the corresponding locations, as shown in fig. 3. The yellow area in the dynamic map is a stable parameter area, and the circuit works in the area and generally only generates damping oscillation, namely resting potential; the blue and green regions outside the yellow region are unstable local active regions, and the circuit operating in the region can generate neuromorphic behaviors including periodic spikes and chaos, wherein the green region generates periodic spikes for neuronsAnd the blue region is the parameter domain of the chaotic form generated by the neuron, and the boundary between the yellow region and the green region is the Hopf bifurcation line.
Therefore, the third-order neuron circuit based on the flow control type local active memristor can generate rich complex neuromorphic behaviors including chaos.
The schematic diagram of the three-order memristive chaotic neuron circuit model is shown in fig. 4. The simulator circuit of the flow control type local active memristor is designed in the frame line, and comprises an operational amplifier circuit (U1A and U1B, four-way TL 084), a multiplier circuit (U2, U3 and U4, AD 633) and a proper amount of resistor and capacitor, wherein the operational amplifier circuit performs proportional addition and integral operation, and the multiplier circuit is used for realizing multiplication operation. The integrated operational amplifier U1A, U B adopts four-way TL084 chips, the multipliers U2, U3 and U4 adopt AD633 chips, wherein the integrated operational amplifier TL084 and the multiplier AD633 are all of the prior art.
As shown in FIG. 4, part (1) is an addition module in which an operational amplifier U1A and a peripheral resistor R 1 、R 2 、R 3 、R 4 Realize proportional addition operation when R 1 +R 2 ＝R 3 +R 4 At the time, the output terminal voltage v i Is proportional to the current i, R 0 For sampling the resistance, the output voltage v of the part i The method comprises the following steps:
v＝v M +R 0 i (10)
the 1 st pin of the operational amplifier U1A and a resistor R 4 1 st pin and 4 th pin of multiplier U2, resistor R i Is connected with the 1 st pin of the multiplier U4, the 2 nd pin is connected with the resistor R 3 One end of (1) resistor R 4 Is connected with the other end of the resistor R at the 3 rd pin 1 One end of (1) resistor R 2 Is connected with the power supply VCC at the 4 th pin and the power supply VEE at the 11 th pin.
Part (2) is a first signal multiplication operation module, which realizes the multiplication operation of the input signals through a multiplier U2, and obtains an output voltage v at an output end w ii Is that
The 1 st pin and the 4 th pin of the multiplier U2 are connected with the 1 st pin of the operational amplifier U1A, the 2 nd pin and the 3 rd pin are grounded, and the 6 th pin is connected with the resistor R w One end of (1) resistor R z Is connected with one end of the resistor R at the 7 th pin w The other end of (C) and the resistor R ii Is connected with the power supply VEE at the 5 th pin and the power supply VCC at the 8 th pin.
Part (3) is a state variable solving module which solves the state variable x, and the output end is v x ；
Part (3) implements an integration operation by means of a resistor, a capacitor and an operational amplifier U1B, wherein the operational amplifier U1B and a peripheral resistor R i 、R ii 、R x And capacitor C x An integrating circuit is formed to obtain an output voltage v x Is that
The 5 th pin of the operational amplifier U1B is grounded, and the 6 th pin and the resistor R i The other end of (C) and the resistor R ii The other end of (C) and the resistor R x One end of (C) capacitor x Is connected with one end of the resistor R at the 7 th pin x The other end of (C) and the capacitance C x The other end of the (1 st) pin and the 3 rd pin of the multiplier U3 are connected.
Part (4) is a second signal multiplication operation module for implementing multiplication operation of input signals by two multipliers U3 and U4, wherein the multiplier U3 is used for implementing output voltage v of operational amplifier U1B x The proportional square operation of (2) can obtain the output voltage of 0.1v x 2 The method comprises the steps of carrying out a first treatment on the surface of the Multiplier U4 is used for realizing output voltage 0.1v of multiplier U3 x 2 And v i Can obtain the output voltage v by proportional multiplication M Is that
The 1 st pin and the 3 rd pin of the multiplier U3 are connected with the 7 th pin of the operational amplifier U1B, the 2 nd pin, the 4 th pin and the 6 th pin are grounded, the 7 th pin is connected with the 3 rd pin of the multiplier U4, the 5 th pin is connected with a power supply VEE, and the 8 th pin is connected with a power supply VCC; the 1 st pin of the multiplier U4 is connected with the 1 st pin of the operational amplifier U1A, the 3 rd pin is connected with the 7 th pin of the multiplier U3, the 2 nd pin and the 4 th pin are grounded, and the 6 th pin is connected with the resistor R w1 One end of (1) resistor R z1 Is connected with one end of the resistor R at the 7 th pin w1 The other end of the power supply VCC is connected with the 5 th pin and the power supply VEE.
Thus, it can be deduced that:
the parameter design of the third-order memristive chaotic neuron circuit is shown in table 1.
Table 1 three-order memristor chaotic neuron circuit parameter design
Claims (9)
1. A three-order memristor chaotic neuron circuit model comprises a flow control type local active memristor, a capacitor, an inductor, a resistor and a voltage source; one end of the local active memristor is grounded, and the other end of the local active memristor is connected with one end of the inductor and is also a neuron output port; the other end of the inductor is connected with one end of the resistor and one end of the capacitor; the other end of the capacitor is grounded; the other end of the resistor is connected with an excitation voltage source, and the resistor is characterized in that:
the mathematical model of the flow control type local active memristor is as follows:
wherein i, v, x are the current flowing through the memristor, the voltage across the memristor, and the state variables of the memristor, R M C is a memristive function 2 ,d 2 ,a 2 ,h 2 And b 2 Is constant and meets the S-shaped negative differential resistance characteristic of the direct-current voltage-current curve of the current control type local active memristor.
2. The third-order memristive chaotic neuron circuit model according to claim 1, wherein: the equivalent capacitance value of the capacitor is greater than-Im [ Z (iw, Q) ]/w, wherein w is the frequency of a small signal impedance function of the current-controlled local active memristor at a local active operating point Q, and Z (iw, Q) is the frequency response.
3. The third-order memristive chaotic neuron circuit model according to claim 1, wherein: the flow control type local active memristor comprises a proportional addition operation module, a first signal multiplication operation module, a state variable solving module and a second signal multiplication operation module.
4. The third-order memristive chaotic neuron circuit model according to claim 3, wherein: the addition operation module comprises an operational amplifier U1A and a peripheral resistor R 1 、R 2 、R 3 、R 4 The positive input termination resistor R of the operational amplifier U1A 1 、R 2 One end of resistor R 1 The other end of the resistor is used as one end of a flow control type local active memristor; resistor R 2 The other end of the first electrode is grounded; the inverting input termination resistor R of the operational amplifier U1A 3 、R 4 One end of resistor R 4 The other end is connected with the output end of the operational amplifier U1A.
5. The third-order memristive chaotic neuron circuit model according to claim 4, wherein: the first signal multiplication operation module comprises a multiplier U2, wherein the 1 st pin and the 4 th pin of the multiplier U2 are connected with the output end of an operational amplifier U1A, the 2 nd pin and the 3 rd pin are grounded, and the 6 th pin is connected with a resistor R w One end of (1) resistor R z Is connected with one end of the resistor R at the 7 th pin w The other end of the system is connected with a state variable solving module.
6. The third-order memristive chaotic neuron circuit model according to claim 5, wherein: the state variable solving module comprises an operational amplifier U1B, wherein the positive input end of the operational amplifier U1B is grounded, and the negative input end of the operational amplifier U1B is connected with a resistor R i The other end of (C) and the resistor R ii The other end of (C) and the resistor R x One end of (C) capacitor x Is connected with one end of the resistor R x The other end of (C) and the capacitance C x Is connected with the other end of the connecting rod; resistor R i One end of (1) resistor R ii One end of the output end of the operational amplifier U1A and the 7 th pin of the multiplier U2 are respectively connected.
7. The third-order memristive chaotic neuron circuit model according to claim 6, wherein: the second signal multiplication operation module comprises a multiplier U3 and a multiplier U4, wherein the 1 st pin and the 3 rd pin of the multiplier U3 are connected with the output end of the operational amplifier U1B, the 2 nd pin, the 4 th pin and the 6 th pin are grounded, and the 7 th pin is connected with the 3 rd pin of the multiplier U4; the 1 st pin of the multiplier U4 is connected with the output end of the operational amplifier U1A, and the 6 th pin is connected with the resistor R w1 One end of (1) resistor R z1 Is connected with one end of the resistor R at the 7 th pin w1 Is connected with the other end of the connecting rod.
8. The method for establishing the third-order memristor chaotic neuron circuit is characterized by comprising the following steps of:
step 1: establishing a mathematical model of the flow control type local active memristor;
step 2: establishing a second-order memristor neuron circuit model;
obtaining the frequency response of a small signal impedance function of the flow control type local active memristor at a local active working point Q by using a small signal analysis method; constructing a second-order memristor neuron circuit model by connecting a parameter with a proper capacitance value in parallel;
step 3: constructing a third-order memristor chaotic neuron circuit model;
and connecting the current control type local active memristor with a capacitor in parallel and then connecting the current control type local active memristor with an inductor L in series to obtain the third-order chaotic neuron circuit based on the current control type local active memristor.
9. The method for establishing the third-order memristive chaotic neuron circuit according to claim 8, which is characterized by comprising the following steps: the step 1 specifically comprises the following steps:
(1) Establishing a mathematical model of the universal current control type memristor according to a Chua's expansion formula of the memristor model
(2) Simplifying a memristor state equation in a mathematical model of the universal current control type memristor, and representing the state change rate of the memristor through a parameter k;
(3) In order to meet the overall passive characteristic of an actual local active memristor, the relationship between the direct-current voltage and the current of the memristor is given to enable the direct-current voltage-current curve of the memristor to present S-shaped negative differential resistance characteristics, namely the condition of the local active memristor is met, and a mathematical model of the current control type local active memristor is given:
wherein d is 2 ,d 0 ,k,β 2 And beta 1 The set of constants, being constants, satisfies the negative differential resistance characteristic, while the memristor operates in the voltage region with the ability to amplify small signals, rendering the memristor circuit complex.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311229469.8A CN117273103A (en) | 2023-09-22 | 2023-09-22 | Third-order memristor chaotic neuron circuit model and establishment method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311229469.8A CN117273103A (en) | 2023-09-22 | 2023-09-22 | Third-order memristor chaotic neuron circuit model and establishment method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117273103A true CN117273103A (en) | 2023-12-22 |
Family
ID=89213796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311229469.8A Pending CN117273103A (en) | 2023-09-22 | 2023-09-22 | Third-order memristor chaotic neuron circuit model and establishment method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117273103A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117540676A (en) * | 2024-01-09 | 2024-02-09 | 山东科技大学 | Equivalent simulation circuit of spike neuron model based on active memristor |
-
2023
- 2023-09-22 CN CN202311229469.8A patent/CN117273103A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117540676A (en) * | 2024-01-09 | 2024-02-09 | 山东科技大学 | Equivalent simulation circuit of spike neuron model based on active memristor |
| CN117540676B (en) * | 2024-01-09 | 2024-04-16 | 山东科技大学 | Equivalent simulation circuit of spike neuron model based on active memristor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Ma et al. | A novel simple chaotic circuit based on memristor–memcapacitor | |
| CN117273103A (en) | Third-order memristor chaotic neuron circuit model and establishment method | |
| Deng et al. | Bifurcation and bursting oscillations in 2D non-autonomous discrete memristor-based hyperchaotic map | |
| Yadav et al. | Novel memristor emulators using fully balanced VDBA and grounded capacitor | |
| CN107016200A (en) | A kind of circuit design method of the smooth cell neural network based on magnetic control memristor | |
| CN109254528A (en) | The fast wisdom PID control method of one kind three | |
| CN110222451B (en) | Third-order absolute value local active memristor circuit model | |
| Wang et al. | A behavioral spice model of a binarized memristor for digital logic implementation | |
| Singh et al. | New meminductor emulators using single operational amplifier and their application | |
| Di Marco et al. | Unfolding nonlinear dynamics in analogue systems with mem-elements | |
| Ersoy et al. | Electronically charge-controlled tunable meminductor emulator circuit with OTAs and its applications | |
| Bhardwaj et al. | VDTA and DO-CCII based incremental/decremental floating memductance/meminductance simulator: A novel realization | |
| CN110896347A (en) | Multi-stability chaotic system with discrete bifurcation graph | |
| CN111079365A (en) | Arc tangent trigonometric function memristor circuit model | |
| CN110598371A (en) | Three-value local active memristor simulator | |
| Dong et al. | Complex dynamics of a bi-directional N-type locally-active memristor | |
| CN107017979A (en) | A kind of Generation of Chaotic Signals based on broad sense memristor simulator | |
| Jain et al. | A New Electronically Tunable Current Differencing Transconductance Amplifier Based Meminductor Emulator and its Application: CDTA BASED AMPLIFIER BASED MEMINDUCTOR EMULATOR | |
| Lin et al. | Turing instability and pattern formation of a fractional Hopfield reaction–diffusion neural network with transmission delay | |
| CN109670221B (en) | Cubic nonlinear magnetic control memristor circuit composed of fractional order capacitors | |
| Wyffels et al. | Band-pass reservoir computing | |
| CN110289944B (en) | Sallen-Key HPF circuit based on diode bridge memristor | |
| CN110032830B (en) | Three-time nonlinear magnetic control memristor simulator based on current transmitter | |
| CN108257628A (en) | A kind of lattice scale fractional order memristor of arbitrary order high-pass filtering | |
| Zhu et al. | Memristor-based neural network PID controller for buck converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |