CN117273103A - A third-order memristive chaotic neuron circuit model and its establishment method - Google Patents
A third-order memristive chaotic neuron circuit model and its establishment method Download PDFInfo
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Abstract
Description
技术领域Technical field
本发明涉及神经元电路设计领域，特别涉及一种由流控型局部有源忆阻器构成的三阶混沌神经元电路模型及其建立方法。The invention relates to the field of neuron circuit design, and in particular to a third-order chaotic neuron circuit model composed of a flow-controlled local active memristor and a method of establishing the same.
背景技术Background technique
由于存算分离的冯诺依曼计算架构已无法满足爆发式增长的数据量的需求，现有的计算系统在计算速度、集成度和能耗方面都存在局限性，亟需突破传统框架，寻求新的体系结构来解决实际应用问题。而神经形态计算架构以其高计算能效、很强的鲁棒性和容错性，成为目前智能计算领域研究的热点。Since the von Neumann computing architecture that separates storage and computing can no longer meet the demand for explosive growth in data volume, existing computing systems have limitations in computing speed, integration, and energy consumption. There is an urgent need to break through the traditional framework and seek New architecture to solve practical application problems. Neuromorphic computing architecture has become a hot research topic in the field of intelligent computing due to its high computing energy efficiency, strong robustness and fault tolerance.
神经形态架构的基本单元是神经元和突触，因神经元神经形态的复杂非线性特征，关于神经元的建模及应用研究仍是较为有挑战性的一项工作。近几年研究发现，局部有源忆阻器因其特有的局部有源特征，非常适合用于构建神经元模型。The basic units of neuromorphic architecture are neurons and synapses. Due to the complex nonlinear characteristics of neuron neuromorphology, modeling and application research on neurons is still a relatively challenging task. In recent years, research has found that local active memristors are very suitable for building neuron models because of their unique local active characteristics.
目前已制备的纳米尺度的局部有源忆阻器有NbO2、VO2和TaO忆阻器，其皆为流控型局部有源忆阻器，在神经元建模方面具有巨大的潜力，但其局限性在于，基于实际材料的忆阻器建立的神经元模型较为复杂而难于分析，且性能不稳定。因此，需建立一种简单有效的且能模拟关键的局部有源特性的忆阻器模型，进一步构建能重现人脑中复杂的混沌现象的混沌神经元电路结构。The nanoscale local active memristors that have been prepared so far include NbO 2 , VO 2 and TaO memristors. They are all fluidic local active memristors and have great potential in neuron modeling. However, Its limitation is that neuron models based on memristors based on actual materials are complex and difficult to analyze, and their performance is unstable. Therefore, it is necessary to establish a simple and effective memristor model that can simulate key local active characteristics, and further construct a chaotic neuron circuit structure that can reproduce the complex chaotic phenomena in the human brain.
发明内容Contents of the invention
本发明提出了一种流控型局部有源忆阻器仿真器模型，基于该模型建立了三阶忆阻混沌神经元电路。The present invention proposes a flow-controlled local active memristor simulator model, and establishes a third-order memristive chaotic neuron circuit based on the model.
本发明的第一方面提供了一种三阶忆阻混沌神经元电路模型，包括流控型局部有源忆阻器、电容、电感、电阻和电压源；局部有源忆阻器的一端接地，另一端接电感的一端，也是神经元输出端口；电感的另一端接电阻的一端和电容的一端；电容的另一端接地；电阻的另一端接激励电压源；The first aspect of the present invention provides a third-order memristor chaotic neuron circuit model, including a flow-controlled local active memristor, a capacitor, an inductor, a resistor and a voltage source; one end of the local active memristor is grounded, The other end is connected to one end of the inductor, which is also the neuron output port; the other end of the inductor is connected to one end of the resistor and one end of the capacitor; the other end of the capacitor is connected to ground; the other end of the resistor is connected to the excitation voltage source;
所述流控型局部有源忆阻器的数学模型为：The mathematical model of the fluidic local active memristor is:
其中i,v,x分别为流经忆阻器的电流、忆阻器两端的电压和忆阻器的状态变量，RM为忆阻函数，c2,d2,a2,h2和b2都是常数，满足流控型局部有源忆阻器的直流电压-电流曲线表现S型负微分电阻特性。where i, v, x are the current flowing through the memristor, the voltage across the memristor and the state variable of the memristor respectively, R M is the memristor function, c 2 , d 2 , a 2 , h 2 and b 2 are both constants, which satisfies the DC voltage-current curve of the current-controlled local active memristor to exhibit S-type negative differential resistance characteristics.
本发明的第二方面提供了一种三阶忆阻混沌神经元电路的建立方法，包括以下步骤：A second aspect of the present invention provides a method for establishing a third-order memristive chaotic neuron circuit, which includes the following steps:
步骤1：建立流控型局部有源忆阻器数学模型；Step 1: Establish a mathematical model of a fluidic local active memristor;
步骤2：建立二阶忆阻神经元电路模型；Step 2: Establish a second-order memristive neuron circuit model;
利用小信号分析法，得到流控型局部有源忆阻器在局部有源工作点Q处的小信号阻抗函数的频率响应；通过并联一个具有合适电容值的参数构建二阶忆阻神经元电路模型；Using the small signal analysis method, the frequency response of the small signal impedance function of the flow-controlled local active memristor at the local active operating point Q is obtained; a second-order memristive neuron circuit is constructed by connecting a parameter with an appropriate capacitance value in parallel. Model;
步骤3：构建三阶忆阻混沌神经元电路模型；Step 3: Construct a third-order memristive chaotic neuron circuit model;
将流控型局部有源忆阻器与电容并联后再与电感L串联，获得基于流控型局部有源忆阻器的三阶混沌神经元电路。By connecting the flow-controlled local active memristor in parallel with the capacitor and then in series with the inductor L, a third-order chaotic neuron circuit based on the flow-controlled local active memristor is obtained.
本发明的有益效果：本发明提出了一种结构简单且有效的三阶忆阻混沌神经元电路，该电路仅包含一个流控型局部有源忆阻器、一个电容、一个电感、一个电阻和一个激励电压信号；该流控型局部忆阻器可模拟现有的纳米局部有源忆阻器的复杂非线性和局部有源特征。Beneficial effects of the present invention: The present invention proposes a third-order memristive chaotic neuron circuit with a simple and effective structure. The circuit only includes a flow-controlled local active memristor, a capacitor, an inductor, a resistor and An excitation voltage signal; the flow-controlled local memristor can simulate the complex nonlinear and local active characteristics of existing nano-local active memristors.
与现有神经元电路相比，该神经元电路具有结构简单、实现简便、神经形态行为丰富等优势，可利用其作为神经形态计算架构单元以构建类脑神经网络实现高效计算。Compared with existing neuron circuits, this neuron circuit has the advantages of simple structure, easy implementation, and rich neuromorphic behaviors. It can be used as a neuromorphic computing architecture unit to build brain-like neural networks to achieve efficient computing.
附图说明Description of the drawings
图1为基于流控型局部有源忆阻器的混沌神经元电路原理图；Figure 1 is a schematic diagram of a chaotic neuron circuit based on a fluidic local active memristor;
图2为流控型局部有源忆阻器的小信号等效电路；Figure 2 shows the small-signal equivalent circuit of a flow-controlled local active memristor;
图3为神经元电路的神经形态及其参数区域分布图；Figure 3 shows the neuromorphology of neuron circuits and their parameter regional distribution diagram;
图4为三阶忆阻混沌神经元电路模型的模拟电路。Figure 4 shows the simulation circuit of the third-order memristive chaotic neuron circuit model.
具体实施方式Detailed ways
下面结合附图对本发明作进一步的描述：The present invention will be further described below in conjunction with the accompanying drawings:
如图1所示，本申请实施例公开了一种三阶忆阻混沌神经元电路模型，它由一个流控型局部有源忆阻器LAM、一个电容C、一个电感L、一个电阻R和一个激励电压源组成。局部有源忆阻器LAM的一端接地，另一端接电感L的一端，也是神经元输出端口；电感L的另一端接电阻R的一端和电容C的一端连接；电容C的另一端接地；电阻R的另一端接激励电压源。As shown in Figure 1, the embodiment of the present application discloses a third-order memristive chaotic neuron circuit model, which consists of a flow-controlled local active memristor LAM, a capacitor C, an inductor L, a resistor R and consists of an excitation voltage source. One end of the local active memristor LAM is connected to ground, and the other end is connected to one end of the inductor L, which is also the neuron output port; the other end of the inductor L is connected to one end of the resistor R and one end of the capacitor C; the other end of the capacitor C is connected to the ground; the resistor The other end of R is connected to the excitation voltage source.
依据上述实施例所提供的模型，本申请还公开了一种三阶忆阻混沌神经元电路的建立过程包括以下步骤：Based on the model provided by the above embodiments, this application also discloses that the establishment process of a third-order memristive chaotic neuron circuit includes the following steps:
步骤1：流控型局部有源忆阻器数学模型的建立。Step 1: Establishment of mathematical model of fluidic local active memristor.
(1)根据忆阻器模型的蔡氏展开公式，通用型电流控制型忆阻器的数学模型为：(1) According to Chua’s expansion formula of the memristor model, the mathematical model of the universal current-controlled memristor is:
其中i和v分别表示流经忆阻器的电流和忆阻器两端的电压；RM(x)为忆阻函数；f(x,i)是关于忆阻器状态变量x和电流i的函数，a、β、d、δ构成的参数组可用于拟合具有不同特性的忆阻器。where i and v represent the current flowing through the memristor and the voltage across the memristor respectively; R M (x) is the memristor function; f (x, i) is a function of the memristor state variable x and current i , the parameter group consisting of a, β, d, and δ can be used to fit memristors with different characteristics.
(2)令n＝1，m＝2，p＝q＝0，a0＝β0＝0，a1＝1，以此设计简单的忆阻器状态方程为(2) Let n=1, m=2, p=q=0, a 0 =β 0 =0, a 1 =1, and design a simple memristor state equation as
其中，方程中设置参数k表征忆阻器的状态变化率，通过控制该参数可控制忆阻器的工作频率范围。Among them, the parameter k set in the equation represents the state change rate of the memristor. By controlling this parameter, the operating frequency range of the memristor can be controlled.
(3)令式(3)中dx/dt＝0，v＝V，可得(3) Let dx/dt=0, v=V in equation (3), we can get
X＝-β1I-β2I2 (4)X＝-β 1 I-β 2 I 2 (4)
(4)为了满足实际局部有源忆阻器的整体无源特性，即RM(x)>0，在此，令r＝1，则忆阻器的直流电压和电流关系可描述为：(4) In order to satisfy the overall passive characteristics of the actual local active memristor, that is, R M (x)>0, here, let r=1, then the relationship between the DC voltage and current of the memristor can be described as:
V＝RM(X)I＝(d0+d2(-β1I-β2I2)2)I (5)V＝R M (X)I＝(d 0 +d 2 (-β 1 I-β 2 I 2 ) 2 )I (5)
要使忆阻器的DC V-I曲线呈现S型负微分电阻特性，即满足局部有源忆阻器的条件，则需满足式(5)中dV/dI<0，据此提出一个简单的流控型局部有源忆阻器的数学模型为In order for the DC V-I curve of the memristor to exhibit S-shaped negative differential resistance characteristics, that is, to meet the conditions of a local active memristor, it is necessary to satisfy dV/dI<0 in equation (5). Based on this, a simple flow control method is proposed The mathematical model of type local active memristor is
其中d2＝2,d0＝20,k＝-1×10-3,β2＝-2.8×10-3,β1＝1000。该组参数可满足其DCV-I曲线上表现负微分电阻特性，而忆阻器工作在该电压区域，具有放大小信号的能力，使忆阻电路呈现复杂特性。Among them, d 2 =2, d 0 =20, k =-1×10 -3 , β 2 =-2.8×10 -3 , β 1 =1000. This set of parameters can satisfy the negative differential resistance characteristics shown on its DCV-I curve, and the memristor operates in this voltage region and has the ability to amplify small signals, making the memristor circuit exhibit complex characteristics.
步骤2：二阶忆阻神经元电路模型的建立。Step 2: Establishment of second-order memristive neuron circuit model.
利用小信号分析法，可得到该流控型局部有源忆阻器在局部有源工作点Q处的小信号阻抗函数的频率响应为：Using the small signal analysis method, the frequency response of the small signal impedance function of the flow-controlled local active memristor at the local active operating point Q can be obtained as:
其中a1＝1,a0＝-k,b1＝d2X2+d0,b0＝2d2XI(2kβ2I+kβ1)-k(d2X2+d0)。Among them, a 1 =1, a 0 =-k, b 1 =d 2 X 2 +d 0 , b 0 =2d 2 XI(2kβ 2 I+kβ 1 )-k(d 2 X 2 +d 0 ).
该流控型局部有源忆阻器的小信号等效电路如图2所示。因此，需并联一个具有合适电容值的参数可构建二阶神经元模型，而其等效电容值需满足C≥-Im[Z(iω,Q)]/ω。The small-signal equivalent circuit of the flow-controlled local active memristor is shown in Figure 2. Therefore, a second-order neuron model needs to be constructed by connecting a parameter with a suitable capacitance value in parallel, and its equivalent capacitance value needs to satisfy C≥-Im[Z(iω,Q)]/ω.
步骤3：三阶忆阻混沌神经元电路模型的构建。Step 3: Construction of third-order memristive chaotic neuron circuit model.
将流控型局部有源忆阻器与电容并联后再与电感L串联，就能构建基于流控型局部有源忆阻器的三阶混沌神经元电路，电路原理图如附图1所示。依据基尔霍夫定律，可得电路状态方程为：By connecting the flow-controlled local active memristor in parallel with the capacitor and then in series with the inductor L, a third-order chaotic neuron circuit based on the flow-controlled local active memristor can be constructed. The circuit schematic is shown in Figure 1 . According to Kirchhoff's law, the circuit state equation can be obtained as:
其中，x、vC、iL分别表示忆阻器的状态变量、忆阻器两端电压和流过电感的电流。Among them, x, v C and i L respectively represent the state variables of the memristor, the voltage across the memristor and the current flowing through the inductor.
为展示该忆阻神经元电路随激励电压VD和电容C变化的神经形态特性，绘制了L＝30mH时VD-C参数平面上的动力学地图及相应位置处的多种神经形态行为，如图3所示。动力学地图中的黄色区域是一个稳定参数域，电路工作在该区域内一般只产生衰减振荡，即静息电位；黄色区域之外的蓝色和绿色区域为不稳定的局部有源域，工作在该区域的电路可产生包括周期尖峰及混沌在内的神经形态行为，其中，绿色区域为神经元产生周期尖峰的参数域，而蓝色区域为神经元产生混沌形态的参数域，而黄色区域和绿色区域的分界线是Hopf分岔线。In order to demonstrate the neuromorphic characteristics of this memristive neuron circuit as the excitation voltage V D and capacitance C change, the dynamics map on the V D -C parameter plane at L = 30mH and various neuromorphic behaviors at the corresponding positions were drawn. As shown in Figure 3. The yellow area in the dynamics map is a stable parameter domain. The circuit operation in this area generally only produces attenuated oscillation, that is, the resting potential; the blue and green areas outside the yellow area are unstable local active domains. Circuits in this area can produce neuromorphic behaviors including periodic spikes and chaos. The green area is the parameter domain where neurons produce periodic spikes, the blue area is the parameter domain where neurons produce chaotic shapes, and the yellow area The dividing line with the green area is the Hopf bifurcation line.
因此，基于该流控型局部有源忆阻器的三阶神经元电路可产生丰富的包含混沌在内的复杂神经形态行为。Therefore, third-order neuron circuits based on this fluidic local active memristor can produce rich complex neuromorphic behaviors including chaos.
该三阶忆阻混沌神经元电路模型的原理图如图4所示。框线内为设计的流控型局部有源忆阻器的仿真器电路，该电路包括运算放大器电路(U1A和U1B，四通道TL084)、乘法器电路(U2、U3和U4，AD633)和适量电阻、电容，运算放大器电路进行比例加法和积分运算，乘法器电路用来实现乘法运算。集成运算放大器U1A、U1B采用四通道TL084芯片，乘法器U2、U3、U4采用AD633芯片，其中集成运算放大器TL084和乘法器AD633均为现有成熟技术。The schematic diagram of the third-order memristive chaotic neuron circuit model is shown in Figure 4. Inside the box is the designed simulator circuit of the flow-controlled local active memristor. The circuit includes the operational amplifier circuit (U1A and U1B, four-channel TL084), the multiplier circuit (U2, U3 and U4, AD633) and appropriate Resistors, capacitors, and operational amplifier circuits perform proportional addition and integral operations, and multiplier circuits are used to implement multiplication operations. The integrated operational amplifiers U1A and U1B use the four-channel TL084 chip, and the multipliers U2, U3, and U4 use the AD633 chip. The integrated operational amplifier TL084 and the multiplier AD633 are both existing mature technologies.
如图4所示，第①部分为加法运算模块，该模块中运算放大器U1A与外围电阻R1、R2、R3、R4实现比例加法运算，当R1+R2＝R3+R4时，输出端电压vi的值与电流i成正比，R0为采样电阻，该部分输出端电压vi为：As shown in Figure 4, part ① is the addition module. In this module, the operational amplifier U1A and the peripheral resistors R 1 , R 2 , R 3 , and R 4 implement proportional addition operations. When R 1 + R 2 = R 3 + R 4 , the value of the output voltage vi is proportional to the current i, R 0 is the sampling resistor, and the output voltage vi of this part is:
v＝vM+R0i (10)v＝v M +R 0 i (10)
所述的运算放大器U1A的第1引脚与电阻R4的一端、乘法器U2的第1引脚和第4引脚、电阻Ri的一端、乘法器U4的第1引脚连接，第2引脚与电阻R3的一端、电阻R4的另一端连接，第3引脚与电阻R1的一端、电阻R2的一端连接，第4引脚连接电源VCC，第11引脚连接电源VEE。The first pin of the operational amplifier U1A is connected to one end of the resistor R 4 , the first and fourth pins of the multiplier U2, one end of the resistor R i , and the first pin of the multiplier U4, and the second The pin is connected to one end of resistor R 3 and the other end of resistor R 4 , the 3rd pin is connected to one end of resistor R 1 and one end of resistor R 2 , the 4th pin is connected to the power supply VCC, and the 11th pin is connected to the power supply VEE. .
第②部分为第一信号相乘运算模块，该模块通过乘法器U2来实现输入信号相乘的运算，在其输出端w可获得输出电压vii为Part ② is the first signal multiplication operation module. This module realizes the operation of multiplying the input signals through the multiplier U2. The output voltage v ii can be obtained at its output terminal w as
所述的乘法器U2的第1引脚和第4引脚与运算放大器U1A的第1引脚连接，第2引脚和第3引脚接地，第6引脚与电阻Rw的一端、电阻Rz的一端连接，第7引脚与电阻Rw的另一端、电阻Rii的一端连接，第5引脚连接电源VEE，第8引脚连接电源VCC。The first and fourth pins of the multiplier U2 are connected to the first pin of the operational amplifier U1A, the second and third pins are connected to ground, and the sixth pin is connected to one end of the resistor R w and the resistor R w One end of R z is connected, pin 7 is connected to the other end of resistor R w and one end of resistor R ii , pin 5 is connected to power supply VEE, and pin 8 is connected to power supply VCC.
第③部分为状态变量求解模块，该模块实现状态变量x的求解，输出端为vx；Part ③ is the state variable solution module, which implements the solution of the state variable x, and the output terminal is v x ;
第③部分通过电阻、电容和运算放大器U1B来实现积分运算，其中运算放大器U1B与外围电阻Ri、Rii、Rx和电容Cx构成积分电路，获得输出电压vx为Part ③ realizes the integral operation through resistors, capacitors and operational amplifier U1B. The operational amplifier U1B, peripheral resistors R i , R ii , R x and capacitor C x form an integral circuit, and the output voltage v x is obtained as
所述的运算放大器U1B的第5引脚接地，第6引脚与电阻Ri的另一端、电阻Rii的另一端、电阻Rx的一端、电容Cx的一端连接，第7引脚与电阻Rx的另一端、电容Cx的另一端、乘法器U3的第1引脚和第3引脚连接。The 5th pin of the operational amplifier U1B is connected to ground, the 6th pin is connected to the other end of the resistor R i , the other end of the resistor R ii , one end of the resistor R x , and one end of the capacitor C x , and the 7th pin is connected to The other end of the resistor R x , the other end of the capacitor C x , and the first and third pins of the multiplier U3 are connected.
第④部分为第二信号相乘运算模块，该模块通过两个乘法器U3和U4来实现输入信号相乘的运算，其中乘法器U3用于实现运算放大器U1B的输出电压vx的比例平方运算，可以获得输出电压0.1vx 2；乘法器U4用于实现乘法器U3的输出电压0.1vx 2与vi的比例乘法运算，可以获得输出电压vM为Part ④ is the second signal multiplication operation module. This module realizes the operation of multiplying the input signals through two multipliers U3 and U4. The multiplier U3 is used to realize the proportional square operation of the output voltage v x of the operational amplifier U1B. , the output voltage 0.1v x 2 can be obtained; the multiplier U4 is used to realize the proportional multiplication operation of the output voltage 0.1v x 2 of the multiplier U3 and vi , and the output voltage v
所述的乘法器U3的第1引脚和第3引脚与运算放大器U1B的第7引脚连接，第2引脚、第4引脚、第6引脚接地，第7引脚与乘法器U4的第3引脚连接，第5引脚连接电源VEE，第8引脚连接电源VCC；乘法器U4的第1引脚与运算放大器U1A的第1引脚连接，第3引脚与乘法器U3的第7引脚连接，第2引脚和第4引脚接地，第6引脚与电阻Rw1的一端、电阻Rz1的一端连接，第7引脚与电阻Rw1的另一端连接，第5引脚连接电源VEE，第8引脚连接电源VCC。The 1st pin and 3rd pin of the multiplier U3 are connected to the 7th pin of the operational amplifier U1B, the 2nd pin, the 4th pin, and the 6th pin are connected to ground, and the 7th pin is connected to the multiplier U1B. The 3rd pin of U4 is connected, the 5th pin is connected to the power supply VEE, and the 8th pin is connected to the power supply VCC; the 1st pin of the multiplier U4 is connected to the 1st pin of the operational amplifier U1A, and the 3rd pin is connected to the multiplier The 7th pin of U3 is connected, the 2nd and 4th pins are connected to ground, the 6th pin is connected to one end of the resistor R w1 and one end of the resistor R z1 , and the 7th pin is connected to the other end of the resistor R w1 . Pin 5 is connected to the power supply VEE, and pin 8 is connected to the power supply VCC.
因此，可推导得：Therefore, it can be derived:
该三阶忆阻混沌神经元电路的参数设计如表1所示。The parameter design of the third-order memristive chaotic neuron circuit is shown in Table 1.
表1三阶忆阻混沌神经元电路参数设计Table 1 Parameter design of third-order memristive chaotic neuron circuit
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