CN214475007U - General simulator for memory element - Google Patents

General simulator for memory element Download PDF

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CN214475007U
CN214475007U CN202120413252.2U CN202120413252U CN214475007U CN 214475007 U CN214475007 U CN 214475007U CN 202120413252 U CN202120413252 U CN 202120413252U CN 214475007 U CN214475007 U CN 214475007U
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current feedback
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feedback operational
current
memory interface
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郑辞晏
庄楚源
李亚
练明坚
颜坤哲
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Guangdong Polytechnic Normal University
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Abstract

The utility model provides a memory element general simulator, current feedback operational amplifier U1Respectively connected with a current feedback operational amplifier U3And as input A, a current feedback operational amplifier U2First transformation memory interface T as series resistance or inductance1Positive and negative terminals of the current feedback operational amplifier U2Respectively connected with a current feedback operational amplifier U4And as input B, a current feedback operational amplifier U2And multiplier U5Connected, multiplier U5Both ends are grounded after being connected together, and a multiplier U5And current feedback operational amplificationDevice U3Connecting, current feedback operational amplifier U3Open-circuit, current-fed operational amplifier U3Current feedback operational amplifier U4Second transformation memory interface T as series-connected resistor or capacitor2Positive and negative terminals of the current feedback operational amplifier U4The two ends of the grounding wire are respectively open-circuited and grounded. The memristor, the memory container and the memory sensor which are conveniently simulated are put into industrial production.

Description

General simulator for memory element
Technical Field
The utility model relates to a construct memory element's technical field, mainly relate to a memory element general simulator.
Background
In 1971, the Chua begonia team studied the current i, voltage V, charge q and magnetic flux
Figure BDA0002952038260000011
The relationship between them to predict a fourth basic circuit element, called memristor, that exists in addition to the resistance, capacitance, inductance, representing the charge q and the magnetic flux
Figure BDA0002952038260000012
The mathematical relationship of (a).
In 2008, Hewlett packard laboratories successfully fabricated nanoscale solid-state devices with memristor characteristics. From this, the historical position of the memristor as the fourth basic circuit element was determined. Due to the unique memory characteristic and the nanostructure of the memristor, the memristor has wide application prospects in the fields of nonvolatile storage, artificial intelligence (including brain-like operation and neural networks), chaotic circuits, logic chips and the like. In 2009, the zeita begonia team further proposed the concept of a memristor and a memcapacitor, and the characteristics of the memcapacitor and the meminductor both show the memory function as the same as the memristor. Thus, memristors, memcapacitors, and memristors are also collectively referred to as memory elements. However, compared with a memristor, the memristor and the memristor exist as a novel generalized energy storage element. Unlike memristors, in some low-power integrated circuits, the memcapacitor and the meminductor do not need to consume energy when operating. Therefore, it is reasonable to believe that memcapacitors and meminductors can have more applications in the field of electronic circuits.
However, due to development costs and the technical difficulties in fabricating nanoscale devices, commercial-scale memory elements cannot be overcome in a short time. Therefore, in order to explore the subsequent application of the three memory elements, it is necessary to research the simulation model and the equivalent circuit simulator.
And in the patent numbers: CN201610580825, patent name: a method for simulating the use of a memristor, a memcapacitor and a meminductor respectively by using five current feedback operational amplifiers and a field effect transistor is disclosed in a patent document (the following patent document A), because the patent document A can realize the simulation of the memory characteristics of the memristor, the memcapacitor and the meminductor by depending on the field effect transistor working in a linear region, the memristor, the memcapacitor and the meminductor simulated by the method of the patent document A can only be used in a circuit with the frequency of 0.8kHZ, but the frequency of the existing circuit is far beyond 0.8kHZ, so that the general memory device simulator obtained in the patent document A can not meet the actual circuit working requirements and can not be really used in a conventional circuit, the general memory device simulator in the patent document A can not be put into the conventional production, and the simulated memristor the memcapacitor and the meminductor can not be really put into the conventional production, The memory container and the memory inductor are put into industrial production.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a hardware architecture of general simulator of memory element, this hardware architecture carry out software programming back to controller wherein at software engineer for the simulation is recalled and is hindered the ware, is recalled the container and is recalled the inductor and can be with imitating that recall that the ware is hindered the ware, is recalled the container and is recalled the inductor and use in frequency is the circuit of 100kHZ magnitude of a magnitude in a flexible way, be convenient for imitate out recall hinder the ware, recall the container and recall and feel in the middle of the industrial production is put into to the inductor.
Therefore, the memory element universal simulator comprises a controller, four current feedback operational amplification chips for amplifying signals at high frequency, a multiplier, a power supply, an integrator, a plurality of resistors, a capacitor and an inductor, wherein the four current feedback operational amplifiers are respectively marked as U1、U2、U3、U4Any one of the current feedback operational amplifiersThe big chips are all provided with an x end, a y end, a p end and a z end, and the current feedback operational amplification chip U1The y end of the current transformer is divided into two branches, wherein one branch is connected to a current feedback operational amplification chip U3And the other branch is taken as an input end A, and the current feedback operation is used for amplifying the chip U1The x terminal of the first transformation memory interface T1The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation2The x terminal of the first transformation memory interface T1Negative terminal of, the first transformation memory interface T1The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or an inductor in series, and the current feedback operational amplifier chip U2The y end of the current transformer is connected with a current feedback operational amplification chip U, and two branches are divided4And the other branch is taken as an input end B, and a current feedback operation amplification chip U1The z end is grounded through an integrator, and a current feedback operational amplification chip U1P terminal of and multiplier U5X of1End connection, current feedback operational amplification chip U2The z end is grounded through a resistor, and a current feedback operational amplification chip U2P terminal of and multiplier U5Y of (A) to (B)1End-connected, multiplier U5X of2The end is grounded through a power supply, and a multiplier U5Y of (A) to (B)2The end and the z end are grounded after being connected together, and a multiplier U5W terminal and current feedback operational amplification chip U3The y end of the current feedback operational amplifier chip U is connected with3P end of the p-type amplifier is open-circuited, and the current feedback operation is used for amplifying the chip U3The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation4The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2Negative terminal of, a second transformation memory interface T2The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or a capacitor in series, and the current feedback operational amplifier chip U4P-end open circuit, current feedback operational amplification chip U4The y end of the controller is grounded, the controller is connected with the input end A and the input end B, and the working frequency ranges from 0kHZ to 100 kHZ.
Further, the integrator is a capacitor.
Further, the current flowing from the input terminal a is iABInto the flow ofCurrent feedback operational amplification chip U3Has a current of i at the z-terminal5Flow direction to the first conversion memory interface T1Has a current of i as a negative terminal1From current feedback operational amplification chip U4The current flowing out of the z terminal is i6From current feedback operational amplification chip U1The current flowing out of the z terminal is i2From current feedback operational amplification chip U2The current flowing out of the z terminal is i3From current feedback operational amplification chip U3The x terminal of (a) flows a current of i4。
Further, if the first transformation memory interface T1Positive terminal and first transformation memory interface T1A resistor is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The other resistor is connected in series between the input end A and the input end B, and then the input end A and the input end B are connected with an external circuit to simulate a memristor.
Further, if the first transformation memory interface T1Positive terminal and first transformation memory interface T1A resistor is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The input end A and the input end B are connected with an external circuit to simulate the memcapacitor.
Further, if the first transformation memory interface T1Positive terminal and first transformation memory interface T1An inductance is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The input end A and the input end B are connected with an external circuit to simulate the memory inductor.
Has the advantages that:
the utility model provides a general simulator of memory element, through the series connection back including controller, four current feedback operational amplifier, multiplier, power, integrator, a plurality of resistance, electric capacity, inductance, form two ports that input A and input B are used for being connected with external circuit as general simulator of memory element, at the general simulation of memory element two ports that are connected of memory elementThe device is provided with a first transformation memory interface T1And a second transformation memory interface T2By using the first transformation memory interface T1Medium series resistance or inductance, in the second transformation memory interface T2The hardware structure is used for simulating a memristor, a memristor capacitor and a memristor sensor after software engineers carry out software programming on a controller in the hardware structure, and the simulated memristor, memristor capacitor and memristor sensor can be flexibly used in a circuit with the frequency of 100kHZ magnitude, so that the simulated memristor, memristor capacitor and memristor sensor can be conveniently put into industrial production.
The above description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the present invention is given.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a memory device simulator according to the present invention;
FIG. 2 is a schematic diagram of the structure of the analog memristor of the present invention;
fig. 3 is a schematic structural diagram of the analog memcapacitor of the present invention;
FIG. 4 is a schematic structural diagram of the analog memory sensor of the present invention;
FIG. 5 is a schematic diagram of the operating frequency of the analog memristor of the present invention;
fig. 6 is a schematic view of the working frequency condition of the analog memcapacitor of the present invention;
fig. 7 is the utility model discloses a frequency of operation condition schematic diagram of inductor is recalled in simulation.
Detailed Description
The invention will be further described with reference to the following examples.
Referring to fig. 1, the memory device universal simulator of the present embodiment includes four current feedback operational amplifiers U respectively electrically connected to the controller1Current feedback operational amplifier U2Current feedback operational amplifier U3And current feedback operational amplifier U4A current feedback type current feedback operational amplifier AD844 and a multiplier U5Resistance R1A capacitor C functioning as an integrator1A DC voltage source Vs, a current feedback operational amplifier U1And a branch connected to a current feedback operational amplifier U3The other branch is used as the input end A of the memory element general simulator, and the voltage of the input end A is VAThe current flowing from the input terminal A to the node of the two branches is iABIn-flow current feedback operational amplifier U3Has a current of i at the z-terminal5Feeding back the operational amplifier U with current1The x terminal of the first transformation memory interface T1With a current feedback operational amplifier U2The x terminal of the first transformation memory interface T1Negative terminal of, the first transformation memory interface T1Positive terminal and first transformation memory interface T1The negative terminal of the first conversion memory interface T can be connected with a resistor or an inductor in series1Positive end of the current feedback operational amplifier U2The x terminal of (b) has a current of i1Current feedback operational amplifier U2And a branch connected to a current feedback operational amplifier U4And the other branch is used as the input end B of the memory element general simulator, and the operational amplifier U is fed back from the current4The current flowing out of the z terminal is i6Current feedback operational amplifier U1Z terminal of (C)1Back grounded, slave current feedback operational amplifier U1The current flowing out of the z terminal is i2Current feedback operational amplifier U1P terminal of and multiplier U5X of1Terminal connection, currentFeedback operational amplifier U2Z terminal series resistance R1Back grounded, slave current feedback operational amplifier U2The current flowing out of the z terminal is i3Current feedback operational amplifier U2P terminal of and multiplier U5Y of (A) to (B)1End-connected, multiplier U5X of1End-series direct current source VsRear grounded, multiplier U5Y of (A) to (B)2Terminals are connected to the z terminal and grounded, and a multiplier U5W terminal and current feedback operational amplifier U3Is connected to a slave current feedback operational amplifier U3The y terminal of (a) flows a current of i4Current feedback operational amplifier U3The p end of the operational amplifier U is open-circuited and fed back by current3The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2With a current feedback operational amplifier U4The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2Negative terminal of, a second transformation memory interface T2Positive terminal and second transformation memory interface T2The negative end of the operational amplifier can be connected with a resistor or a capacitor in series, and the current is fed back to the operational amplifier U4P-terminal open-circuit, current feedback operational amplifier U4The y-terminal of (1) is grounded. Current feedback operational amplifier U1The x, y, p and z terminals of the voltage source respectively correspond to the voltage V1x、V1y、V1p、V1zCurrent feedback operational amplifier U2The x, y, p and z terminals of the voltage source respectively correspond to the voltage V2x、V2y、V2p、V2zCurrent feedback operational amplifier U3The x, y, p and z terminals of the voltage source respectively correspond to the voltage V3x、V3y、V3p、V3zCurrent feedback operational amplifier U4The x, y, p and z terminals of the voltage source respectively correspond to the voltage V4x、V4y、V4p、V4z。
The input end A and the input end B are used as external ports of the universal interface circuit, so that the memory element universal simulator can be connected and communicated with external equipment. By using the first transformation memory interface T1Positive and negative end, second conversion memory interface T2The positive and negative terminals are respectively connected in series with a resistor, a capacitor or an inductor to change the state variable relationship inside the memory element universal simulator,therefore, the characteristics of the memory element universal simulator for simulating the memristor, the memory container and the memory sensor are realized, and the memory element universal simulator is flexibly connected with an external circuit through the input end A and the input end B for use, so that the effect of simulating the use of the memristor, the memory container and the memory sensor by hardware is achieved.
The current feedback operational amplifier AD844 is a current feedback type current feedback operational amplifier, plays the role of a current transmitter and a voltage follower in a memory element universal simulator, and based on the characteristics of the AD844 current feedback operational amplifier, an x end is an inverted input end, a y end is a same-direction input end, a p end and a z end are output ends, and V isp＝Vz，Vy＝Vx，ip＝iz，iy＝ixSince the z terminal has a weak ability to drive the load, the p terminal is usually connected to the external load. Multiplier U5For the two-input multiplier AD633 chip, its input terminal x is recorded1、x2、y1、y2And z have a voltage (or potential) value of Vx1、Vx2、Vy1、Vy2And VzThe voltage (or potential) value of the output end w is marked as VwBased on AD633 multiplier U5Of which is
Figure BDA0002952038260000051
Capacitor C1The memory device universal simulator of the present embodiment functions as an integrator, and equivalently, integrates the input voltage.
The memory element comprises a memristor, a memory container and a memory inductor which respectively correspond to different constitutive relations, and the constitutive relation of the memristor is
Figure BDA0002952038260000052
The constitutive relation of the nonlinear relation and the memcapacitor is
Figure BDA0002952038260000053
The nonlinear relation and the constitutive relation of the memory sensor are q-rho nonlinear relations. Wherein q represents the amount of charge,
Figure BDA0002952038260000054
is the magnetic flux, i.e. the integral of voltage over time, σ is the integral of q over time, ρ is
Figure BDA0002952038260000055
Integration over time.
The following embodiments all propose corresponding memory element simulators based on the constitutive relation of memristors, memristors and memristors, and memristors. Namely, only the first transformation memory interface T is changed under the condition of ensuring that the circuit topology structure of the simulator is not changed1Positive and negative end, second conversion memory interface T2The positive end and the negative end of the memory cell are respectively connected with a resistor, a capacitor or an inductor in series, so that the simulator can be respectively converted into a memristor, a memory capacitor and a memory inductor. For example, memristors, converting state variables inside a memory element simulator into magnetic flux by changing the properties of an access element
Figure BDA0002952038260000056
And a charge q, and the relationship between them can be characterized by a quadratic non-linear function. For the memcapacitor and the meminductor, the constitutive relation of the memcapacitor and the meminductor can be characterized through a quadratic nonlinear function. Thereby, the relationship between the internal state variables of the memory simulator is characterized in the form of a quadratic non-linear function.
Example 1
For memristors, internal state variables of the simulator
Figure BDA0002952038260000057
Relationship (D) and memory conductance value Wm(the reciprocal of memristance, like conductance) can be defined as:
Figure BDA0002952038260000058
Figure BDA0002952038260000059
wherein alpha is1Represents WmSlope of change of beta1Represents WmIs started.
Referring to fig. 2, under the condition that an excitation voltage is applied between a and B, the matched setting of various parameters in the memory element general simulator of the embodiment is completed by the following method to simulate the use of a memristor:
will resistance R2Connected in series to the first transformation memory interface T1Between the positive and negative terminals, a resistance R3Connected in series to the second transformation memory interface T2Between the positive and negative terminals, the voltage following characteristic of the current feedback operational amplifier AD844 can be obtained:
V1x＝VA，V2x＝VB；
obtaining the flow through the first transformation memory interface T1Current i between positive and negative terminals1；
In particular, the resistance R2The voltage at both ends is equal to the external input voltage VABThe current i is obtained according to the following algorithm1
Figure BDA0002952038260000061
In the current feedback operational amplifier U1、U2The output current at each z-terminal is as follows:
i2＝i1
Figure BDA0002952038260000062
capacitor C1Plays an integral role in the general interface circuit, so VC1Can be expressed as:
Figure BDA0002952038260000063
Figure BDA0002952038260000064
is the voltage V between the input terminal A and the input terminal BABThe integral value of time is calculated to obtain:
Figure BDA0002952038260000065
Figure BDA0002952038260000066
available multiplier U5Output voltage V ofwComprises the following steps:
Figure BDA0002952038260000067
current feedback operational amplifier U3Current feedback operational amplifier U4The corresponding voltages and currents, respectively, are:
V3x＝V3y＝Vw
V4x＝V4y＝0
i4＝-iAB
therefore, the method can obtain:
Figure BDA0002952038260000068
Figure BDA0002952038260000069
Figure BDA00029520382600000610
wherein the memristor has a memristive memristor
Figure BDA00029520382600000611
Is about
Figure BDA00029520382600000612
Function of alpha1Representing the memory conductance value
Figure BDA00029520382600000613
Rate of change of beta1Representing the memory conductance value
Figure BDA00029520382600000614
Is a from an initial value of1、β1Respectively as follows:
Figure BDA00029520382600000615
the parameters obtained by the above calculation are put into the memory element general simulator of this embodiment, and the input terminal a and the input terminal B are respectively connected to an external circuit to simulate the use of the memristor.
In order to verify the correctness of the memristor imitated by the memory element general simulator of the embodiment, the applicant uses the formula V of the excitation voltageABAsin (2 pi ft) Asin (ω t), obtained
Figure BDA00029520382600000616
Wherein the content of the first and second substances,
Figure BDA00029520382600000617
is a VABThe integral value of time is compared to obtain the magnetic flux of the memristor
Figure BDA0002952038260000071
Amplitude of and
Figure BDA0002952038260000072
in a proportional relationship.
And according to the formula
Figure BDA0002952038260000073
Transform derived algorithm
Figure BDA0002952038260000074
Root of Chinese angelicaAccording to an algorithm
Figure BDA0002952038260000075
At VAB-iABDrawing hysteresis curve in plane, comparing to obtain when exciting voltage VABWhile the amplitude of the magnetic flux is kept constant, the magnetic flux increases with the excitation frequency
Figure BDA0002952038260000076
Is reduced in amplitude, current iABIs also reduced in amplitude, at VAB-iABThe hysteresis loop curve is drawn in the plane to contract inwards.
According to the theoretical analysis, the applicant also adopts Pspice software to carry out simulation experiments, and builds the memory element universal simulator of the embodiment in the Pspice software and puts the following parameters into the simulator: sinusoidal excitation voltage VABIs a VABSin (2 pi ft) (V), capacitance C1＝0.1nF、R1＝45kΩ、R2＝16kΩ、R3＝55kΩ、Vs-2.5V, in each of the current feedback type current feedback operational amplifier and multiplier U5The power supply ends are respectively connected with a direct current power supply voltage with the amplitude of +/-15V.
For a memory device general simulator, current iABThe current flowing between the input end A and the input end B can be directly measured by a meter pen in Pspice software simulation; voltage VABCan also be directly measured.
When the excitation frequencies are 80kHz, 100kHz and 130kHz, respectively, the voltage V between the input terminal A and the input terminal BABAnd current iABThe lissajous phase trace of (a) is shown in fig. 5.
It can be seen that the voltage VABAnd current iABWhen the frequency of the Lissajous phase track is respectively 80kHz, 100kHz and 130kHz, the memory characteristic of a memristor can be achieved, namely the memory resistance reciprocal wmAt VAB-iABKeeping a magnetic hysteresis loop in a shape like a slant '8' in a plane, keeping the amplitude of the voltage unchanged along with the increase of the frequency of the excitation voltage, and keeping the current iABAnd the hysteresis ring shrinks inwards.
In summary, the simulation experiment result is consistent with the theoretical analysis, so the memory device general simulator of the present embodiment can simulate the memory characteristics of the memristor.
Example 2
For memcapacitor, internal state variables of simulator
Figure BDA0002952038260000077
Relationship and memory capacity value CmCan be defined as:
Figure BDA0002952038260000078
Figure BDA0002952038260000079
wherein alpha is2Represents CmSlope of change of beta2Represents CmIs started.
Referring to fig. 3, in the case of applying an excitation voltage between an input terminal a and an input terminal B, matching setting of various parameters in the memory element general simulator of the present embodiment is completed by the following method to simulate the use of a memcapacitor:
will resistance R2Connected in series to the first transformation memory interface T1Between the positive and negative terminals, a resistance C2Connected in series to the second transformation memory interface T2Between the positive end and the negative end, the capacitor C can be obtained by the voltage following characteristic of the current feedback operational amplifier AD8442Voltage across
Figure BDA00029520382600000710
Comprises the following steps:
Figure BDA00029520382600000711
current feedback operational amplifier U3Is equal to its z-terminal input current:
i4＝-iAB
thus passing through the capacitor C2Electric charge of
Figure BDA0002952038260000081
Comprises the following steps:
Figure BDA0002952038260000082
wherein the content of the first and second substances,
Figure BDA0002952038260000083
is flowing through a capacitor C2Current i of4Integration over time, i.e.
Figure BDA0002952038260000084
Figure BDA0002952038260000085
Figure BDA0002952038260000086
Wherein C ismFor memory capacity of a memory vessel, alpha2Representing a memory capacity value CmRate of change of beta2Representing a memory capacity value CmIs a from an initial value of2、β2Respectively as follows:
Figure BDA0002952038260000087
the parameters obtained by the above calculation are put into the memory element general simulator of this embodiment, and the input terminal a and the input terminal B are respectively connected to an external circuit to simulate the use of a memcapacitor.
In order to verify the correctness of the memcapacitor simulated by the memory element general simulator of the embodiment, the applicant shows that the formula V of the excitation voltage is usedABObtaining (2 pi ft) or (ω t) A sin
Figure BDA0002952038260000088
Wherein the content of the first and second substances,
Figure BDA0002952038260000089
is a VABThe integral value of time is compared to obtain the magnetic flux of memory container
Figure BDA00029520382600000810
Amplitude of and
Figure BDA00029520382600000811
in a proportional relationship.
And according to the formula
Figure BDA00029520382600000812
Transform derived algorithm
Figure BDA00029520382600000813
And according to an algorithm
Figure BDA00029520382600000814
At VAB-qABDrawing hysteresis curve in plane, comparing to obtain when exciting voltage VABWhile the amplitude of the magnetic flux is kept constant, the magnetic flux increases with the excitation frequency
Figure BDA00029520382600000815
Is reduced in amplitude, the charge qABBecomes smaller in magnitude at VAB-qABThe hysteresis loop curve is drawn in the plane to contract inwards.
According to the theoretical analysis, the applicant also adopts Pspice software to carry out simulation experiments, and builds the memory element universal simulator of the embodiment in the Pspice software and puts the following parameters into the simulator: sinusoidal excitation voltage VABIs a VABSin (2 pi ft) (V), capacitance C1＝0.25nF、C2＝0.1nF、R1＝3kΩ、R2＝11kΩ、Vs-0.5V, in each of the current feedback type current feedback operational amplifier and the multiplier U5The power supply ends are respectively connected with a direct current power supply voltage with the amplitude of +/-15V.
Because some internal variables to be measured are not easy to be directly detected, the memory element universal simulator of the embodiment adopts an equivalent substitution mode to equivalently substitute measurable data which is in direct proportion to the variables to be measured for the requirement of experimental result analysis. This approach is suitable for Pspice software simulation.
For the memory device general simulator of this embodiment, qABIs a current i flowing between the input terminal A and the input terminal BABThe time integral value is obtained by i based on the current following characteristic of the current feedback operational amplifier AD844AB＝-i4. Capacitor C2The integration function is performed in the general simulator of the memory device
Figure BDA0002952038260000091
Wherein the content of the first and second substances,
Figure BDA0002952038260000092
is a capacitor C2The voltage value at both ends is
Figure BDA0002952038260000093
It can be seen that q isABAnd
Figure BDA0002952038260000094
in a proportional relationship, can be used
Figure BDA0002952038260000095
Equivalent substitution of qABFor calculating, and VABThe voltage between the input end A and the input end B can be directly measured.
When the excitation frequency is 95kHz, 100kHz and 105kHz, the voltage V between the input end A and the input end BABAnd is equivalent to charge qABVoltage of
Figure BDA0002952038260000096
The lissajous phase trace of (a) is shown in fig. 6.
Comparing the trace graphs with the frequencies of 95kHz, 100kHz and 105kHz respectively to obtain the important characteristics of the memcapacitor, namely the memcapacitor value CmAt VAB-qABIn-planeKeeping a hysteresis loop shaped like a diagonal 8, keeping the voltage amplitude constant along with the increase of the frequency of the excitation voltage, and keeping the charge qABThe variation range of (2) is reduced, and the hysteresis ring is contracted inwards.
In summary, the result of the simulation experiment is consistent with the theoretical analysis, so the memory device general simulator of the present embodiment can simulate the memory characteristics of the memory capacitor.
Example 3
For the memristor, the relationship of the internal state variables q- ρ of the simulator and the reciprocal L of the memristive valuem -1Can be defined as:
Figure BDA0002952038260000097
Figure BDA0002952038260000098
wherein alpha is3Represents Lm -1Slope of change of beta3Represents Lm -1Is started.
Referring to fig. 4, under the condition that an excitation voltage is applied between a and B, the matching setting of various parameters in the memory element general simulator of the embodiment is completed by the following method to simulate the use of a memory sensor:
inductor L1Connected in series to the first transformation memory interface T1Between the positive and negative terminals, a resistance R2Connected in series to the second transformation memory interface T2Between the positive end and the negative end, the inductance L can be obtained by the voltage following characteristic of the current feedback operational amplifier AD8441Voltage V acrossABAnd current i1Respectively as follows:
Figure BDA0002952038260000099
wherein the content of the first and second substances,
Figure BDA00029520382600000910
voltage V for memory sensorABIntegration over time.
Current feedback operational amplifier U1C on the z-terminal of1Providing integral operation, current feedback operational amplifier U1The current outputted by the z terminal is equal to the current outputted by the x terminal, so that the current passes through C1The charge q of (a) is:
Figure BDA00029520382600000911
where ρ isABIs a magnetic flux
Figure BDA00029520382600000912
Integration over time.
Available multiplier U5Output voltage V ofwComprises the following steps:
Figure BDA0002952038260000101
current feedback operational amplifier U2Z terminal output voltage V2zCan be expressed as:
Figure BDA0002952038260000102
Figure BDA0002952038260000103
Figure BDA0002952038260000104
wherein L ism -1(rho AB) is the inverse value of the memory inductance value of the magnetic flux memory sensor, alpha3Represents Lm -1Rate of change of beta3Represents Lm -1Is a from an initial value of3、β3Respectively as follows:
Figure BDA0002952038260000105
the parameters obtained by the above calculation are put into the memory element general simulator of this embodiment, and the input terminal a and the input terminal B are respectively connected to an external circuit to be used as a simulated memory sensor.
In order to verify the correctness of the memcapacitor simulated by the memory element general simulator of the embodiment, the applicant shows that the formula V of the excitation voltage is usedABAsin (2 pi ft) ═ Asin (ω t), where,
Figure BDA0002952038260000106
is a VABIntegral value over time, pABIs composed of
Figure BDA0002952038260000107
Integral value over time, and thus the conversion formula can be obtained
Figure BDA0002952038260000108
The integral value rho can be obtained by comparisonABAmplitude of and
Figure BDA0002952038260000109
in a proportional relationship.
And according to the formula
Figure BDA00029520382600001010
Transform derived algorithm
Figure BDA00029520382600001011
And according to an algorithm
Figure BDA00029520382600001012
In that
Figure BDA00029520382600001013
Drawing hysteresis curve in plane, comparing to obtain when exciting voltage VABWhile the amplitude of the magnetic flux is kept constant, the magnetic flux increases with the excitation frequency
Figure BDA00029520382600001014
And integrated value ρ thereofABWill become smaller, making the memory sensing value inverse value Lm -1Gradually approaches beta3In a
Figure BDA00029520382600001015
The hysteresis loop curve is drawn in the plane to contract inwards.
The memory element universal simulator of the present embodiment was built in Pspice software and the following parameters were put in: sinusoidal excitation voltage VABIs a VAB3sin (2 pi ft) (V), capacitance C1＝0.02nF、R1＝3kΩ、R2＝8kΩ、L1＝0.05H、Vs-2.5V, in each of the current feedback type current feedback operational amplifier and multiplier U5The power supply ends are respectively connected with a direct current power supply voltage with the amplitude of +/-15V.
Since some variables to be measured in the memory device general simulator of this embodiment are not easily detected, for the analysis of experimental results, we will use an equivalent substitution method to substitute measurable data, which is directly proportional to the variables to be measured, for the variables to be measured. This approach is suitable for Pspice software simulation.
For the memory sensor simulated by the memory element general simulator of the embodiment, iABThe current flowing between the input end A and the input end B can be directly measured by a meter pen in Pspice software simulation; based on the voltage following characteristic of the current feedback operational amplifier AD844, and the inductance L1Has a voltage of V at both endsABCan derive
Figure BDA0002952038260000111
As can be seen,
Figure BDA0002952038260000112
and i1In a proportional relationship, i can be used1Equivalent substitution
Figure BDA0002952038260000113
For algorithmic calculations.
When the excitation frequencies are 95kHz, 100kHz and 105kHz, respectively, the current iABAnd equivalent to magnetic flux
Figure BDA0002952038260000114
Current i of1The Lissajous phases of (A) are shown in FIG. 7.
Comparing the trace plots at frequencies of 95kHz, 100kHz and 105kHz respectively, important characteristics of the memory sensor can be obtained: memory inductance reciprocal Lm -1At i1-iABThe magnetic hysteresis loop in the shape of an oblique 8 is kept in a plane, and the voltage amplitude is kept unchanged and the magnetic flux is kept constant along with the increase of the frequency of the excitation voltage
Figure BDA0002952038260000115
And ρABThe hysteresis ring contracts inward as it becomes smaller.
In summary, the simulation experiment result is consistent with the theoretical analysis, so the memory device general simulator of the present embodiment can simulate the memory characteristics of the memory sensor.
Has the advantages that: in the above embodiments 1, 2 and 3, only the first transformation memory interface T is changed1Positive and negative end, second conversion memory interface T2The characteristics of a memristor, a memristor capacitor and a memristor can be simulated by the resistor, the capacitor or the inductor which are respectively connected with the positive end and the negative end in series, and the characteristics of the memristor, the capacitor and the inductor can be realized without additional equipment or auxiliary circuits, so that the memristor, the capacitor and the inductor which are obtained through simulation can be flexibly connected with other circuits for use, meanwhile, the circuit structure of the embodiment is simple, the circuit experiment is easy, and the converted memristor, the capacitor and the inductor can present the memory characteristics under the working frequency higher than 100 kHZ. Compared with the prior art, the memristor, the memcapacitor and the meminductor respectively simulated in the embodiments 1, 2 and 3 can reduce the consumption of the frequency in the circuit by 11.8% in the use process, but the simulated memristor, the memcapacitor and the meminductor in the embodiment can be used in the circuit with the frequency of 100kHZ, and are increased by 162 times compared with the existing 0.8kHZ, so that the embodiment has the advantages that the memristor, the memcapacitor and the meminductor are respectively simulated in the embodiments 1, 2 and 3The general memory element simulator can be flexibly used in a circuit with the frequency of 100kHZ, and a memristor, a memory capacitor and a memory sensor which are simulated conveniently are put into industrial production.
It should be finally noted that the above embodiments are only intended to illustrate the technical solutions of the present invention, and not to limit the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention can be modified or replaced with equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims (6)

1. A memory element universal simulator is characterized by comprising a controller, four current feedback operational amplification chips for amplifying signals at high frequency, a multiplier, a power supply, an integrator, a plurality of resistors, a capacitor and an inductor, wherein the four current feedback operational amplifiers are respectively marked as U1、U2、U3、U4Any one of the current feedback operational amplification chips has an x terminal, a y terminal, a p terminal and a z terminal, and the current feedback operational amplification chip U1The y end of the current transformer is divided into two branches, wherein one branch is connected to a current feedback operational amplification chip U3And the other branch is taken as an input end A, and the current feedback operation is used for amplifying the chip U1The x terminal of the first transformation memory interface T1The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation2The x terminal of the first transformation memory interface T1Negative terminal of, the first transformation memory interface T1The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or an inductor in series, and the current feedback operational amplifier chip U2The y end of the current transformer is connected with a current feedback operational amplification chip U, and two branches are divided4And the other branch is taken as an input end B, and a current feedback operation amplification chip U1The z end is grounded through an integrator, and a current feedback operational amplification chip U1P terminal of and multiplier U5X of1End connection, current feedback operational amplification chip U2The z end is grounded through a resistor, and a current feedback operational amplification chip U2P terminal of (A) andmultiplier U5Y of (A) to (B)1End-connected, multiplier U5X of2The end is grounded through a power supply, and a multiplier U5Y of (A) to (B)2The end and the z end are grounded after being connected together, and a multiplier U5W terminal and current feedback operational amplification chip U3The y end of the current feedback operational amplifier chip U is connected with3P end of the p-type amplifier is open-circuited, and the current feedback operation is used for amplifying the chip U3The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation4The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2Negative terminal of, a second transformation memory interface T2The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or a capacitor in series, and the current feedback operational amplifier chip U4P-end open circuit, current feedback operational amplification chip U4The y end of the controller is grounded, the controller is connected with the input end A and the input end B, and the working frequency ranges from 0kHZ to 100 kHZ.
2. The memory element universal simulator of claim 1, wherein the integrator is a capacitor.
3. The memory device universal simulator according to claim 2, wherein the current flowing from the input terminal a is iABCurrent feedback operational amplifier chip U3Has a current of i at the z-terminal5Flow direction to the first conversion memory interface T1Has a current of i as a negative terminal1From current feedback operational amplification chip U4The current flowing out of the z terminal is i6From current feedback operational amplification chip U1The current flowing out of the z terminal is i2From current feedback operational amplification chip U2The current flowing out of the z terminal is i3From current feedback operational amplification chip U3The x terminal of (a) flows a current of i4。
4. The memory device universal simulator of claim 1, wherein if the first transformation memory interface T is1Positive terminal and first transformation memory interface T1Is connected with an electricity in series between the negative terminalsResistance-second transformation memory interface T2Positive terminal and second transformation memory interface T2The other resistor is connected in series between the input end A and the input end B, and then the input end A and the input end B are connected with an external circuit to simulate a memristor.
5. The memory device universal simulator of claim 1, wherein if the first transformation memory interface T is1Positive terminal and first transformation memory interface T1A resistor is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The input end A and the input end B are connected with an external circuit to simulate the memcapacitor.
6. The memory device universal simulator of claim 1, wherein if the first transformation memory interface T is1Positive terminal and first transformation memory interface T1An inductance is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The input end A and the input end B are connected with an external circuit to simulate the memory inductor.
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