CN112134680B - Chaotic circuit based on magnetic control memristor - Google Patents

Chaotic circuit based on magnetic control memristor Download PDF

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CN112134680B
CN112134680B CN202010820774.4A CN202010820774A CN112134680B CN 112134680 B CN112134680 B CN 112134680B CN 202010820774 A CN202010820774 A CN 202010820774A CN 112134680 B CN112134680 B CN 112134680B
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operational amplifier
resistor
multiplier
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output signal
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CN112134680A (en
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阳启帆
董凯锋
曹建瑾
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China University of Geosciences
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China University of Geosciences
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Abstract

The invention provides a chaotic circuit based on a magnetic control memristor, which comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, a capacitor C1, a capacitor C2, a capacitor C3, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, a peripheral resistor and a sinusoidal signal source. The invention has the beneficial effects that: by adding the magnetic control memristor model into the Duffing-Van der pol chaotic oscillator circuit structure, the chaotic system with unique dynamic behaviors is realized, and unique complex chaotic signals can be generated.

Description

Chaotic circuit based on magnetic control memristor
Technical Field
The invention relates to the field of chaotic circuits, in particular to a chaotic circuit based on a magnetic control memristor.
Background
The memristor is a nonlinear circuit element, has natural nonlinearity and plasticity, and can be organically combined with other circuit elements to construct a chaotic oscillating circuit based on the memristor. The chaotic oscillating circuit based on the memristor has an important role in the fields of weak signal detection, secret communication and the like based on the chaotic system due to the unique dynamic behavior of the chaotic oscillating circuit. At present, the chaotic circuit based on the memristor is quite limited in variety, and the enrichment of the chaotic circuit library of the memristor has great practical significance.
Disclosure of Invention
In order to solve the problems, the invention provides a chaotic circuit based on a magnetic control memristor, which comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, a capacitor C1, a capacitor C2, a capacitor C3, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, a peripheral resistor and a sinusoidal signal source;
one end of the resistor R1 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R1 is connected with the output end of the multiplier A1; one end of the resistor R3 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R3 is connected with the output end of the operational amplifier U2; one end of the resistor R5 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R5 is connected with the output end of the operational amplifier U4; one end of the resistor R7 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R7 is connected with the output port of the multiplier A3; one end of the resistor R10 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R10 is connected with the anode of the sinusoidal signal source; one end of the resistor R2 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R2 is connected with the output end of the operational amplifier U1; the non-inverting input end of the operational amplifier U1 is grounded, and the output end of the operational amplifier U1 is connected with the inverting input end of the operational amplifier U2 through a resistor R8;
the resistor R4 and the capacitor C1 are connected in parallel to form a first parallel network, one end of the first parallel network is connected with the inverting input end of the operational amplifier U2, and the other end of the first parallel network is connected with the output end of the operational amplifier U2; the non-inverting input end of the operational amplifier U2 is grounded through a resistor R11, and the output end of the operational amplifier U2 is connected with the inverting input end of the operational amplifier U3 through a resistor R9; one end of the resistor R6 is connected with the inverting input end of the operational amplifier U3, and the other end of the resistor R6 is connected with the output end of the operational amplifier U3; the non-inverting input end of the operational amplifier U3 is grounded, and the output end of the operational amplifier U3 is connected with the inverting input end of the operational amplifier U4 through a resistor R15;
the resistor R12 and the capacitor C2 are connected in parallel to form a second parallel network, one end of the second parallel network is connected with the inverting input end of the operational amplifier U4, and the other end of the second parallel network is connected with the output end of the operational amplifier U4; the non-inverting input end of the operational amplifier U4 is grounded through a resistor R18, and the output end of the operational amplifier U4 is connected with the inverting input end of the operational amplifier U5 through a resistor R16;
one end of the resistor R14 is connected with the inverting input end of the operational amplifier U5, and the other end of the resistor R14 is connected with the output end of the operational amplifier U5; the non-inverting input end of the operational amplifier U5 is grounded, and the output end of the operational amplifier U5 is connected with the inverting input end of the operational amplifier U6 through a resistor R17; the resistor R13 and the capacitor C3 form a third parallel network, one end of the third parallel network is connected with the inverting input end of the operational amplifier U6, and the other end of the third parallel network is connected with the output end of the operational amplifier U6; the non-inverting input end of the operational amplifier U6 is grounded through a resistor R19, and the output end of the operational amplifier U6 is connected with the Y port of the multiplier A4;
the Y port of the multiplier A2 is connected with the output end of the operational amplifier U5, the X port of the multiplier A2 is connected with the output end of the operational amplifier U5, and the output port of the multiplier A2 is connected with the Y port of the multiplier A1; the X port of the multiplier A1 is connected with the output end of an operational amplifier U3; the X port of the multiplier A4 is connected with the output end of the operational amplifier U6, and the output port of the multiplier A4 is connected with the X port of the multiplier A3; the Y port of multiplier a3 is connected to the output of operational amplifier U5.
Further, the working principle of the chaotic circuit is as follows:
inputting a sinusoidal signal V1, and obtaining a first output signal after passing through a summing circuit; the first output signal is integrated through a first integrating circuit to obtain a second output signal; the second output signal is reversed through a first reversing circuit to obtain a third output signal; the third output signal is integrated by a second integrating circuit to obtain a fourth output signal; the fourth output signal is inverted through a second inverting circuit to obtain a fifth output signal; the fifth output signal is integrated by a third integrating circuit to obtain a sixth output signal; the summing circuit comprises a resistor R1, a resistor R3, a resistor R5, a resistor R7, a resistor R10, a resistor R2 and an operational amplifier U1; the first integrating circuit comprises a resistor R8, a resistor R11, a resistor R4, a capacitor C1 and an operational amplifier U2; the first inverting circuit comprises a resistor R9, a resistor R6 and an operational amplifier U3; the second integrating circuit is composed of a resistor R15, a resistor R18, a resistor R12, a capacitor C2 and an operational amplifier U4; the second inverter circuit comprises a resistor R16, a resistor R14 and an operational amplifier U5; the third integrating circuit comprises a resistor R17, a resistor R19, a resistor R13, a capacitor C3 and an operational amplifier U6;
multiplying the sixth output signal by a multiplier A4 to obtain a seventh output signal; multiplying the seventh output signal by the fifth output signal through a multiplier A3 to obtain an eighth output signal; multiplying the fifth output signal by a multiplier A2 to obtain a ninth output signal; multiplying the ninth output signal by the third output signal through a multiplier A1 to obtain a tenth output signal; the second output signal, the fourth output signal, the eighth output signal and the tenth output signal are inversely added to the sinusoidal signal V1 through the summing circuit;
the sinusoidal signal V1 is inversely added to the signals respectively output by the multiplier a1, the multiplier A3, the operational amplifier U2 and the operational amplifier U4 when the sinusoidal signal V1 is not input through the summing circuit, so as to obtain the first output signal.
Further, the magnetically controlled memristor includes the third integration circuit, the multiplier A3, and the multiplier a 4;
further, the mathematical model of the magnetic control memristor is expressed as formula (1):
Figure GDA0003220514660000031
wherein q represents the amount of charge,
Figure GDA0003220514660000032
which represents the magnetic flux, is,
Figure GDA0003220514660000033
the value of (a) is equal to the integral of the voltage at two ends of the magnetic control memristor to the time t, and a and b are two coefficients in the magnetic control memristor model;
the Duffing chaotic oscillator mathematical model is expressed as the following formula (2):
Figure GDA0003220514660000034
wherein x represents the voltage, k represents the damping ratio, γ represents the amplitude of the sinusoidal signal V1, ω represents the angular frequency of the sinusoidal signal V1;
memristor memory conductance value by magnetic control
Figure GDA0003220514660000035
And magnetic flux
Figure GDA0003220514660000036
The relation between the two elements replaces a cubic nonlinear term in a Duffing chaotic oscillator mathematical model, and the following differential equation is obtained as the formula (3):
Figure GDA0003220514660000037
wherein x is1Representing the voltage, x, at the output of the operational amplifier U62Representing the voltage, x, at the output of the operational amplifier U43Represents the output terminal voltage of the operational amplifier U2,
Figure GDA0003220514660000041
by
Figure GDA0003220514660000042
Determine, i.e. that
Figure GDA0003220514660000043
Figure GDA0003220514660000044
The mathematical model of the Van der pol chaotic oscillator is expressed as the formula (4):
Figure GDA0003220514660000045
wherein δ represents a nonlinear damping coefficient;
the differential equation is combined with a Van der pol chaotic oscillator mathematical model, and a secondary nonlinear damping term is added to obtain the memristive chaotic oscillator, wherein the state equation of the memristive chaotic oscillator is expressed as a formula (5):
Figure GDA0003220514660000046
equation (5) represents the following differential equation as equation (6):
Figure GDA0003220514660000047
the technical scheme provided by the invention has the beneficial effects that: by adding the magnetic control memristor model into the Duffing-Van der pol chaotic oscillator circuit structure, the chaotic system with unique dynamic behaviors is realized, and unique complex chaotic signals can be generated.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic structural diagram of a chaotic circuit based on a magnetic control memristor in an embodiment of the present invention;
FIG. 2 shows an embodiment x of the present invention2-x3And (4) phase diagrams.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a chaotic circuit based on a magnetic control memristor.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chaotic circuit based on a magnetic control memristor according to an embodiment of the present invention, where the chaotic circuit includes an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, a capacitor C1, a capacitor C2, a capacitor C3, a multiplier a1, a multiplier a2, a multiplier A3, a multiplier a4, a peripheral resistor, and a sinusoidal signal source;
one end of the resistor R1 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R1 is connected with the output end of the multiplier A1; one end of the resistor R3 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R3 is connected with the output end of the operational amplifier U2; one end of the resistor R5 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R5 is connected with the output end of the operational amplifier U4; one end of the resistor R7 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R7 is connected with the output port of the multiplier A3; one end of the resistor R10 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R10 is connected with the anode of the sinusoidal signal source; one end of the resistor R2 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R2 is connected with the output end of the operational amplifier U1; the non-inverting input end of the operational amplifier U1 is grounded, and the output end of the operational amplifier U1 is connected with the inverting input end of the operational amplifier U2 through a resistor R8;
the resistor R4 and the capacitor C1 are connected in parallel to form a first parallel network, one end of the first parallel network is connected with the inverting input end of the operational amplifier U2, and the other end of the first parallel network is connected with the output end of the operational amplifier U2; the non-inverting input end of the operational amplifier U2 is grounded through a resistor R11, and the output end of the operational amplifier U2 is connected with the inverting input end of the operational amplifier U3 through a resistor R9; one end of the resistor R6 is connected with the inverting input end of the operational amplifier U3, and the other end of the resistor R6 is connected with the output end of the operational amplifier U3; the non-inverting input end of the operational amplifier U3 is grounded, and the output end of the operational amplifier U3 is connected with the inverting input end of the operational amplifier U4 through a resistor R15;
the resistor R12 and the capacitor C2 are connected in parallel to form a second parallel network, one end of the second parallel network is connected with the inverting input end of the operational amplifier U4, and the other end of the second parallel network is connected with the output end of the operational amplifier U4; the non-inverting input end of the operational amplifier U4 is grounded through a resistor R18, and the output end of the operational amplifier U4 is connected with the inverting input end of the operational amplifier U5 through a resistor R16;
one end of the resistor R14 is connected with the inverting input end of the operational amplifier U5, and the other end of the resistor R14 is connected with the output end of the operational amplifier U5; the non-inverting input end of the operational amplifier U5 is grounded, and the output end of the operational amplifier U5 is connected with the inverting input end of the operational amplifier U6 through a resistor R17; the resistor R13 and the capacitor C3 form a third parallel network, one end of the third parallel network is connected with the inverting input end of the operational amplifier U6, and the other end of the third parallel network is connected with the output end of the operational amplifier U6; the non-inverting input end of the operational amplifier U6 is grounded through a resistor R19, and the output end of the operational amplifier U6 is connected with the Y port of the multiplier A4;
the Y port of the multiplier A2 is connected with the output end of the operational amplifier U5, the X port of the multiplier A2 is connected with the output end of the operational amplifier U5, and the output port of the multiplier A2 is connected with the Y port of the multiplier A1; the X port of the multiplier A1 is connected with the output end of an operational amplifier U3; the X port of the multiplier A4 is connected with the output end of the operational amplifier U6, and the output port of the multiplier A4 is connected with the X port of the multiplier A3; the Y port of multiplier a3 is connected to the output of operational amplifier U5.
The working principle of the chaotic circuit is as follows:
inputting a sinusoidal signal V1, and obtaining a first output signal after passing through a summing circuit; the first output signal is integrated through a first integrating circuit to obtain a second output signal; the second output signal is reversed through a first reversing circuit to obtain a third output signal; the third output signal is integrated by a second integrating circuit to obtain a fourth output signal; the fourth output signal is inverted through a second inverting circuit to obtain a fifth output signal; the fifth output signal is integrated by a third integrating circuit to obtain a sixth output signal; the summing circuit comprises a resistor R1, a resistor R3, a resistor R5, a resistor R7, a resistor R10, a resistor R2 and an operational amplifier U1; the first integrating circuit comprises a resistor R8, a resistor R11, a resistor R4, a capacitor C1 and an operational amplifier U2; the first inverting circuit comprises a resistor R9, a resistor R6 and an operational amplifier U3; the second integrating circuit comprises a resistor R15, a resistor R18, a resistor R12, a capacitor C2 and an operational amplifier U4; the second inverter circuit comprises a resistor R16, a resistor R14 and an operational amplifier U5; the third integrating circuit comprises a resistor R17, a resistor R19, a resistor R13, a capacitor C3 and an operational amplifier U6;
multiplying the sixth output signal by a multiplier A4 to obtain a seventh output signal; multiplying the seventh output signal by the fifth output signal through a multiplier A3 to obtain an eighth output signal; multiplying the fifth output signal by a multiplier A2 to obtain a ninth output signal; multiplying the ninth output signal by the third output signal through a multiplier A1 to obtain a tenth output signal; the second output signal, the fourth output signal, the eighth output signal and the tenth output signal are inversely added to the sinusoidal signal V1 through the summing circuit;
the sinusoidal signal V1 is inversely added to the signals respectively output by the multiplier a1, the multiplier A3, the operational amplifier U2 and the operational amplifier U4 when the sinusoidal signal V1 is not input through the summing circuit, so as to obtain the first output signal.
The magnetically controlled memristor comprises the third integrating circuit, the multiplier A3 and the multiplier A4;
the mathematical model of the magnetic control memristor is expressed as the following formula (1):
Figure GDA0003220514660000061
wherein q represents the amount of charge,
Figure GDA0003220514660000071
which represents the magnetic flux, is,
Figure GDA0003220514660000072
the value of (a) is equal to the integral of the voltage at two ends of the magnetic control memristor to the time t, and a and b are two coefficients in the magnetic control memristor model;
the Duffing chaotic oscillator mathematical model is expressed as the following formula (2):
Figure GDA0003220514660000073
wherein x represents the voltage, k represents the damping ratio, γ represents the amplitude of the sinusoidal signal V1, ω represents the angular frequency of the sinusoidal signal V1;
memristor memory conductance value using magnetic control type memory resistor
Figure GDA0003220514660000074
And magnetic flux
Figure GDA0003220514660000075
The relation between the two elements replaces a cubic nonlinear term in a Duffing chaotic oscillator mathematical model, and the following differential equation is obtained as the formula (3):
Figure GDA0003220514660000076
wherein x is1Representing the voltage, x, at the output of the operational amplifier U62Representing the voltage, x, at the output of the operational amplifier U43Represents the output terminal voltage of the operational amplifier U2,
Figure GDA0003220514660000077
by
Figure GDA0003220514660000078
Determine, i.e. that
Figure GDA0003220514660000079
Figure GDA00032205146600000710
The mathematical model of the Van der pol chaotic oscillator is expressed as the formula (4):
Figure GDA00032205146600000711
wherein δ represents a nonlinear damping coefficient;
the differential equation is combined with a Van der pol chaotic oscillator mathematical model, and a secondary nonlinear damping term is added to obtain the memristive chaotic oscillator, wherein the state equation of the memristive chaotic oscillator is expressed as a formula (5):
Figure GDA00032205146600000712
equation (5) is expressed as the following differential equation such as equation (6):
Figure GDA00032205146600000713
referring to FIG. 2, FIG. 2 shows an embodiment x of the present invention2-x3In the present invention, the operational amplifier U1, the operational amplifier U2, the operational amplifier U3, the operational amplifier U4, and the operational amplifier U4 all use the operational amplifier TL082, the multiplier a4, and the multiplier a4 all use the four-quadrant multiplier AD633, the capacitor C4 ═ 100uF, the resistor R4 ═ 20K Ω, the resistor R4 ═ 10K Ω, the resistor R4 ═ 20K Ω, the resistor R4 ═ 220K Ω, the resistor R4 ═ 10K ═ Ω, the resistor R4 ═ 10K ═ 10 Ω, the resistor R4 ═ 4 Ω, the resistor R ═ 4 ═ 36k ═ 4 ═ 10 Ω, the resistor R ═ 36k ═ 4 ═ 10 Ω, the resistor R ═ 36k ═ 10 Ω, the resistor R ═ 4 ═ 36k ═ 4, the resistor R ═ 36k ═ 4 ═ 10 ═ 36k ═ 4, the resistor R ═ 10 ═ 36k ═ 10 Ω, the resistor R ═ 36k ═ 10 ═ 4, the resistor R ═ 36k ═ 4, the resistor R ═ 10 ═ 36k ═ 4, the resistor R ═ 10 ═ 4, the resistor R ═ 10 ═ 36k ═ 10 ═ 3 ═ 36k ═ 4, the resistor R ═ 4, the resistor R ═ 10 Ω, the resistor R ═ 3 ═ 10 Ω, the resistor R ═ 4, the resistor R ═ 10 Ω, the resistor R ═ 10K ═ 4, the resistor R ═ 3 ═ 10 Ω, the resistor R ═ 10K ═ 36k ═ 4, the resistor R ═ 10K ═ 4, the resistor R ═ 10 Ω, the resistor R ═ 36k ═ 10 Ω, the resistor R ═ 4 ═ 36, the values of all parameters are as follows: gamma is 0.5V, omega is 1rad/s,
Figure GDA0003220514660000081
a＝1，
Figure GDA0003220514660000082
as can be seen from FIG. 2, the chaotic circuit based on the magnetic control memristor has unique chaotic dynamic behaviors and can generate unique chaotic signals.
The invention has the beneficial effects that: by adding the magnetic control memristor model into the Duffing-Van derpol chaotic oscillator circuit structure, the chaotic system with unique dynamic behaviors is realized, and unique complex chaotic signals can be generated.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (2)

1. The utility model provides a chaotic circuit based on magnetic control memristor which characterized in that: the chaotic circuit comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, a capacitor C1, a capacitor C2, a capacitor C3, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, a peripheral resistor and a sinusoidal signal source;
one end of the resistor R1 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R1 is connected with the output end of the multiplier A1; one end of the resistor R3 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R3 is connected with the output end of the operational amplifier U2; one end of the resistor R5 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R5 is connected with the output end of the operational amplifier U4; one end of the resistor R7 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R7 is connected with the output port of the multiplier A3; one end of the resistor R10 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R10 is connected with the anode of the sinusoidal signal source; one end of the resistor R2 is connected with the inverting input end of the operational amplifier U1, and the other end of the resistor R2 is connected with the output end of the operational amplifier U1; the non-inverting input end of the operational amplifier U1 is grounded, and the output end of the operational amplifier U1 is connected with the inverting input end of the operational amplifier U2 through a resistor R8;
the resistor R4 and the capacitor C1 are connected in parallel to form a first parallel network, one end of the first parallel network is connected with the inverting input end of the operational amplifier U2, and the other end of the first parallel network is connected with the output end of the operational amplifier U2; the non-inverting input end of the operational amplifier U2 is grounded through a resistor R11, and the output end of the operational amplifier U2 is connected with the inverting input end of the operational amplifier U3 through a resistor R9; one end of the resistor R6 is connected with the inverting input end of the operational amplifier U3, and the other end of the resistor R6 is connected with the output end of the operational amplifier U3; the non-inverting input end of the operational amplifier U3 is grounded, and the output end of the operational amplifier U3 is connected with the inverting input end of the operational amplifier U4 through a resistor R15;
the resistor R12 and the capacitor C2 are connected in parallel to form a second parallel network, one end of the second parallel network is connected with the inverting input end of the operational amplifier U4, and the other end of the second parallel network is connected with the output end of the operational amplifier U4; the non-inverting input end of the operational amplifier U4 is grounded through a resistor R18, and the output end of the operational amplifier U4 is connected with the inverting input end of the operational amplifier U5 through a resistor R16;
one end of the resistor R14 is connected with the inverting input end of the operational amplifier U5, and the other end of the resistor R14 is connected with the output end of the operational amplifier U5; the non-inverting input end of the operational amplifier U5 is grounded, and the output end of the operational amplifier U5 is connected with the inverting input end of the operational amplifier U6 through a resistor R17; the resistor R13 and the capacitor C3 form a third parallel network, one end of the third parallel network is connected with the inverting input end of the operational amplifier U6, and the other end of the third parallel network is connected with the output end of the operational amplifier U6; the non-inverting input end of the operational amplifier U6 is grounded through a resistor R19, and the output end of the operational amplifier U6 is connected with the Y port of the multiplier A4;
the Y port of the multiplier A2 is connected with the output end of the operational amplifier U5, the X port of the multiplier A2 is connected with the output end of the operational amplifier U5, and the output port of the multiplier A2 is connected with the Y port of the multiplier A1; the X port of the multiplier A1 is connected with the output end of an operational amplifier U3; the X port of the multiplier A4 is connected with the output end of the operational amplifier U6, and the output port of the multiplier A4 is connected with the X port of the multiplier A3; the Y port of the multiplier A3 is connected with the output end of an operational amplifier U5;
the magnetically controlled memristor comprises a third integrating circuit, the multiplier A3 and the multiplier A4;
the mathematical model of the magnetic control memristor is expressed as the following formula (1):
Figure FDA0003220514650000021
wherein q represents the amount of charge,
Figure FDA0003220514650000022
which represents the magnetic flux, is,
Figure FDA0003220514650000023
the value of (a) is equal to the integral of the voltage at two ends of the magnetic control memristor to the time t, and a and b are two coefficients in the magnetic control memristor model;
the Duffing chaotic oscillator mathematical model is expressed as the following formula (2):
Figure FDA0003220514650000024
wherein x represents the voltage, k represents the damping ratio, γ represents the amplitude of the sinusoidal signal V1, ω represents the angular frequency of the sinusoidal signal V1;
memristor memory conductance value by magnetic control
Figure FDA0003220514650000025
And magnetic flux
Figure FDA0003220514650000026
The relation between the two elements replaces a cubic nonlinear term in a Duffing chaotic oscillator mathematical model, and the following differential equation is obtained as the formula (3):
Figure FDA0003220514650000027
wherein x is1Representing the voltage, x, at the output of the operational amplifier U62Representing the voltage, x, at the output of the operational amplifier U43Represents the output terminal voltage of the operational amplifier U2,
Figure FDA0003220514650000028
by
Figure FDA0003220514650000029
Determine, i.e. that
Figure FDA00032205146500000210
Figure FDA00032205146500000211
The mathematical model of the Van der pol chaotic oscillator is expressed as the formula (4):
Figure FDA00032205146500000212
wherein δ represents a nonlinear damping coefficient;
the differential equation is combined with a Van der pol chaotic oscillator mathematical model, and a secondary nonlinear damping term is added to obtain the memristive chaotic oscillator, wherein the state equation of the memristive chaotic oscillator is expressed as a formula (5):
Figure FDA0003220514650000031
equation (5) is expressed as the following differential equation such as equation (6):
Figure FDA0003220514650000032
2. the chaotic circuit based on the magnetically controlled memristor according to claim 1, wherein: the working principle of the chaotic circuit is as follows:
inputting a sinusoidal signal V1, and obtaining a first output signal after passing through a summing circuit; the first output signal is integrated through a first integrating circuit to obtain a second output signal; the second output signal is reversed through a first reversing circuit to obtain a third output signal; the third output signal is integrated by a second integrating circuit to obtain a fourth output signal; the fourth output signal is inverted through a second inverting circuit to obtain a fifth output signal; the fifth output signal is integrated by a third integrating circuit to obtain a sixth output signal; the summing circuit comprises a resistor R1, a resistor R3, a resistor R5, a resistor R7, a resistor R10, a resistor R2 and an operational amplifier U1; the first integrating circuit comprises a resistor R8, a resistor R11, a resistor R4, a capacitor C1 and an operational amplifier U2; the first inverting circuit comprises a resistor R9, a resistor R6 and an operational amplifier U3; the second integrating circuit comprises a resistor R15, a resistor R18, a resistor R12, a capacitor C2 and an operational amplifier U4; the second inverter circuit comprises a resistor R16, a resistor R14 and an operational amplifier U5; the third integrating circuit comprises a resistor R17, a resistor R19, a resistor R13, a capacitor C3 and an operational amplifier U6;
multiplying the sixth output signal by a multiplier A4 to obtain a seventh output signal; multiplying the seventh output signal by the fifth output signal through a multiplier A3 to obtain an eighth output signal; multiplying the fifth output signal by a multiplier A2 to obtain a ninth output signal; multiplying the ninth output signal by the third output signal through a multiplier A1 to obtain a tenth output signal; the second output signal, the fourth output signal, the eighth output signal and the tenth output signal are inversely added to the sinusoidal signal V1 through the summing circuit;
the sinusoidal signal V1 is inversely added to the signals respectively output by the multiplier a1, the multiplier A3, the operational amplifier U2 and the operational amplifier U4 when the sinusoidal signal V1 is not input through the summing circuit, so as to obtain the first output signal.
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